WO2015043499A1 - 一种半导体封装结构及其成型方法 - Google Patents
一种半导体封装结构及其成型方法 Download PDFInfo
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- WO2015043499A1 WO2015043499A1 PCT/CN2014/087508 CN2014087508W WO2015043499A1 WO 2015043499 A1 WO2015043499 A1 WO 2015043499A1 CN 2014087508 W CN2014087508 W CN 2014087508W WO 2015043499 A1 WO2015043499 A1 WO 2015043499A1
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- pin
- heat sink
- frame
- chip
- lead frame
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Definitions
- the invention belongs to the field of semiconductor packaging, and in particular relates to a semiconductor package structure and a molding method thereof.
- the lead frame is the skeleton of the semiconductor integrated circuit, and the lead frame is used as the chip carrier of the integrated circuit or the discrete device, and is a key for forming an electrical circuit by electrically connecting the terminal of the chip to the outer lead by means of the key alloy wire.
- the lead frame is mainly composed of two parts: the chip holder and the pin. The chip holder provides mechanical support for the chip during the packaging process, and the pin is the electrical path connecting the chip to the outside of the package.
- the function of the lead frame is obvious. First, it plays a supporting role for the packaged electronic device, while preventing the resin from suddenly escaping between the leads to provide support for the plastic. Secondly, it connects the chip to the substrate, providing the power of the chip circuit board. Hot aisle. When an integrated circuit is used, heat is inevitably generated. In particular, a circuit with a large power consumption generates more heat. Therefore, the lead frame must have good thermal conductivity during operation, otherwise it will work. The chip is burned out due to the large amount of heat and the inability to dissipate in time.
- the main function of the lead frame is to provide a mechanical support carrier for the integrated circuit chip, and to connect the external circuit of the integrated circuit as a conductive medium, transmit electrical signals, and together with the packaging material, dissipate heat generated when the chip operates.
- the existing lead frame is dissipated through the heat sink, but the disadvantage is that due to too many pins on the chip, The heat generation is too slow, and there are many other defects in the combination of the existing lead frame and the heat sink, such as inaccurate combination and inefficiency.
- the Chinese utility model patent CN201629305U discloses a heat dissipation package structure of a lead frame, comprising a lead frame and a heat sink, wherein: a through hole is formed around the lead frame and the through hole is matched with a bump on the heat sink. The lead frame and the heat sink are press-fitted to the bump via the through hole.
- the package structure is connected by bump stamping, but the heat dissipation function is limited.
- An integrated circuit lead frame heat sink is disclosed in the Chinese utility model patent CN202394951U.
- the integrated circuit lead frame heat sink of the utility model has a groove in the middle of the bottom surface of the sheet body, and a groove is matched in the groove.
- the insert is silver plated on the outer surface of the insert.
- the integrated circuit lead frame heat sink has limited heat dissipation function.
- the invention provides a semiconductor package structure with clear and simple structure and good heat dissipation function.
- the invention also provides a semiconductor package structure forming method which at least realizes a clear and simple structure of the package structure and a good heat dissipation function.
- the present invention firstly provides a semiconductor package structure including a heat sink frame and a lead frame, the heat sink frame is connected with a heat sink, a chip is attached to the chip holder of the lead frame, and the heat sink and the chip are connected by a bonding material.
- the lead frame is provided with a first pin
- the heat sink frame is provided with a second pin and a third pin.
- the four first pins on the lead frame are connected to the bottom electrode of the chip holder, which is a current input end; the three second pins on the heat sink frame are connected with the upper surface electrode of the chip, and are current output ends;
- the third pin soldering wire on the heat sink frame is the current control terminal.
- the lead frame is provided with a positioning groove
- the heat sink frame is provided with a positioning leg.
- the lead frame and the heat sink frame are respectively provided with a first link and a second link.
- the invention also provides a semiconductor package structure forming method, which comprises the following steps:
- a semi-etched area is arranged around the chip holder of the lead frame, the first pin is connected to the chip holder, and the chip holder electrode is directly connected to the first pin, and the first pin is provided with the first crawler a tin hole, the lead frame is further provided with a positioning groove and a first connecting rod;
- Soldering chip soldering the chip on the chip holder using a bonding material
- the heat sink frame is provided with a second pin and a third pin, and the second pin and the third pin are respectively provided with a second climbing hole, and the heat sink frame is further provided There is a second connecting rod and a positioning leg, and the heat sink frame is connected with a heat sink;
- Chip soldering fin the bonding fin is used to solder the heat sink to the chip, and the positioning pin on the heat sink frame is inserted into the positioning groove on the lead frame;
- Bonding wire use a wire to connect the third pin to the chip to achieve conduction
- Injection molding a film is applied on the back surface of the lead frame, so that the upper surface of the semiconductor and the surface of the film are attached to the upper and lower surfaces of the abrasive tool during injection molding, and then the surfaces are exposed after the molding;
- the first pin, the second pin, the third pin and the lead frame exposed on the outside of the glue are plated with a tin layer. At this time, the first climbing hole and the second climbing hole are also plated with tin. Floor;
- Cutting the foot The excess lead frame and the heat sink frame, the first link, and the second link are cut off using the mold, and the excess portions of the first pin, the second pin, and the third pin are cut off.
- the fin frame is provided with support legs for balancing the fins on the chip.
- the lead frame is provided with a pin recognition hole.
- the lead frame and the heat sink frame are provided with a back half etching region and a front half etching region.
- the tin layer is contained after the excess portion of the first pin, the second pin and the third pin is cut, and the first pin, the second pin and the third pin are cut.
- the position is the first climbing tin hole and the second climbing tin hole.
- one lead frame is welded with 100 heat sinks each time the solder is soldered.
- the first pin is connected to the bottom electrode of the chip holder and is a current input end; the three second pins on the heat sink frame are connected with the upper surface electrode of the chip, which is a current output end; the third on the heat sink frame
- the pin welding wire is a current control terminal; the wire application is greatly reduced, thereby reducing heat loss.
- the arrangement of the first climbing hole and the second climbing hole enables the tin layer on the sidewall of the cutting foot to be retained, thereby improving the reliability of soldering of the semiconductor and the circuit board.
- FIG. 1 is a schematic structural view of a semiconductor package structure of the present invention
- FIG. 2 is a schematic structural view of a lead frame of the present invention
- Figure 3 is a side view of the lead frame of the present invention.
- FIG. 4 is a schematic structural view of a heat sink frame of the present invention.
- Figure 5 is a side elevational view of the heat sink frame of the present invention.
- the present invention provides a semiconductor package structure including a heat sink frame 2 and a lead frame 1, to which a heat sink 4 is attached, and a chip holder 21 of the lead frame 1 is attached
- the chip 3, the heat sink 4 and the chip 3 are connected together by a bonding material 5, wherein the lead frame 1 is provided with a first pin 22, and the heat sink frame 2 is provided with a second pin 43 and a third pin 44.
- the four first pins 22 of the lead frame 1 are connected to the bottom electrode of the chip holder 21 as a current input terminal; the three second pins 43 on the heat sink frame 2 are connected to the upper surface electrode of the chip 3. It is a current output terminal; the third pin 44 on the heat sink frame 2 is welded with a wire, which is a current control terminal.
- the lead frame 1 is provided with a positioning groove 25, and the heat sink frame 2 is provided with a positioning leg 48. More specifically, the lead frame 1 and the fin frame 2 are provided with a first link 27 and a second link 46, respectively.
- the bonding material 5 is any bonding material known to those skilled in the art as long as it can accomplish its object in the present invention.
- the present invention also provides a semiconductor package structure forming method, which comprises the following steps:
- the lead frame 1 is prepared: a half etching region 23 is disposed around the chip holder 21 of the lead frame 1, and the first pin 22 is connected to the chip holder 21, and the electrode of the chip holder 21 is directly connected to the first pin 22, the first a first climbing hole 24 is disposed on the pin 22, and the lead frame 1 is further provided with a positioning groove 25, a foot recognition hole 26 and a first link 27;
- Soldering chip 3 using the bonding material 5 to solder the chip 3 on the chip holder 21;
- the heat sink frame 2 is provided with a back half etching region 41 and a front half etching region 42, and is provided with a second pin 43 and a third pin 44, a second pin 43 and a third A second climbing hole 45 is disposed on the pin 44.
- the heat sink frame 2 is further provided with a second connecting rod 46, a supporting leg 47 and a positioning leg 48.
- the heat sink frame 2 is connected with a heat sink 4 ;
- the chip 3 is soldered to the heat sink 4: the heat sink 4 is soldered to the chip 3 using the bonding material 5, and the positioning legs 48 on the heat sink frame 2 are inserted into the positioning grooves 25 on the lead frame 1;
- Bonding wire the third pin 44 is connected to the chip 3 by using a wire to achieve conduction
- Injection molding a film is applied on the back surface of the lead frame 1, so that the upper surface of the semiconductor and the surface of the film are attached to the upper and lower surfaces of the abrasive tool during injection molding, and then the double surfaces are exposed after the molding;
- Electroplating the first pin 22, the second pin 43, the third pin 44 and the lead frame 1 exposed outside the glue are plated with a tin layer, at this time, the first climbing hole 24 and the second climbing hole 45 will also be plated with tin;
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
Claims (10)
- 一种半导体封装结构,包括散热片框架和引线框架,所述散热片框架连有散热片,所述引线框架的芯片座上贴有芯片,所述散热片和芯片通过结合材连接在一起,其特征是,所述引线框架设有第一管脚,所述散热片框架上设有第二管脚和第三管脚。
- 根据权利要求1所述一种半导体封装结构,其特征是,所述引线框架上4个第一管脚与芯片座底部电极相连接,为电流输入端;散热片框架上的3个第二管脚与芯片上表面电极相连接,为电流输出端;散热片框架上的第三管脚焊接导线,为电流控制端。
- 根据权利要求2所述一种半导体封装结构,其特征是,所述引线框架上设有定位槽,所述散热片框架上设有定位脚。
- 根据权利要求1所述一种半导体封装结构,其特征是,所述引线框架和散热片框架上分别设有第一连杆和第二连杆。
- 一种半导体封装结构成型方法,其特征是,其包括以下步骤:准备引线框架:所述引线框架的芯片座四周设有半蚀刻区,第一管脚连接芯片座,将芯片座电极直接导通第一管脚,所述第一管脚上设有第一爬锡孔,所述引线框架上还设有定位槽和第一连杆;焊接芯片:使用结合材在芯片座上面焊接芯片;准备散热片框架:所述散热片框架上设有第二管脚和第三管脚,第二管脚和第三管脚上皆设有第二爬锡孔,所述散热片框架上还设有第二连杆和定位脚,所述散热片框架上连有散热片;芯片焊接散热片:使用结合材将散热片与芯片焊接,同时散热片框架上的定位脚插入到引线框架上的定位槽内;焊线:使用导线将第三管脚与芯片连接,实现导通;载入治具烘烤:将焊线后的半导体放入治具,然后送入烤箱烘烤,烘烤后结合材固化,进而半导体整体高度确定;注塑成型:在引线框架背面贴上一次胶膜,从而在注塑的时候半导体上表面和胶膜表面贴合在磨具的上下表面,进而成型后双表面均路出胶体;电镀:将裸露在胶体外的第一管脚、第二管脚、第三管脚和引线框架上镀 上锡层,此时,第一爬锡孔和第二爬锡孔也会镀上锡层;切脚成型:使用模具将多余的引线框架和散热片框架、第一连杆、第二连杆切除,同时将第一管脚、第二管脚和第三管脚多余部分切除。
- 根据权利要求5所述一种半导体封装结构成型方法,其特征是,所述散热片框架上设有用来平衡散热片站立在芯片上的支撑脚。
- 根据权利要求5所述一种半导体封装结构成型方法,其特征是,所述引线框架上设有脚位识别孔。
- 根据权利要求5所述一种半导体封装结构成型方法,其特征是,所述散热片框架上设有背面半蚀刻区和正面半蚀刻区。
- 根据权利要求5所述一种半导体封装结构成型方法,其特征是,在切除第一管脚、第二管脚和第三管脚时切割位置为第一爬锡孔和第二爬锡孔处。
- 根据权利要求5所述一种半导体封装结构成型方法,其特征是,在芯片焊接散热片时,每次焊接时一引线框架焊接100个散热片。
Priority Applications (2)
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JP2016537120A JP2016532297A (ja) | 2013-09-26 | 2014-09-26 | 半導体パッケージ構造及びその成形方法 |
US15/022,055 US9673138B2 (en) | 2013-09-26 | 2014-09-26 | Semiconductor package structure having a heat sink frame connected to a lead frame |
Applications Claiming Priority (2)
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CN201310443963.4A CN103531551A (zh) | 2013-09-26 | 2013-09-26 | 一种半导体封装结构及其成型方法 |
CN201310443963.4 | 2013-09-26 |
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JP (1) | JP2016532297A (zh) |
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CN112117251A (zh) * | 2020-09-07 | 2020-12-22 | 矽磐微电子(重庆)有限公司 | 芯片封装结构及其制作方法 |
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CN103531551A (zh) | 2013-09-26 | 2014-01-22 | 杰群电子科技(东莞)有限公司 | 一种半导体封装结构及其成型方法 |
CN104465597B (zh) * | 2014-12-08 | 2018-02-16 | 杰群电子科技(东莞)有限公司 | 一种四面无引脚扁平半导体器件封装结构及封装方法 |
US20160276185A1 (en) * | 2015-03-17 | 2016-09-22 | Texas Instruments Incorporated | Method and apparatus for making integrated circuit packages |
CN105810648A (zh) * | 2016-05-06 | 2016-07-27 | 上海凯虹科技电子有限公司 | 封装体及封装方法 |
CN106876342A (zh) * | 2016-12-19 | 2017-06-20 | 杰群电子科技(东莞)有限公司 | 一种双面散热半导体元件的制造方法 |
CN107660003B (zh) * | 2017-10-23 | 2024-04-16 | 伟创力电子技术(苏州)有限公司 | 一种散热片加热装置 |
CN110416093A (zh) * | 2018-04-26 | 2019-11-05 | 珠海格力电器股份有限公司 | 一种半导体器件及其封装方法、集成半导体器件 |
CN110661169A (zh) * | 2018-06-28 | 2020-01-07 | 潍坊华光光电子有限公司 | 一种小尺寸低成本smd封装vcsel的制备方法 |
CN113066777A (zh) * | 2021-03-03 | 2021-07-02 | 福建福顺半导体制造有限公司 | 一种高散热型半导体器件结构 |
CN112992819B (zh) * | 2021-04-26 | 2022-03-18 | 佛山市国星光电股份有限公司 | 一种封装器件及其制作方法 |
CN113394177A (zh) * | 2021-08-18 | 2021-09-14 | 瑞能半导体科技股份有限公司 | 半导体封装结构及其制造方法 |
TWI814424B (zh) * | 2022-06-07 | 2023-09-01 | 強茂股份有限公司 | 薄型化半導體封裝件及其封裝方法 |
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Also Published As
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US9673138B2 (en) | 2017-06-06 |
US20160225704A1 (en) | 2016-08-04 |
CN103531551A (zh) | 2014-01-22 |
JP2016532297A (ja) | 2016-10-13 |
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