CN111081671A - 低应力半导体芯片固定结构、半导体器件及其制造方法 - Google Patents
低应力半导体芯片固定结构、半导体器件及其制造方法 Download PDFInfo
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Abstract
本发明公开了一种低应力半导体芯片固定结构、半导体器件及其制造方法,包括芯片、引线框架、导电结合件、陶瓷基板,所述引线框架包括芯片座,芯片座用于承载固定陶瓷基板,陶瓷基板用于固定芯片,包括陶瓷层和金属层,所述陶瓷层面通过导电结合件固定在芯片座上,所述金属层面通过导电结合件与芯片连接。本发明在引线框架上设置陶瓷基板,陶瓷基板包括陶瓷层和金属层,陶瓷层面与引线框架芯片座接触、通过导电结合件将陶瓷基板固定在芯片座上,并将金属层面与芯片连接,利用陶瓷的高机械强度、低热膨胀系数缓冲芯片应力,芯片不易出现翘曲、损坏,提高半导体器件封装良率及可靠性,提高了半导体器件的使用寿命。
Description
技术领域
本发明属于电子器件技术领域,具体涉及一种低应力半导体芯片固定结构、半导体器件及其制造方法。
背景技术
半导体器件通常要经过芯片制造与芯片封装两部分加工过程,因此,芯片自身的特性以及封装技术的优劣都直接决定了半导体器件产品最终的性能。随着芯片制造技术的不断发展,芯片厚度不断减薄,随即芯片的机械强度也越来越差,传统封装结构中芯片通过结合材直接焊接在铜框架上,由于铜材的热膨胀系数较大,会导致封装应力不匹配从而使芯片出现翘曲,导致芯片内部晶胞损伤或因为芯片翘曲出现能带弯曲,导致芯片损坏,无法正常工作。
发明内容
本发明的目的在于克服现有技术中半导体器件由于封装应力不匹配导致芯片翘曲、损坏的问题,提供一种低应力半导体芯片固定结构、半导体器件及其制造方法。
为实现上述目的,本发明采用的技术方案如下:一种低应力半导体芯片固定结构,包括芯片、引线框架,所述引线框架包括芯片座,还包括导电结合件、陶瓷基板,所述芯片座用于承载固定陶瓷基板,陶瓷基板用于固定芯片,包括陶瓷层和金属层,所述陶瓷层面通过导电结合件固定在芯片座上,所述金属层面通过导电结合件与芯片连接。
进一步的,所述陶瓷基板上设置有通孔,导电结合件填充于通孔中。
进一步的,所述通孔设有多个。
进一步的,多个通孔对称布置于陶瓷基板两侧或四周。
进一步的,所述的导电结合件包括锡膏、锡线、纳米银中的任意一种。
进一步的,所述金属层的材质为金属铜。
一种低应力半导体器件,包括上述的低应力半导体芯片固定结构,还包括封装体、键合金属线,所述引线框架还包括引脚,所述封装体通过注塑成型包覆于芯片、键合金属线、引线框架外且引脚部分伸出封装体。
进一步的,所述的芯片包括三个电极,分别为栅极、集电极和发射极,所述引脚包括与芯片电极对应连接的栅极引脚、集电极引脚和发射极引脚。
进一步的,所述芯片的集电极通过导电结合件连接至芯片座上,继而连接至集电极引脚上。
进一步的,所述芯片的栅极、发射极分别通过金属键合线连接至栅极引脚、发射极引脚上。
一种低应力半导体器件的制造封装方法,制备上述的低应力半导体器件,方法如下:
准备芯片和引线框架;
在引线框架上放置陶瓷基板,将陶瓷基板陶瓷层面与引线框架芯片座接触、金属层面用于固定芯片,
通过导电结合件将陶瓷基板固定在引线框架芯片座上,且导电结合件与金属层连接,
将芯片焊接固定在金属层上,使得芯片电性连接至引线框架芯片座上;
将芯片的电极与对应引线框架的引脚通过金属键合线连接;
使用注塑工艺将芯片和引线框架进行封装,将芯片、键合金属线、引线框架封装于封装体中,且引脚部分伸出封装体。
进一步的,导电结合件填充于陶瓷基板上的通孔中,芯片的集电极通过导电结合件连接至至芯片座上,继而连接至集电极引脚上。
进一步的,所述引线框架为联排引线框架,所述联排引线框架包含多个并列连接排布的引线框架,引线框架之间通过连杆连接。
由上述对本发明的描述可知,与现有技术相比,本发明提供的一种低应力半导体芯片固定结构、半导体器件及其制造封装方法,在引线框架上设置陶瓷基板,陶瓷基板包括陶瓷层和金属层,陶瓷层面与引线框架芯片座接触、通过导电结合件将陶瓷基板固定在芯片座上,并将金属层面与芯片连接,利用陶瓷的高机械强度、低热膨胀系数缓冲芯片应力,芯片不易出现翘曲、损坏,提高半导体器件封装良率及可靠性,提高了半导体器件的使用寿命。
附图说明
图1为本发明低应力半导体芯片固定结构示意图;
图2为本发明低应力半导体器件装配示意图。
具体实施方式
以下将结合本发明实施例中的附图对本发明中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅是本发明的一部分实施例,而不是全部的实施例。
如图1所示,一种低应力半导体芯片固定结构,包括芯片1、引线框架2、导电结合件3、陶瓷基板4,所述引线框架包括芯片座21,该芯片座21用于承载固定陶瓷基板4,陶瓷基板4用于固定芯片1,包括陶瓷层41和金属层42,陶瓷基板4可以缓冲芯片应力,防止芯片变形损坏,如常用的锡膏、锡线、纳米银,所述芯片座21包括陶瓷基板4和金属层42,可在高温环境下,将金属层42直接键合在陶瓷基板4上,所述陶瓷层面41通过导电结合件3固定在芯片座21上,所述金属层面42通过导电结合件3与芯片1连接。所述陶瓷基板4上开设有通孔5,导电结合件3填充于通孔5中,所述通孔5设有多个,多个通孔5对称布置于陶瓷基板4两侧或四周,本实施例中设置有2个,对称分布在陶瓷基板4两侧,在陶瓷基板上设置通孔,方便导电结合件3填充,不仅实现了陶瓷基板4与引线框架2的固定,也实现了芯片1与引线框架2的电性连接;所述金属层42的材质为金属铜,采用金属铜,导电性高,焊接性能强,载流能力强,更加方便焊接。
如图2所示,一种低应力半导体器件,包括上述的低应力半导体芯片固定结构,还包括封装体20、金属键合线30,所述引线框架还包括引脚,所述封装体20通过注塑成型包覆于芯片1、金属键合线30、引线框架2外且引脚部分伸出封装体20,为芯片1提供物理及电性保护、应力缓冲和散热作用;所述的芯片1包括三个电极,分别为栅极、集电极和发射极,所述引脚包括与芯片电极对应连接的栅极引脚22、集电极引脚23和发射极引脚24。芯片1的集电极通过填充于通孔5中的导电结合件3连接至集电极引脚23上,芯片的栅极、发射极分别通过金属键合线30连接至栅极引脚22、发射极引脚24上,金属键合线可以采用金属铝线,导电性能高,容易焊接。
一种低应力半导体器件的制造封装方法,制备上述的低应力半导体器件,包括以下步骤:
S1:准备芯片和引线框架,引线框架上还设置有连杆,方便引线框架传送、桥接、支撑,同时引线框架通过连杆并列连接排布形成引线框架阵列,便于批量自动化生产;
S2:在引线框架上放置陶瓷基板,将陶瓷基板陶瓷层面与引线框架芯片座接触、金属层面用于固定芯片;
S3:在陶瓷基板的通孔上涂覆锡膏或锡线或纳米银等形成导电结合件将陶瓷基板固定在引线框架上,且导电结合件与金属层连接,
S4:采用锡膏或锡线或纳米银将芯片焊接固定在金属层上,可采用回流焊设备进行固化焊接,通孔中导电结合件与引线框架连接固定陶瓷基板,同时与金属层连接,实现芯片的集电极与引线框架集电极引脚的连接;
S5:采用冷焊接设备分别将芯片的栅极、发射极通过金属键合线连接至栅极引脚、发射极引脚上;
S6:使用注塑工艺将芯片和引线框架进行封装,将芯片、金属键合线、引线框架封装于封装体中,且引脚部分伸出封装体,待液态封装体固化后,开模并将封装后的半成品半导体器件取出,切割多余的封装体和伸出封装体的连杆,使连接的半导体器件分离。
本发明提供的一种低应力半导体芯片固定结构、半导体器件及其制造方法,在引线框架上设置陶瓷基板,陶瓷基板包括陶瓷层和金属层,陶瓷层面与引线框架芯片座接触、通过导电结合件将陶瓷基板固定在芯片座上,并将金属层面与芯片连接,利用陶瓷的高机械强度、低热膨胀系数缓冲芯片应力,芯片不易出现翘曲、损坏,提高半导体器件封装良率及可靠性,提高了半导体器件的使用寿命。
上述仅为本发明的若干具体实施方式,但本发明的设计构思并不局限于此,凡利用此构思对本发明进行非实质性的改动,均应属于侵犯本发明保护范围的行为。
Claims (13)
1.一种低应力半导体芯片固定结构,包括芯片、引线框架,所述引线框架包括芯片座,其特征在于:还包括导电结合件、陶瓷基板,所述芯片座用于承载固定陶瓷基板,陶瓷基板用于固定芯片,包括陶瓷层和金属层,所述陶瓷层面通过导电结合件固定在芯片座上,所述金属层面通过导电结合件与芯片连接。
2.根据权利要求1所述的低应力半导体芯片固定结构,其特征在于:所述陶瓷基板上设置有通孔,导电结合件填充于通孔中。
3.根据权利要求2所述的低应力半导体芯片固定结构,其特征在于:所述通孔设有多个。
4.根据权利要求3所述的低应力半导体芯片固定结构,其特征在于:多个通孔对称布置于陶瓷基板两侧或四周。
5.根据权利要求1所述的低应力半导体芯片固定结构,其特征在于:所述的导电结合件包括锡膏、锡线、纳米银中的任意一种。
6.根据权利要求1所述的低应力半导体芯片固定结构,其特征在于:所述金属层的材质为金属铜。
7.一种低应力半导体器件,其特征在于:包括权利要求1-6任意一项所述的低应力半导体芯片固定结构,还包括封装体、键合金属线,所述引线框架还包括引脚,所述封装体通过注塑成型包覆于芯片、键合金属线、引线框架外且引脚部分伸出封装体。
8.根据权利要求7所述的低应力半导体器件,其特征在于:所述的芯片包括三个电极,分别为栅极、集电极和发射极,所述引脚包括与芯片电极对应连接的栅极引脚、集电极引脚和发射极引脚。
9.根据权利要求8所述的低应力半导体器件,其特征在于:所述芯片的集电极通过导电结合件连接至芯片座上,继而连接至集电极引脚上。
10.根据权利要求8所述的低应力半导体器件,其特征在于:所述芯片的栅极、发射极分别通过金属键合线连接至栅极引脚、发射极引脚上。
11.一种低应力半导体器件的制造方法,其特征在于,制备权利要求7-10所述的低应力半导体器件,方法如下:
准备芯片和引线框架;
在引线框架上放置陶瓷基板,将陶瓷基板陶瓷层面与引线框架芯片座接触、金属层面用于固定芯片,
通过导电结合件将陶瓷基板固定在引线框架芯片座上,且导电结合件与金属层连接,
将芯片焊接固定在金属层上,使得芯片电性连接至引线框架芯片座上;
将芯片的电极与对应引线框架的引脚通过金属键合线连接;
使用注塑工艺将芯片和引线框架进行封装,将芯片、键合金属线、引线框架封装于封装体中,且引脚部分伸出封装体。
12.根据权利要求11所述的一种半导体器件的制造方法,其特征在于:导电结合件填充于陶瓷基板上的通孔中,芯片的集电极通过导电结合件连接至至芯片座上,继而连接至集电极引脚上。
13.根据权利要求11所述的一种半导体器件的制造方法,其特征在于:所述引线框架为联排引线框架,所述联排引线框架包含多个并列连接排布的引线框架,引线框架之间通过连杆连接。
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