CN215220709U - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN215220709U CN215220709U CN202023032130.3U CN202023032130U CN215220709U CN 215220709 U CN215220709 U CN 215220709U CN 202023032130 U CN202023032130 U CN 202023032130U CN 215220709 U CN215220709 U CN 215220709U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
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- 230000008878 coupling Effects 0.000 claims abstract description 17
- 238000010168 coupling process Methods 0.000 claims abstract description 17
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- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 12
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010931 gold Substances 0.000 claims description 9
- 239000002470 thermal conductor Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052763 palladium Inorganic materials 0.000 claims description 7
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Abstract
本公开的各实施例涉及半导体器件。一种半导体器件,包括至少一个半导体裸片,被电耦合到一组导电引线,以及封装成型材料,成型在至少一个半导体裸片和导电引线之上。导电引线的至少一部分在封装成型材料的后表面处被暴露,以提供导电焊盘。该导电焊盘包括放大的端部,放大的端部至少部分地在封装成型材料之上延伸并且被配置用于耦合到印刷电路板。根据本公开的实施例,提供了改进的半导体器件。
Description
技术领域
本公开涉及半导体器件。
背景技术
半导体器件(诸如集成电路)可以提供有各种类型的封装。例如,方形扁平无引线(QFN)封装和平面网格阵列(LGA)封装是本领域已知的表面安装技术(SMT)封装的示例。
QFN封装是提供有平面引线框架衬底的近芯片级塑料密封封装,其中封装后(例如,底部)侧的周围焊盘被配置为提供与印刷电路板 (PCB)的电连接。因此,引线框架的引线完全包含在封装成型化合物中。QFN封装可以包括一个暴露的热焊盘,以改进从集成电路到印刷电路板的热传递。
LGA封装也具有完全包含在封装成型化合物中的引线,并且包括在封装底侧的(矩形)触点网格。封装上的触点被配置为耦合到PCB 上的触点网格。
QFN和LGA封装(以及其他SMT封装)都没有外部引线,而具有“连接盘”或“焊盘”,可以通过焊料膏或焊料合金直接耦合到PCB 焊盘上进行焊接。安装(焊接)步骤可能很复杂,并且可能导致焊接强度和结构的广泛变化。此外,封装与印刷电路板之间的热膨胀系数不同可能导致焊料材料中的高应力和/或QFN/LGA封装一旦安装在印刷电路板上而产生的高的热疲劳。
在这种情况下,“可湿侧面(wettable flanks)”的使用在本领域是已知的。可湿侧面有助于增加引线的可湿性,通过增加连接盘或焊盘垂直侧的焊料附着面积,提高焊料附着力和整体焊接强度。可湿侧面只能稍微提高焊点的可靠性,并且有助于表面安装过程后焊点的自动光学检测,用于表面安装过程的控制。
因此需要封装的半导体器件提供改进的焊点可靠性和/或对PCB 更强的固定。
本领域中需要有助于提供封装的半导体器件,例如,包括QFN 型或LGA型封装,具有改进的焊点可靠性和/或对印刷电路板更强的固定。
实用新型内容
本公开至少解决了上述缺陷中的一些缺陷或者全部缺陷。
根据本公开的第一方面,提供了一种半导体器件,包括:引线框架,包括一组导电引线;半导体裸片,被电耦合到一组导电引线;以及封装成型材料,在半导体裸片和引线框架的导电引线之上成型,其中导电引线的至少一部分未被封装成型材料覆盖;导电焊盘,在导电引线的、未被封装成型材料覆盖的部分处;其中导电焊盘包括第一放大的端部,第一放大的端部至少部分地在封装成型材料的后表面之上延伸;其中第一放大的端部被配置用于耦合到印刷电路板。
在一些实施例中,导电引线包括嵌入在封装成型材料中的主体部分,并且第一放大的端部在封装成型材料的后表面处从主体部分突出。
在一些实施例中,第一放大的端部在主体部分的侧面的封装成型材料的后表面之上延伸达10μm至100μm的长度。
在一些实施例中,第一放大的端部在主体部分的侧面的封装成型材料的后表面之上延伸达50μm至70μm的长度。
在一些实施例中,半导体器件进一步包括在第一放大的端部上的电镀生长材料层。
在一些实施例中,第一放大的端部包括铜。
在一些实施例中,第一放大的端部包括从由镍、钯和金组成的群组中选择的至少一种金属。
在一些实施例中,第一放大的端部的厚度在10μm至100μm的范围内。
在一些实施例中,第一放大的端部的厚度在50μm至70μm的范围内。
在一些实施例中,半导体器件进一步包括镀在第一放大的端部之上的金属层。
在一些实施例中,金属层包括锡。
在一些实施例中,引线框架进一步包括热导体,半导体裸片被安装到热导体,其中热导体的至少一部分未被封装成型材料覆盖,并且半导体器件进一步包括导热焊盘,导热焊盘在热导体的、未被封装成型材料覆盖的部分处;其中导热焊盘包括第二放大的端部,第二放大的端部至少部分地在封装成型材料的后表面之上延伸;其中相应的放大的端部被配置用于耦合到印刷电路板。
在一些实施例中,半导体器件被配置为方形扁平无引线封装。
在一些实施例中,半导体器件被配置为平面网格阵列封装。
根据本公开的第二方面,提供了一种半导体器件,包括:半导体裸片,被安装到导热焊盘并且被电耦合到一组导电引线;以及封装成型材料,被成型在半导体裸片、导热焊盘和导电引线之上,其中导热焊盘的至少一部分在封装成型材料的后表面处被暴露;其中导热焊盘包括放大的部分,放大的部分至少部分地在封装成型材料的后表面之上延伸,其中放大的部分被配置用于耦合到印刷电路板。
在一些实施例中,导热焊盘包括嵌入在封装成型材料中的主体部分,并且放大的端部从封装成型材料的后表面突出。
在一些实施例中,放大的端部在主体部分的侧面的封装成型材料的后表面之上延伸达10μm至100μm的长度。
在一些实施例中,放大的端部在主体部分的侧面的封装成型材料的后表面之上延伸达50μm至70μm的长度。
在一些实施例中,半导体器件进一步包括在放大的端部上的电镀生长材料层。
在一些实施例中,放大的端部包括从铜、镍、钯和金组成的群组中选择的至少一种金属。
在一些实施例中,放大的端部的厚度在10μm到100μm的范围内。
在一些实施例中,放大的端部的厚度在50μm到70μm的范围内。
在一些实施例中,半导体器件进一步包括镀在放大的端部之上的金属层。
在一些实施例中,金属层包括锡。
根据本公开的实施例,提供了改进的半导体器件。
附图说明
现在将仅通过示例参考附图描述一个或多个实施例,其中:
图1是包括QFN封装的半导体器件的倒置显示的(即,其中后侧朝上)立体视图示例;
图2是图1的半导体器件的后侧视图;
图3A是图2的半导体器件的后侧的部分的放大视图;
图3B是图3A的半导体器件的、安装在印刷电路板上的部分的侧视图;
图4A是根据实施例的半导体器件的后侧的部分的放大视图;
图4B是图4A的半导体器件的、安装在印刷电路板上的部分的侧视图;以及
图5A至图5G是根据实施例的制造半导体器件的方法的步骤的示例。
具体实施方式
一个或多个实施例可以涉及半导体器件(例如,集成电路)。
一个或多个实施例可以涉及制造半导体器件的对应的方法。
一个或多个实施例可以提供一种封装半导体器件(例如,包括 QFN或LGA封装),封装半导体器件包括至少一个半导体裸片,被电耦合到一组导电引线,以及封装成型材料,成型在至少一个半导体裸片和导电引线之上。导电引线的至少一部分在封装成型材料的后表面处暴露,以提供导电焊盘。该导电焊盘可以包括放大的端部,放大的端部至少部分地在封装成型材料之上延伸并且被配置用于耦合到印刷电路板。
在随后的说明书中,示出了一个或多个具体细节,旨在提供对该说明书的实施例的示例的深入理解。实施例可以在没有一个或多个具体细节的情况下获得,或者使用其他方法、部件、材料等获得。在其他情况下,没有详细地说明或描述已知的结构、材料或操作,使得不会模糊实施例的某些方面。
在本说明书的框架中引用“一个实施例”或“一种实施例”旨在指示与实施例相关描述的特定配置、结构或特性被包括在至少一个实施例中。因此,诸如“在一个实施例中”或“在一种实施例中”的短语可以出现在本说明书的一个或多个点中,不一定是指同一个实施例。此外,特定构造、结构或特征可在一个或多个实施例中以任何适当的方式组合。
在本文所附的附图中,相同的部件或元件用相同的参考/数字指示,并且为了简洁起见,不会重复对应的描述。
本文使用的引用仅仅是为了方便而提供的,因此不定义保护的范围或实施例的范围。
通过介绍示例性实施例的详细描述,可以首先参考图1和图2,它们是包括QFN封装的半导体器件10的示例。
尽管为了简洁起见,在本说明书和附图中主要引用QFN封装,但是一个或多个实施例可以被应用于其他类型的“无引线”封装,例如,LGA封装。
作为本领域的现有技术,与附图中不可见的其它元件/特征一起,如本文举例说明的半导体器件10可以包括封装半导体裸片(在图1 和图2中不可见)的封装成型材料100,成型材料100被形成以提供半导体器件10的后(例如,底)侧10A,该后侧10A被配置用于与印刷电路板电气和机械耦合。
如图1和图2所示,一组导电的“连接盘”或“焊盘”12可以在后(或底)侧10A(例如,在其外围)上提供。附加地或备选地,焊盘12可以按照LGA封装中的惯例被布置在后侧10A的整个区域上。焊盘12可以被电耦合到封装在成型材料100中的半导体裸片。
可选地,该封装可以包括在后侧10A上的暴露的热焊盘14。该热焊盘14可以被热耦合到封装在成型材料100中的半导体裸片,以改进集成电路10向外的热传递。
总之,电焊盘12和热焊盘14可以提供集成电路10的引线框架。
两个相邻焊盘12之间的(最小)间距可能受到引线框架制造约束的约束。通常,PCB上对应的焊盘可以更宽和/或间隔更小。例如,图2示出了示例性集成电路10的底视图,该集成电路具有电焊盘12 和热焊盘14(用实线示出),以及焊盘12’和14’的对应的示例性布置,该焊盘可以存在于被配置用于耦合到集成电路10的印刷电路板上。
图3A是集成电路10的后侧10A的部分(例如,图2中所示的部分20)的放大视图示例。图3B是部分20的对应的侧视图,该部分是借助焊接材料32安装在印刷电路板30上的集成电路10的示例,该焊接材料32在集成电路10的电焊盘12与PCB 30上的对应的焊盘 12’之间插入。
应该注意的是,由于焊盘12之间的间距Do(相当地)大于焊盘 12’之间的间距d,集成电路10与PCB 30的机电耦合可能不令人满意。
在如图4A和图4B举例说明的一个或多个实施例中,可以通过增加集成电路10的电焊盘12的面积来提高这种机电耦合的可靠性。
图4A是根据一个或多个实施例的集成电路10的后侧10A的部分20的放大视图示例。图4B是部分20的对应的侧视图,该部分20 是借助焊接材料42安装在印刷电路板30上的集成电路10的示例。
如本文举例说明,在封装材料100成型后,可以选择性地在焊盘 12处提供金属层,以提供焊盘的放大的端部44。因此,该放大的端部44可以部分地在焊盘12与成型材料100之间的界面处的成型材料 100之上(例如,嵌入成型材料中的焊盘的主体部分12的“侧向”)延伸,从而增加了适用于与焊盘12’的电气和/或机械耦合的焊盘的面积。
因此,在一个或多个实施例中,金属材料的(厚的)“基座”可以在由成型材料100暴露的焊盘12和/或焊盘14的表面之上生长,从而提供更大的焊盘(即,在焊盘12之间提供减小的间距Dn,从而增加焊接表面)以及半导体封装100与印刷电路板30之间的平衡。因此,可以提高焊点可靠性并且/或者可以获得集成电路到PCB的更强的固定。
在一个或多个实施例中,放大的端部44可以在借助电镀来成型封装材料100后在焊盘12和/或焊盘14上提供(例如,生长)。
通过电镀来提供放大的端部44可能是有利的,因为它可以有助于在焊盘12和/或焊盘14与成型化合物100之间的界面处的成型化合物100之上(侧向)生长金属44,即,它可以有助于适当地增加焊盘的面积(如图4B中举例说明)。
附加地或备选地,可以使用导致在焊盘12和/或焊盘14处的金属的各向同性生长的任何其它选择性金属沉积技术来形成放大的部分 44。
在一个或多个实施例中,放大的端部44的厚度可以在10μm至 100μm的范围内,优选地在50μm至70μm的范围。
在一个或多个实施例中,放大的端部44可以在成型化合物100 之上(侧向)从焊盘12和/或焊盘14的相应的主体部分与成型化合物 100(参见图4B中的长度Dp)之间的界面延伸大约10μm至100μm,优选地为50μm至70μm。
在一个或多个实施例中,放大的端部44可以包括从铜(Cu)、镍 (Ni)、钯(Pd)和金(Au)中选择的至少一种金属。优选地,放大的端部44包括铜(Cu)。
在一个或多个实施例中,可以在放大的端部44之上提供另一金属层。例如,另一金属层可以包括镀在焊盘12和/或焊盘14处的放大的端部44之上的锡(Sn)。
一个或多个实施例可以提供比先前解决方案(例如,涉及可湿侧面的解决方案)更高的可靠性(例如,使用寿命更长)。
图5A至图5G是根据一个或多个实施例的制造半导体器件的方法的可能步骤的示例。在图5A至图5G中,举例说明了一对半导体器件的制造。
如图5A中举例说明,作为第一制造步骤,可以提供传统的引线框架。针对每个半导体器件,引线框架可以包括裸片焊盘14和相应的引线12。
如图5B中举例说明,可以在引线框架的每个裸片焊盘14上安装至少一个半导体裸片50。例如,半导体裸片50可以经由裸片连接材料52(例如,软焊接裸片连接材料和/或胶水)连接到裸片焊盘14上。
如图5C中举例说明,可以执行线接合以经由接合线54在半导体裸片50与相应的引线12之间提供电耦合。
如图5D中举例说明,封装成型材料100可以被成型以封装半导体裸片50和引线框架,使电焊盘12和热焊盘14暴露在半导体器件的后侧处。
如图5E中举例说明,金属层44可以在封装材料100成型后在焊盘12和/或焊盘14处被提供,从而在封装引线处提供金属“凸点”(放大的端部)。放大的端部44例如可以通过电镀而生长。放大的端部44 的厚度(t)可以在10μm至100μm的范围内,优选地在50μm至 70μm的范围内。放大的端部44的横向延伸(Dp)可以在10μm至 100μm的范围内,优选地在50μm至70μm的范围内。放大的端部 44可以包括从铜(Cu)、镍(Ni)、钯(Pd)和金(Au)中选择的一种或多种金属。
如图5F中举例说明,可以在金属层44之上提供另一金属层56 (例如,通过电镀)。另一金属层56可以包括锡(Sn)。
如图5G中举例说明,如本领域的传统方法,该制造方法可以包括分离半导体器件10(例如,通过沿着锯切线切割或锯切)。
如本文中举例说明,半导体器件(例如,10)可以包括:至少一个半导体裸片(例如,50)至少一个半导体裸片被电耦合(例如54) 到一组导电引线;以及封装成型材料(例如,100),成型在至少一个半导体裸片和导电引线之上,其中导电引线的至少一部分在封装成型材料的后表面处(例如,10A)被暴露,以提供导电焊盘(例如,12、 44)。
如本文中举例说明,导电焊盘可以包括放大的端部(例如,44),放大的端部至少部分地在封装成型材料之上延伸,该放大的端部被配置用于耦合到印刷电路板(例如,30)。
如本文中举例说明,导电焊盘可以包括主体部分(例如,杆状部分或网状部分12),该主体部分被嵌入到封装成型材料中,并且放大的端部可以从封装成型材料突出。
如本文中举例说明,放大的端部可以在所述部分的封装成型材料侧面上延伸达10μm至100μm(例如Dp),优选为50μm至70μm。
如本文中举例说明,放大的端部可以包括电镀生长材料。
如本文中举例说明,放大的端部可包括从铜、镍、钯和金中选择的至少一种金属,优选为铜。
如本文中举例说明,放大的端部的厚度(例如,t)可以在10μm 至100μm的范围内,优选地在50μm至70μm的范围内。
如本文中举例说明,半导体器件可以包括镀在放大的端部之上的金属层(例如,56)。该金属层可以包括锡。
如本文中举例说明,半导体器件可以包括导热焊盘(例如,14)。导热焊盘可以包括相应的放大的端部,放大的端部至少部分地在封装成型材料之上延伸并且被配置用于耦合到印刷电路板。
如本文中举例说明,半导体器件可以包括方形扁平无引线封装或平面网格阵列封装。
如本文中举例说明,一种方法可以包括:提供引线框架,引线框架包括至少一个裸片焊盘和相应的至少一组导电引线;将至少一个半导体裸片安装到至少一个裸片焊盘上;将至少一个半导体裸片电耦合到相应的至少一组导电引线中的导电引线;将封装成型材料成型到至少一个半导体裸片和引线框架上,封装成型材料将导电引线的至少一部分在封装成型材料的后表面处暴露,以提供导电焊盘;并且提供导电焊盘的放大端部,导电焊盘的放大端部至少部分地在封装成型材料之上延伸,放大的端部被配置用于耦合到印刷电路板上。
在不损害基本原理的情况下,细节和实施例可以相对于仅通过示例描述的内容而变化,甚至显著地变化,而不背离保护的范围。
权利要求书是本文相对于实施例提供的技术教学的组成部分。
保护范围由所附权利要求定义。
Claims (24)
1.一种半导体器件,其特征在于,包括:
引线框架,包括一组导电引线;
半导体裸片,被电耦合到所述一组导电引线;以及
封装成型材料,在所述半导体裸片和所述引线框架的所述导电引线之上成型,其中所述导电引线的至少一部分未被所述封装成型材料覆盖;
导电焊盘,在所述导电引线的、未被所述封装成型材料覆盖的所述部分处;
其中所述导电焊盘包括第一放大的端部,所述第一放大的端部至少部分地在所述封装成型材料的后表面之上延伸;
其中所述第一放大的端部被配置用于耦合到印刷电路板。
2.根据权利要求1所述的半导体器件,其特征在于,所述导电引线包括嵌入在所述封装成型材料中的主体部分,并且所述第一放大的端部在所述封装成型材料的所述后表面处从所述主体部分突出。
3.根据权利要求2所述的半导体器件,其特征在于,所述第一放大的端部在所述主体部分的侧面的所述封装成型材料的所述后表面之上延伸达10μm至100μm的长度。
4.根据权利要求2所述的半导体器件,其特征在于,所述第一放大的端部在所述主体部分的侧面的所述封装成型材料的所述后表面之上延伸达50μm至70μm的长度。
5.根据权利要求1所述的半导体器件,其特征在于,进一步包括在所述第一放大的端部上的电镀生长材料层。
6.根据权利要求1所述的半导体器件,其特征在于,所述第一放大的端部包括铜。
7.根据权利要求1所述的半导体器件,其特征在于,所述第一放大的端部包括从由镍、钯和金组成的群组中选择的至少一种金属。
8.根据权利要求1所述的半导体器件,其特征在于,所述第一放大的端部的厚度在10μm至100μm的范围内。
9.根据权利要求1所述的半导体器件,其特征在于,所述第一放大的端部的厚度在50μm至70μm的范围内。
10.根据权利要求1所述的半导体器件,其特征在于,进一步包括镀在所述第一放大的端部之上的金属层。
11.根据权利要求10所述的半导体器件,其特征在于,所述金属层包括锡。
12.根据权利要求1所述的半导体器件,其特征在于,所述引线框架进一步包括热导体,所述半导体裸片被安装到所述热导体,其中所述热导体的至少一部分未被所述封装成型材料覆盖,并且所述半导体器件进一步包括导热焊盘,所述导热焊盘在所述热导体的、未被所述封装成型材料覆盖的所述部分处;其中所述导热焊盘包括第二放大的端部,所述第二放大的端部至少部分地在所述封装成型材料的所述后表面之上延伸;其中相应的所述放大的端部被配置用于耦合到所述印刷电路板。
13.根据权利要求1所述的半导体器件,其特征在于,被配置为方形扁平无引线封装。
14.根据权利要求1所述的半导体器件,其特征在于,被配置为平面网格阵列封装。
15.一种半导体器件,其特征在于,包括:
半导体裸片,被安装到导热焊盘并且被电耦合到一组导电引线;以及
封装成型材料,被成型在所述半导体裸片、所述导热焊盘和所述导电引线之上,其中所述导热焊盘的至少一部分在所述封装成型材料的后表面处被暴露;
其中所述导热焊盘包括放大的端部,所述放大的端部至少部分地在所述封装成型材料的所述后表面之上延伸,其中所述放大的端部被配置用于耦合到印刷电路板。
16.根据权利要求15所述的半导体器件,其特征在于,所述导热焊盘包括嵌入在所述封装成型材料中的主体部分,并且所述放大的端部从所述封装成型材料的所述后表面突出。
17.根据权利要求16所述的半导体器件,其特征在于,所述放大的端部在所述主体部分的侧面的所述封装成型材料的所述后表面之上延伸达10μm至100μm的长度。
18.根据权利要求16所述的半导体器件,其特征在于,所述放大的端部在所述主体部分的侧面的所述封装成型材料的所述后表面之上延伸达50μm至70μm的长度。
19.根据权利要求16所述的半导体器件,其特征在于,进一步包括在所述放大的端部上的电镀生长材料层。
20.根据权利要求16所述的半导体器件,其特征在于,所述放大的端部包括从铜、镍、钯和金组成的群组中选择的至少一种金属。
21.根据权利要求16所述的半导体器件,其特征在于,所述放大的端部的厚度在10μm到100μm的范围内。
22.根据权利要求16所述的半导体器件,其特征在于,所述放大的端部的厚度在50μm到70μm的范围内。
23.根据权利要求16所述的半导体器件,其特征在于,进一步包括镀在所述放大的端部之上的金属层。
24.根据权利要求23所述的半导体器件,其特征在于,所述金属层包括锡。
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