CN102420217B - 多芯片半导体封装体及其组装 - Google Patents

多芯片半导体封装体及其组装 Download PDF

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Publication number
CN102420217B
CN102420217B CN201110348417.3A CN201110348417A CN102420217B CN 102420217 B CN102420217 B CN 102420217B CN 201110348417 A CN201110348417 A CN 201110348417A CN 102420217 B CN102420217 B CN 102420217B
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tube core
die attach
attach pad
substrate
tube
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CN102420217A (zh
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张翠嶶
李德森
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

多芯片半导体封装体及其组装。描述了半导体封装体以及其制造方法。在一个实施例中，该半导体封装体包括具有第一和第二管芯附着垫的基板。第一管芯设置在第一管芯附着垫之上。第二管芯设置在第二管芯附着垫之上。第三管芯设置在第一管芯和第二管芯之间。第三管芯具有第一、第二和第三部分，以使第一部分设置在第一管芯的一部分之上，第二部分设置在第二管芯的一部分之上，并且第三部分设置在第一管芯和第二管芯之间的区域之上。

Description

多芯片半导体封装体及其组装
技术领域
本发明大体上涉及一种半导体封装体，并且尤其涉及一种多芯片半导体封装体及其组装。
背景技术
集成电路芯片通常被包装在封装体中以在环境条件中提供保护，并且能使半导体芯片与其他电子部件(如印刷电路板或者主板)之间电互连。半导体封装体可包括具有引线的支撑引线框、电耦合至该引线框的半导体芯片、以及在该引线框和芯片表面成型的密封材料。
由于低制造成本和高可靠性，引线框封装体用于封装半导体芯片。然而，引线框的成本优势随着封装复杂性的增加而降低。例如，由于封装体尺寸和工艺复杂性的增加，需要多芯片集成的封装体需要使用更昂贵的引线框。
发明内容
这些以及其他问题通常可通过说明本发明的实施例来解决或避免，并取得技术优势。
根据本发明的实施例，半导体封装体包括具有第一和第二管芯附着垫的基板。第一管芯设置在第一管芯附着垫之上。第二管芯设置在第二管芯附着垫之上。具有至少第一、第二和第三部分的第三管芯设置在第一管芯和第二管芯之间，以使第一部分设置在第一管芯的一部分之上，第二部分设置在第二管芯的一部分之上，并且第三部分设置在第一管芯和第二管芯之间的区域之上。
根据本发明的实施例，形成半导体封装体的方法包括附着第一管芯至基板的第一管芯附着垫之上。第二管芯附着至基板的第二管芯附着垫之上。该方法进一步包括将第三芯片附着至第一和第二管芯。在一个或更多实施例中，第三管芯的第一部分附着至第一管芯的第一部分，第三管芯的第二部分附着至第二管芯的第一部分，并且第三管芯的第三部分附着至第一管芯和第二管芯之间的第一区域。
前述已相当概括地概述了本发明实施例的特征，以便可更好地理解以下本发明的详细说明。将在以下说明本发明实施例其他的特征和优点，它们构成本发明权利要求的主题。本领域技术人员应该理解可容易地利用所公开的概念和具体实施例作为用于实现本发明相同目的而变更或设计其他结构或工艺的基础。本领域技术人员还可了解这样同等的构造不脱离所附权利要求所述的本发明的精神和范围。
附图说明
为了更完整地理解本发明及其优势，参考结合附图进行的下面的说明，其中：
图1包括图1a和1b，是根据本发明的实施例的半导体封装体，其中图1a图示了半导体封装体的俯视图，并且图1b图示了半导体封装体的剖视图；
图2图示了根据本发明的实施例使用的引线框基板；
图3图示了根据本发明的实施例的图2的引线框基板的一部分，其中图3a图示了剖视图并且图3b图示了俯视图；
图4包括图4a和4b，图示了根据本发明的实施例的制造阶段的半导体封装体，其中图4a图示了剖视图并且图4b图示了俯视图；
图5图示了根据本发明的实施例的下一制造阶段的半导体封装体的俯视图；
图6包括图6a和6b，图示了根据本发明的实施例的随后的制造阶段的半导体封装体，其中图6a图示了剖视图并且图6b图示了俯视图；
图7包括图7a和7b，图示了根据本发明的实施例的随后的制造阶段的半导体封装体，其中图7a图示了剖视图并且图7b图示了俯视图；
图8图示了根据本发明的实施例成型密封后的下一制造阶段的半导体封装体的剖视图；
图9包括图9a和9b，图示了根据本发明的实施例成型密封后的切割工艺，其中图9a图示了切割前的半导体封装体，而图9b图示了切割后的半导体封装体；
图10图示了其中使用不同厚度芯片的本发明的实施例；
图11包括图11a和11b，图示了在每一个管芯附着垫上设置有不同数目的第一管芯的实施例；
图12图示了根据本发明的实施例的半导体封装体，其中基板的印迹面积减小，尽管管芯附着垫的数目没有减少；以及
图13包括图13a和13b，图示了半导体封装体的实施例，其中不同尺寸的芯片被有效封装。
不同图中的相应数字和符号通常指代相应的部分，除非另有说明。所作的图清楚地说明实施例的相应方面，而并非按比例作图。
具体实施方式
下面详细讨论多个实施例的制作和使用。然而应当认识到，本发明提供了很多适用的发明构思，其可以体现在诸多具体环境中。所讨论的具体实施例仅仅是制作和使用本发明的例证性的具体方式，而并不限制本发明的范围。
将多个芯片集成至单个半导体封装体中需要使用大的管芯垫以支撑所有芯片。可选地，使用多个管芯垫以使每一管芯垫支撑特定芯片。然而，所有这些增加了封装体的尺寸，因而要求使用昂贵的封装技术。例如，越大的封装体需要使用越昂贵的腔成型(cavitymolding)工艺，而越小的封装体可使用越便宜的也称之为地图成型(mapmolding)工艺的模具阵列工艺(MAP)来制造。在多个实施例中，本发明通过使用新的集成策略减小了多芯片半导体封装体的封装体尺寸。这允许比较便宜的地图成型工艺的使用。
在多个实施例中，本发明通过部分地堆叠芯片减小了封装体的尺寸，从而减小了封装体尺寸。在一个或更多实施例中，通过消除引线框中心位置的管芯垫减小了封装体尺寸。
半导体封装体的结构实施例将使用图1进行说明。根据本发明的实施例的半导体封装体的制造方法将使用图2-9进行说明。进一步的结构实施例将使用图10-13进行说明。
根据本发明的实施例，半导体封装体使用图1进行说明。参见图1a，基板10包括第一和第二管芯附着垫11和12。在多个实施例中，基板10包括印刷电路板、陶瓷印刷电路板或凸块芯片载体(BCC)金属载体。
在多个实施例中，基板10包括具有双列扁平无引脚(DFN)(如图1a所示)、方形扁平无引脚(QFN)以及小外型无引脚(SON)框架结构的引线框。引线框是导电的支撑或框架结构，用于牢固地附着半导体器件的管芯或者集成电路(IC)芯片。取决于形成的封装体的类型，引线框的厚度有所不同，例如在约0.1mm至约2mm之间。在多个实施例中，引线框包括约0.05mm至约0.4mm之间的厚度。
在多个实施例中，基板10包括导电金属，如铜、铜合金、或铁镍合金(如“合金42”、殷钢(invar)等)、铝、硅合金、镁、以及包括合金的锌(如黄铜)。基板10的材料基于预期的热、机械和电气特性进行选择。基板10可通过刻蚀和/或冲压工艺形成。
基板10包括底表面上的电气垫，以提供到封装体的电连接。基板10也可包括热垫，以从有源器件向外有效散热。如此，支撑10不仅提供稳定的支撑基底以牢固地附着第一管芯30，而且有助于从第一管芯30向散热器(未示出)和/或可选的热沉(未示出)传输热。
多个接触55设置在第一和第二管芯附着垫11和12的周围。在一个实施例中，半导体封装体包括至少四个设置在第一和第二管芯附着垫11和12上的第一管芯30。在一个实施例中，每一个管芯附着垫具有设置于其上的两个第一管芯30。在一个实施例中，第一管芯30对称地设置于第一和第二管芯附着垫11和12之上。
如图1b所示，第一管芯30通过焊料20耦合至基板10。在多个实施例中，焊料20包括银膏。在多个实施例中，焊料20包括任何合适的导电材料，以耦合基板10至第一管芯30。
如图1a和1b所示，第二管芯50设置在基板10之上。在一个实施例中，第二管芯50包括驱动第一管芯30的驱动电路。因此，在多个实施例中，第二管芯50对称地设置在第一管芯30之间。特别是，如图1a和1b所示，第二管芯50设置在第一管芯30的一部分之上。
在多个实施例中，第一和第二管芯30和50包括模拟、逻辑或功率器件。在一个或更多实施例中，第一管芯30包括功率器件，如功率MOSFET，并且第二管芯50包括用于操作功率MOSFET的电路。
在一个或更多实施例中，第一和第二管芯30和50包括用于汽车应用的器件。在一个实施例中，第一管芯30包括大电流电机功率芯片，并且第二管芯50包括驱动该功率芯片的驱动芯片。在多个实施例的多个汽车和非汽车应用中，第一和第二管芯30和50控制电机的操作。
进一步，在多个实施例中，第一管芯30的每一个并非都相同。在多个实施例中，第一管芯30可为不同类型的管芯，包括不同尺寸和/或功能的管芯。
在多个实施例中，第二管芯50可电耦合至第一管芯30的每一个以及基板10。多个结合垫95设置在第一和第二管芯30和50的每一个上面。多个结合垫95的每个结合垫耦合至第一和第二管芯30和50内的有源电路。
第一多个结合线60耦合第二管芯50至第一管芯30的每一个。第二多个结合线65耦合第二管芯50与基板10上的多个接触55。第一管芯30的每一个通过接触引线75耦合至基板10上的多个接触55。在替代实施例中，接触引线75可仅机械地帮助支撑第一管芯30，而所有的电连接直接形成在基板10中。
在多个实施例中，第一和第二结合线60和65由金制造，但是也可以由铜、铝及其合金制造。在多个实施例中，第一和第二结合线60和65在第一和第二管芯30和50之间或者在第二管芯50与基板10上的多个接触55之间传导功率和/或I/O信号。类似的，接触引线75可以在该第一管芯30和基板10之间传导功率和/或I/O信号。
有利地，通过在第一管芯30之上设置第二管芯50，第一多个结合线60的长度被缩短，减小了电连接的电阻，而且降低了不必要的干扰。因此，由于最终减少了包括电阻、电容和电感的寄生器件，半导体封装体的电性能得以提高。
在多个实施例中，半导体封装体的热性能也被提高了。在一个或更多实施例中，第二管芯50包括温度传感器，以监测半导体封装体的温度。温度升高的主要来源是由于第一管芯30的操作。第一多个结合线60的长度缩短也降低了第二管芯50和第一管芯30之间的热阻。因此，第二管芯50上的温度传感器更有效地传感第一管芯30的温度，从而提高了半导体封装体的热性能。
在基板10之上设置密封剂70(图1b)以覆盖第一和第二管芯30和50。在多个实施例中，密封剂70保护第一和第二管芯30和50以及基板10。密封剂70包括成型材料。在多个实施例中，密封剂70包括聚合物。在一个实施例中，密封剂70包括环氧树脂基成型化合物。
在多个实施例中，在第一管芯30之上放置第二管芯50减小了基板10的面积(印迹(footprint))。有利地，由于减小了基板10的面积，本发明的实施例降低了制造半导体封装体的成本。
根据本发明的实施例的半导体封装体的制造方法将使用图2-9进行说明。
图2图示了包括多个管芯附着垫11a/12a-11f/12f的基板10。图3，其包括图3a和3b，图示了图2所示的基板10的近视图。基板10使用包括刻蚀和/或冲压的常规技术来制造。如图3所示，基板10包括管芯附着垫11/12用以固定芯片。多个接触55邻近管芯附着垫11/12设置，并且没有电耦合至管芯附着垫11/12。多个接触55耦合至基板10背面上的外部接触(未示出)。
图4，其包括图4a和图4b，图示了在基板10上安装了第一管芯30后的半导体封装体。载带90可附着至基板10的底表面以支撑基板10以易于处理。在第一管芯30的顶表面上施加焊膏。在多个实施例中，焊膏包括银膏。参见图4，第一管芯30设置在管芯附着垫11/12之上(例如，图4b，其表示俯视图)。封装体被加热以回流焊膏形成焊料20(例如，图4a，其表示剖视图)。在一个或更多实施例中，焊料20与第一管芯30的顶表面上暴露的金属层形成第一共晶合金，并与基板10的顶表面上暴露的金属层形成第二共晶。因此，只有第一管芯30和基板10上的暴露金属层电耦合至焊料20。
接下来，如图5所示，第一管芯30的每一个通过接触引线75耦合至基板10上的多个接触55。从而，第一管芯30耦合至基板10背面上的外部接触。
参见图6，第二管芯50结合至第一管芯30。如图6b的俯视图所示，第二管芯50对称地设置在第一管芯30之间并且在其上。在多个实施例中，只有第二管芯50的一部分与第一管芯30重叠。第二管芯50的其余部分设置在如图6a的剖视图所示的第一管芯30之间的间隙之上。
第二管芯50利用粘合剂膜40附着至第一管芯30(图6a和6b)。在多个实施例中，粘合剂膜40为电绝缘体，例如包括聚合物材料。第二管芯50的背面预层积有粘合剂膜40。在一个实施例中，第二管芯的背面与具有有源器件的顶面相对。在多个实施例中，粘合剂膜40施加在第二管芯50的背面。加热半导体封装体以固化粘合剂膜40，使第一和第二管芯30和50之间形成物理结合。
图7，其包括图7a和7b，图示了形成线结合之后的半导体封装体，其中图7a为剖视图并且图7b为俯视图。
参见图7a，第一多个结合线60耦合第二管芯50至第一管芯30的每一个。第一多个结合线60耦合第一和第二管芯30和50上的结合垫95，从而将第一管芯30与第二管芯50电耦合。在一个实施例中，第一多个结合线60附着至第二管芯50上的结合垫95。随后，第一多个结合线60的相对的未附着端(自由端)附着至第一管芯30上的结合垫95。
如图7b所示，形成第二多个结合线65以将第二管芯50上的结合垫95与基板10上的多个接触55电耦合。在一个实施例中，第二多个结合线65附着至第二管芯50上的结合垫95。随后，第二多个结合线65的相对的未附着端(自由端)附着至基板10上的多个接触55。
在多个实施例中，第一和第二结合线60和65由金制造，但是也可由铜、铝及其合金制造。线结合在约150℃至约250℃下实施。
参见图8，形成密封剂70以保护半导体封装体。基板10、第一和第二管芯30和50被成型化合物覆盖。在一个实施例中，成型化合物包括液体环氧树脂，其可以填充在第二管芯50之下且第一管芯30之间的间隙中。在一个或更多实施例中，液体环氧树脂可注入进该间隙中。随后进行固化工艺。成型固化工艺在约200℃至约400℃之间实施。
图9，其包括图9a和9b，图示了根据本发明的实施例的形成半导体封装体的锯割工艺。
图9a图示了处于如图8所示的相同工艺阶段的半导体封装体。然而，图9a图示了两个半导体封装体，图8图示了表现仅具有两个管芯附着垫的基底10的一部分的放大示图。
在具有载带90的实施例中，载带90被移除以暴露半导体封装体的底表面。
接下来实施修边工艺。在修边时，突出封装体边缘的或在封装体的其他不希望的部位(如引线或热沉等)上的多余成型材料被移除。该多余的成型材料也称为毛边(flash)，如果不去除则可导致严重的电或者甚至热特性退化。在多个实施例中，修边工艺可利用化学或机械工艺来实施。修边工艺的例子包括喷水器的使用并且在化学溶液中浸泡。在一些实施例中，可使用激光修边工艺。
半导体封装体的底表面使用锡进行电镀以形成外部接触。如上所述的修边工艺可被改进以防止电镀步骤期间任何晶须的生长。在多个实施例中，半导体封装体的外部引线使用锡进行电镀。在多个实施例中，电镀材料包括Sn、Sn-Ag、Sn-Sb、以及其组合。在替代实施例中，电镀材料可包括Pt、Ag、Au、以及其组合。
如接下来图9b所示，半导体封装体被分开或单个化(singulate)。在一个实施例中，单个封装体通过锯割被单个化。可选地，在一些实施例中，可使用化学工艺将封装体单个化成单独的单元。
图10图示了半导体封装体的实施例，其中使用了不同厚度的芯片。
尽管前面已经描述了具有大约相同厚度的芯片的半导体封装体的形成方法，本发明的实施例还包括具有不同厚度的芯片的封装体。例如，如图10所示，第一芯片31与第二芯片32具有不同的厚度。因此，尽管第一和第二芯片31和32两者设置在具有共面表面的管芯附着垫11/12之上，但是第一和第二芯片31和32的顶表面不是共面的。尽管有这些差异，本发明的实施例在将第二管芯50附着至第一和第二芯片31和32方面不存在任何问题。这是因为，固化期间粘合剂膜40将形成基本上平坦的顶表面，和/或即使表面不平坦也能粘附。进一步，粘合剂膜40是柔性的，并可经受变形。
图11，其包括图11a和11b，图示了在每一个管芯附着垫之上设置不同数目的第一管芯30的实施例。图11a说明了显示两个第一管芯30和设置在两个第一管芯30之间且在其上的第二管芯50的实施例。图11b说明了显示六个第一管芯30和设置在六个第一管芯30之上的第二管芯50的实施例。
尽管在此实施例中，只显示了两个或六个管芯，然而在多个实施例中，可使用其他数目的管芯。例如，在不同实施例中，可使用八个或十个第一管芯30，单个第二管芯50部分地覆盖他们，如其他实施例所述。
进一步，仅示出了基板在两个相对边缘上具有的两排接触。然而，在一些实施例中，基板10可在所有四边都具有接触。
在替代实施例中，可使用多个第二管芯50，尽管在之前描述的实施例中仅显示出一个第二管芯50。在一个实施例中，两个第二管芯50设置在四个第一管芯30之上，以使每对第一管芯30均有设置其上的第二管芯50。可选地，在一个实施例中，两个第二管芯50设置在八个第一管芯30之上，以使每组四个第一管芯30具有设置其上的第二管芯50。
图12图示了根据本发明的实施例的半导体封装体，其中基板的印迹的面积减少，尽管管芯附着垫的数目并没有减少。图12说明了显示出设置在三个管芯附着垫11/12/13之上的两个第一管芯30的发明的实施例。然而，第二管芯50设置在第一管芯30之上并且在内部管芯附着垫12之上。由于改进的封装，尽管使用三个管芯附着垫，半导体封装体的总的印迹减少。在一个或更多实施例中，可使用多个结合线使第一管芯与基板10接触。
图13，其包括图13a和13b，说明了其中不同尺寸的芯片被有效封装在半导体封装体中的实施例。
参见图13a，第一管芯30(第一芯片31和第二芯片32)设置在两个管芯附着垫11/12之上。第二管芯50设置在第一管芯30之上。第三管芯110设置在第二管芯50之上，以使第三管芯110被第二管芯50支撑。
在多个实施例中，封装体可要求第三管芯110例如通过结合线60耦合至第一和第二管芯30和50的每一个。可选地，在一些实施例中，第三管芯110仅耦合至第一或第二管芯30或50中的每一个。
如图13b所示，在替代实施例中，第三管芯110与第二管芯50设置在同一水平，以使第三管芯110被第一管芯30支撑。
当第一管芯远大于第二和第三管芯50和110时，图13所示的实施例是有益的。可选地，在一些实施例中，第二和第三管芯50和110可设置在第一管芯30之上的同一水平。
尽管已详细说明了本发明及其优点，应该理解在此可作出多种变化、代替和变更而不脱离由所附权利要求所定义的精神和范围。例如，本领域技术人员可容易理解在此说明的许多特征、功能、工艺和材料是可以变化的，然而保持在本发明的范围之内。
此外，本申请的范围不限于在说明书所描述的工艺、机器、制备、物质组成、装置、方法和步骤的具体实施例。如本领域一般技术人员可从本发明的公开容易到理解，可以根据本发明利用当前存在的或以后将被开发的与在此描述的对应实施例表现出实质相同的功能或达到实质相同结果的工艺、机器、制备、物质组成、装置、方法或步骤。因此，所附权利要求意于将这样的工艺、机器、制备、物质组成、装置、方法或步骤包括在它们的范围内。

Claims (25)

1.一种半导体封装体，包括：
包括第一和第二管芯附着垫的基板；
设置在该第一管芯附着垫之上的第一管芯；
设置在该第二管芯附着垫之上的第二管芯，其中该第一管芯设置在该第一管芯附着垫的第一部分之上并且设置在该第二管芯附着垫的第一部分之上，其中该第二管芯设置在该第二管芯附着垫的第二部分之上并且设置在邻近第二管芯附着垫的第三管芯附着垫的第一部分之上；
设置在该第一和第二管芯之间的第三管芯，该第三管芯的第一部分设置在该第一管芯的第一部分之上，该第三管芯的第二部分设置在该第二管芯的第一部分之上，并且该第三管芯的第三部分设置在该第一和第二管芯之间的第一区域之上。
2.如权利要求1的封装体，进一步包括：
设置在该第一管芯附着垫之上的第四管芯，该第四管芯邻近该第一管芯设置，其中该第三管芯的第四部分设置在该第四管芯的一部分之上；
设置在该第二管芯附着垫之上的第五管芯，该第五管芯邻近该第二管芯设置，其中该第三管芯的第五部分设置在该第五管芯的一部分之上，并且其中该第三管芯的第六部分设置在该第四管芯和该第五管芯之间的第一区域之上。
3.如权利要求2的封装体，进一步包括：
设置在该第一管芯附着垫之上的第六管芯，该第六管芯邻近该第一管芯设置，其中该第三管芯的第七部分设置在该第六管芯的一部分之上；
设置在该第二管芯附着垫之上的第七管芯，该第七管芯邻近该第二管芯设置，其中该第三管芯的第八部分设置在该第七管芯的一部分之上，并且其中该第三管芯的第九部分设置在该第六管芯和该第七管芯之间的第一区域之上。
4.如权利要求3的封装体，其中该第一管芯设置于该第四和第六管芯之间，其中该第二管芯设置于该第五和第七管芯之间。
5.如权利要求1的封装体，进一步包括：
设置在该第一管芯和该第二管芯之间的第四管芯，该第四管芯的第一部分设置在该第一管芯的第二部分之上，该第四管芯的第二部分设置在该第二管芯的第二部分之上，并且该第四管芯的第三部分设置在该第一管芯和该第二管芯之间的第二区域之上。
6.如权利要求5的封装体，进一步包括：
设置在该第一和该第二管芯之间的第五管芯，该第五管芯的第一部分设置在该第一管芯的第三部分之上，该第五管芯的第二部分设置在该第二管芯的第三部分之上，并且该第五管芯的第三部分设置在该第一管芯和该第二管芯之间的第三区域之上。
7.如权利要求6的封装体，其中该第一和第二管芯具有第一尺寸，其中该第三和第四管芯具有不同于该第一尺寸的第二尺寸，并且其中该第五管芯具有不同于该第一和第二尺寸的尺寸。
8.如权利要求5的封装体，进一步包括：
设置在该第一和该第二管芯之间的第五管芯，该第五管芯的第一部分设置在该第三管芯的该第三部分的区域之上，该第五管芯的第二部分设置在该第四管芯的该第三部分的区域之上，并且该第五管芯的第三部分设置在该第三管芯和该第四管芯之间的第一区域之上。
9.如权利要求8的封装体，其中该第一和第二管芯具有第一尺寸，其中该第三和第四管芯具有不同于该第一尺寸的第二尺寸，并且其中该第五管芯具有不同于该第一和第二尺寸的尺寸。
10.如权利要求1的封装体，其中该第一管芯通过第一连接器耦合至该基板上的第一接触引线，其中该第二管芯通过第二连接器耦合至该基板上的第二接触引线，并且其中该第三管芯通过结合线耦合至该基板上的第三接触引线。
11.如权利要求1的封装体，其中第一多个结合线将该第三管芯与该第一管芯耦合，并且其中第二多个结合线将该第三管芯与该第二管芯耦合。
12.如权利要求1的封装体，其中该基板为引线框。
13.如权利要求1的封装体，其中该基板为双列扁平无引脚引线框。
14.如权利要求1的封装体，其中该基板、该第一、第二以及第三管芯被成型材料密封。
15.如权利要求1的封装体，进一步包括：
设置在该第一管芯附着垫之上的第四管芯；
设置在该第二管芯附着垫之上的第五管芯；
设置在该第四和第五管芯之间的第六管芯，该第六管芯的第一部分设置在该第四管芯的第一部分之上，该第六管芯的第二部分设置在该第五管芯的第一部分之上，并且该第六管芯的第三部分设置在该第四管芯和该第五管芯之间的第一区域之上。
16.一种半导体封装体，包括：
包括第一和第二管芯附着垫的基板；
设置在该第一管芯附着垫之上的第一管芯；
设置在该第二管芯附着垫之上的第二管芯，其中该第一管芯设置在该第一管芯附着垫的第一部分之上并且设置在该第二管芯附着垫的第一部分之上，其中该第二管芯设置在该第二管芯附着垫的第二部分之上并且设置在邻近第二管芯附着垫的第三管芯附着垫的第一部分之上；
设置在该第一和第二管芯之间的第三管芯，该第三管芯的第一部分设置在该第一管芯的第一部分之上，该第三管芯的第二部分设置在该第二管芯的第一部分之上，并且该第三管芯的第三部分设置在该第一和第二管芯之间的第一区域之上；
设置在该第一管芯附着垫之上的第四管芯，该第四管芯邻近该第一管芯设置，其中该第三管芯的第四部分设置在该第四管芯的一部分之上；以及
设置在该第二管芯附着垫之上的第五管芯，该第五管芯邻近该第二管芯设置，其中该第三管芯的第五部分设置在该第五管芯的一部分之上，并且其中该第三管芯的第六部分设置在该第四管芯和该第五管芯之间的第一区域之上。
17.如权利要求16的封装体，进一步包括：
设置在该第一管芯附着垫之上的第六管芯，该第六管芯邻近该第一管芯设置，其中该第三管芯的第七部分设置在该第六管芯的一部分之上；
设置在该第二管芯附着垫之上的第七管芯，该第七管芯邻近该第二管芯设置，其中该第三管芯的第八部分设置在该第七管芯的一部分之上，并且其中该第三管芯的第九部分设置在该第六管芯和该第七管芯之间的第一区域之上。
18.如权利要求17的封装体，其中该第一管芯设置于该第四和第六管芯之间，其中该第二管芯设置于该第五和第七管芯之间。
19.如权利要求16的封装体，其中该第四管芯设置在该第一管芯附着垫的第二部分之上并且设置在该第二管芯附着垫的第三部分之上，并且其中该第五管芯设置在该第二管芯附着垫的第四部分之上并且设置在该第三管芯附着垫的第二部分之上。
20.如权利要求16的封装体，其中该第一管芯通过第一连接器耦合至该基板上的第一接触引线，其中该第二管芯通过第二连接器耦合至该基板上的第二接触引线，其中该第三管芯通过结合线耦合至该基板上的第三接触引线，其中该第四管芯通过第三连接器耦合至该基板上的第四接触引线，并且其中该第五管芯通过第四连接器耦合至该基板上的第五接触引线。
21.如权利要求16的封装体，其中第一多个结合线将该第三管芯与该第一管芯耦合，其中第二多个结合线将该第三管芯与该第二管芯耦合，其中第三多个结合线将该第三管芯与该第四管芯耦合，并且其中第四多个结合线将该第三管芯与该第五管芯耦合。
22.一种制造半导体封装体的方法，该方法包括：
将第一管芯附着至基板的第一管芯附着垫之上；
将第二管芯附着至该基板的第二管芯附着垫之上，其中该第一管芯设置在该第一管芯附着垫的第一部分之上并且设置在该第二管芯附着垫的第一部分之上，其中该第二管芯设置在该第二管芯附着垫的第二部分之上并且设置在邻近第二管芯附着垫的第三管芯附着垫的第一部分之上；以及
将第三管芯附着至该第一和第二管芯，其中该第三管芯的第一部分附着至该第一管芯的第一部分，其中该第三管芯的第二部分附着至该第二管芯的第一部分，并且其中该第三管芯的第三部分附着至该第一和第二管芯之间的第一区域。
23.如权利要求22的方法，其中附着该第一和第二管芯包括：
在该第一和第二管芯的表面施加焊膏；
将该第一和第二管芯放置在该第一和第二管芯附着垫之上；以及
加热该焊膏以形成焊料。
24.如权利要求22的方法，其中附着该第三管芯包括：
在该第三管芯的表面上施加粘合剂膜；以及
固化该粘合剂膜。
25.如权利要求22的方法，进一步包括：
线结合以将该第三管芯与该基板耦合并且将该第三管芯与该第一和第二管芯耦合；
使用成型材料覆盖该第一、第二和第三管芯；
固化该成型材料以形成密封剂；
修边以去除任何多余的密封剂；
电镀该基板的接触引线；以及
单个化该被密封的基板。
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