CN103531551A - 一种半导体封装结构及其成型方法 - Google Patents

一种半导体封装结构及其成型方法 Download PDF

Info

Publication number
CN103531551A
CN103531551A CN201310443963.4A CN201310443963A CN103531551A CN 103531551 A CN103531551 A CN 103531551A CN 201310443963 A CN201310443963 A CN 201310443963A CN 103531551 A CN103531551 A CN 103531551A
Authority
CN
China
Prior art keywords
pin
lead frame
fin
chip
framework
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310443963.4A
Other languages
English (en)
Inventor
曹周
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Great Team Backend Foundry Dongguan Co Ltd
Original Assignee
Great Team Backend Foundry Dongguan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Great Team Backend Foundry Dongguan Co Ltd filed Critical Great Team Backend Foundry Dongguan Co Ltd
Priority to CN201310443963.4A priority Critical patent/CN103531551A/zh
Publication of CN103531551A publication Critical patent/CN103531551A/zh
Priority to JP2016537120A priority patent/JP2016532297A/ja
Priority to PCT/CN2014/087508 priority patent/WO2015043499A1/zh
Priority to US15/022,055 priority patent/US9673138B2/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75272—Oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75703—Mechanical holding means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/8321—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开一种半导体封装结构及其成型方法，所述半导体封装结构包括包括散热片框架和引线框架，所述散热片框架连有散热片，所述引线框架的芯片座上贴有芯片，所述散热片和芯片通过结合材连接在一起，所述引线框架设有第一管脚，所述散热片框架上设有第二管脚和第三管脚。所述半导体封装结构成型方法将第二管脚、第三管脚设置在散热片上面，第一管脚与芯片座底部电极相连接，为电流输入端；散热片框架上的3个第二管脚与芯片上表面电极相连接，为电流输出端；散热片框架上的第三管脚焊接导线，为电流控制端，大大减少了导线的应用，减少了作业流程加速了散热；注塑成型后，半导体双面均露出胶体，实现双面散热，提高半导体的散热功能。

Description

一种半导体封装结构及其成型方法
技术领域
本发明属于半导体封装领域，具体涉及一种半导体封装结构及其成型方法。
背景技术
近些年来，半导体器件的集成度越来越高，而且其存储量、信号处理速度和功率急速发展，但体积却越来越小，这一趋势加速了半导体集成电路的高速发展。其中，引线框架是半导体集成电路的骨架，引线框架作为集成电路或分立器件的芯片载体，是一种借助于键合金丝实现芯片内部电路引出端与外引线的电气连接，形成电气回路的关键结构件，它起到了和外部导线连接的桥梁作用。引线框架主要由两部分组成：芯片座和引脚。其中芯片座在封装过程中位芯片提供机械支撑，而引脚则是连接芯片到封装外的电学通路。引线框架的功能是显而易见的，首先它起到了封装电子器件的支撑作用，同时防止树脂在引线间突然涌出，为塑料提供支撑；其次它使芯片连接到基板，提供了芯片线路板的电及热通道。集成电路在使用时，不可避免的会产生热量，尤其是功耗较大的电路，产生的热量就更加大，因此在工作时就要求引线框架必须具有很好的导热性，否则在工作中就会由于热量较大且不能及时发散出去而烧坏芯片。引线框架的主要功能是为集成电路芯片提供机械支撑载体，并且作为导电介质连接集成电路外部电路，传送电信号，以及与封装材料一起，向外散发芯片工作时产生的热量。
现有导线框架通过散热片来进行散热，但缺点是由于芯片上管脚过多，造成热量散发过慢，同时现有导线框架与散热片的结合还有很多其他缺陷，比如：结合不精确、效率低下等。
中国实用新型专利说明书CN201629305U中公开了一种引线框架的散热封装结构，包括一引线框架及散热片，其特征在于：所述引线框架四周开设有通孔与所述通孔配合在散热片上开设有凸块，所述引线框架及散热片经通孔与凸块冲压卡合连接。所述封装结构通过凸块冲压卡合连接这种方式，散热功能有限。
中国实用新型专利说明书CN202394951U中公开了集成电路引线框架散热片，本实用新型的集成电路引线框架散热片，在片体底面中部设一个凹槽，在凹槽内设有一个与凹槽匹配一致的镶件，在镶件的外表面上镀银层。所述集成电路引线框架散热片散热功能有限。
发明内容
本发明提供一种半导体封装结构，一种构造清晰简洁、散热功能良好的半导体封装结构；本发明同时提供一种半导体封装结构的成型方法，一种至少实现封装结构构造清晰简洁、散热功能良好的成型方法。
本发明首先提供一种半导体封装结构，包括散热片框架和引线框架，所述散热片框架连有散热片，所述引线框架的芯片座上贴有芯片，所述散热片和芯片通过结合材连接在一起，所述引线框架设有第一管脚，所述散热片框架上设有第二管脚和第三管脚。
其中，所述引线框架上4个第一管脚与芯片座底部电极相连接，为电流输入端；散热片框架上的3个第二管脚与芯片上表面电极相连接，为电流输出端；散热片框架上的第三管脚焊接导线，为电流控制端。
较佳地，为控制引线框架和散热片框架的精确位置叠合，所述引线框架上设有定位槽，所述散热片框架上设有定位脚。
较佳地，为了将芯片座和散热片与相对应的框架连接及提高连接强度，所述引线框架和散热片框架上分别设有第一连杆和第二连杆。
本发明同时提供一种半导体封装结构成型方法，其包括以下步骤：
准备引线框架：所述引线框架的芯片座四周设有半蚀刻区，第一管脚连接芯片座，将芯片座电极直接导通第一管脚，所述第一管脚上设有第一爬锡孔，所述引线框架上还设有定位槽和第一连杆；
焊接芯片:使用结合材在芯片座上面焊接芯片；
准备散热片框架：所述散热片框架上设有第二管脚和第三管脚，第二管脚和第三管脚上皆设有第二爬锡孔，所述散热片框架上还设有第二连杆和定位脚，所述散热片框架上连有散热片；
芯片焊接散热片：使用结合材将散热片与芯片焊接，同时散热片框架上的定位脚插入到引线框架上的定位槽内；
焊线：使用导线将第三管脚与芯片连接，实现导通；
载入治具烘烤：将焊线后的半导体放入治具，然后送入烤箱烘烤，烘烤后结合材固化，进而半导体整体高度确定；
注塑成型：在引线框架背面贴上一次胶膜，从而在注塑的时候半导体上表面和胶膜表面贴合在磨具的上下表面，进而成型后双表面均路出胶体；
电镀：将裸露在胶体外的第一管脚、第二管脚、第三管脚和引线框架上镀上锡层，此时，第一爬锡孔和第二爬锡孔也会镀上锡层；
切脚成型：使用模具将多余的引线框架和散热片框架、第一连杆、第二连杆切除，同时将第一管脚、第二管脚和第三管脚多余部分切除。
较佳地，所述散热片框架上设有用来平衡散热片站立在芯片上的支撑脚。
较佳地，为了防止在安装时无法区分各个管脚的脚位将半导体装反，，所述引线框架上设有脚位识别孔。
其中，为了注塑时能够牢牢锁住树脂，所述引线框架及散热片框架上设有背面半蚀刻区和正面半蚀刻区。
更佳地，为增加第一管脚、第二管脚和第三管脚切除多余部分后尽可能多的含有锡层，在切除第一管脚、第二管脚和第三管脚时切割位置为第一爬锡孔和第二爬锡孔处。
更佳地，为增加焊接效率，在芯片焊接散热片时，每次焊接时一枚引线框架焊接100颗散热片。
本发明至少具有以下优点：
1）  将第二管脚、第三管脚设置在散热片上面，减少了导线的使用减少了作业流程加速了散热，同时减少了第二连杆的使用，解决了后续注塑成型及第二连杆切割问题。
2）  第一管脚与芯片座底部电极相连接，为电流输入端；散热片框架上的3个第二管脚与芯片上表面电极相连接，为电流输出端；散热片框架上的第三管脚焊接导线，为电流控制端；大大减少了导线的应用，进而减少热量的损耗。
3）  注塑成型后，半导体双面均露出胶体，实现双面散热，提高半导体的散热功能。
4）  通过定位槽和定位脚，能够精确控制引线框架和散热片框架的位置叠合。
5）  第一爬锡孔和第二爬锡孔的设置，使得切脚成型后侧壁上的锡层能够保留下来，提高了半导体与电路板焊接的可靠性。
6）  通过散热片凸出高度、治具压紧后烘烤以及引线框架 贴胶膜等工艺有效的防止了溢胶的发生及芯片的破裂。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明半导体封装结构结构示意图；
图2是本发明引线框架结构示意图；
图3是本发明引线框架侧视图；
图4是本发明半散热片框架结构示意图；
图5是本发明散热片框架侧视图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1
参考图1至图5，一种半导体封装结构成型方法，其包括以下步骤：
准备引线框架1：所述引线框架1的芯片座21四周设有半蚀刻区23，第一管脚22连接芯片座21，将芯片座21电极直接导通第一管脚22，所述第一管脚22上设有第一爬锡孔24，所述引线框架1上还设有定位槽25、脚位识别孔26和第一连杆27；
焊接芯片3:使用结合材5在芯片座21上面焊接芯片3；
准备散热片框架2：所述散热片框架2上设有背面半蚀刻区41和正面半蚀刻区42，同时设有第二管脚43和第三管脚44，第二管脚43和第三管脚44上皆设有第二爬锡孔45，所述散热片框架2上还设有第二连杆46、支撑脚47和定位脚48，所述散热片框架2上连有散热片4；
芯片3焊接散热片4：使用结合材5将散热片4与芯片3焊接，同时散热片框架2上的定位脚48插入到引线框架1上的定位槽25内；
焊线：使用导线将第三管脚44与芯片3连接，实现导通；
载入治具烘烤：将焊线后的半导体放入治具，然后送入烤箱烘烤，烘烤后结合材固化，进而半导体整体高度确定；
注塑成型：在引线框架1背面贴上一次胶膜，从而在注塑的时候半导体上表面和胶膜表面贴合在磨具的上下表面，进而成型后双表面均路出胶体；
电镀：将裸露在胶体外的第一管脚22、第二管脚43、第三管脚44和引线框架1上镀上锡层，此时，第一爬锡孔24和第二爬锡孔45也会镀上锡层；
切脚成型：使用模具将多余的引线框架1和散热片框架2、第一连杆27、第二连杆46切除，同时将第一管脚22、第二管脚43和第三管脚44多余部分切除。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

1.一种半导体封装结构，包括散热片框架和引线框架，所述散热片框架连有散热片，所述引线框架的芯片座上贴有芯片，所述散热片和芯片通过结合材连接在一起，其特征是，所述引线框架设有第一管脚，所述散热片框架上设有第二管脚和第三管脚。
2.根据权利要求1所述一种半导体封装结构，其特征是，所述引线框架上4个第一管脚与芯片座底部电极相连接，为电流输入端；散热片框架上的3个第二管脚与芯片上表面电极相连接，为电流输出端；散热片框架上的第三管脚焊接导线，为电流控制端。
3.根据权利要求2所述一种半导体封装结构，其特征是，所述引线框架上设有定位槽，所述散热片框架上设有定位脚。
4.根据权利要求1所述一种半导体封装结构，其特征是，所述引线框架和散热片框架上分别设有第一连杆和第二连杆。
5.一种半导体封装结构成型方法，其特征是，其包括以下步骤：
准备引线框架：所述引线框架的芯片座四周设有半蚀刻区，第一管脚连接芯片座，将芯片座电极直接导通第一管脚，所述第一管脚上设有第一爬锡孔，所述引线框架上还设有定位槽和第一连杆；
焊接芯片:使用结合材在芯片座上面焊接芯片；
准备散热片框架：所述散热片框架上设有第二管脚和第三管脚，第二管脚和第三管脚上皆设有第二爬锡孔，所述散热片框架上还设有第二连杆和定位脚，所述散热片框架上连有散热片；
芯片焊接散热片：使用结合材将散热片与芯片焊接，同时散热片框架上的定位脚插入到引线框架上的定位槽内；
焊线：使用导线将第三管脚与芯片连接，实现导通；
载入治具烘烤：将焊线后的半导体放入治具，然后送入烤箱烘烤，烘烤后结合材固化，进而半导体整体高度确定；
注塑成型：在引线框架背面贴上一次胶膜，从而在注塑的时候半导体上表面和胶膜表面贴合在磨具的上下表面，进而成型后双表面均路出胶体；
电镀：将裸露在胶体外的第一管脚、第二管脚、第三管脚和引线框架上镀上锡层，此时，第一爬锡孔和第二爬锡孔也会镀上锡层；
切脚成型：使用模具将多余的引线框架和散热片框架、第一连杆、第二连杆切除，同时将第一管脚、第二管脚和第三管脚多余部分切除。
6.根据权利要求5所述一种半导体封装结构成型方法，其特征是，所述散热片框架上设有用来平衡散热片站立在芯片上的支撑脚。
7.根据权利要求5所述一种半导体封装结构成型方法，其特征是，所述引线框架上设有脚位识别孔。
8.根据权利要求5所述一种半导体封装结构成型方法，其特征是，所述散热片框架上设有背面半蚀刻区和正面半蚀刻区。
9.根据权利要求5所述一种半导体封装结构成型方法，其特征是，在切除第一管脚、第二管脚和第三管脚时切割位置为第一爬锡孔和第二爬锡孔处。
10.根据权利要求5所述一种半导体封装结构成型方法，其特征是，在芯片焊接散热片时，每次焊接时一枚引线框架焊接100颗散热片。
CN201310443963.4A 2013-09-26 2013-09-26 一种半导体封装结构及其成型方法 Pending CN103531551A (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201310443963.4A CN103531551A (zh) 2013-09-26 2013-09-26 一种半导体封装结构及其成型方法
JP2016537120A JP2016532297A (ja) 2013-09-26 2014-09-26 半導体パッケージ構造及びその成形方法
PCT/CN2014/087508 WO2015043499A1 (zh) 2013-09-26 2014-09-26 一种半导体封装结构及其成型方法
US15/022,055 US9673138B2 (en) 2013-09-26 2014-09-26 Semiconductor package structure having a heat sink frame connected to a lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201310443963.4A CN103531551A (zh) 2013-09-26 2013-09-26 一种半导体封装结构及其成型方法

Publications (1)

Publication Number Publication Date
CN103531551A true CN103531551A (zh) 2014-01-22

Family

ID=49933442

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310443963.4A Pending CN103531551A (zh) 2013-09-26 2013-09-26 一种半导体封装结构及其成型方法

Country Status (4)

Country Link
US (1) US9673138B2 (zh)
JP (1) JP2016532297A (zh)
CN (1) CN103531551A (zh)
WO (1) WO2015043499A1 (zh)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465597A (zh) * 2014-12-08 2015-03-25 杰群电子科技（东莞）有限公司 一种四面无引脚扁平半导体器件封装结构及封装方法
WO2015043499A1 (zh) * 2013-09-26 2015-04-02 杰群电子科技（东莞）有限公司 一种半导体封装结构及其成型方法
CN105810648A (zh) * 2016-05-06 2016-07-27 上海凯虹科技电子有限公司 封装体及封装方法
CN107660003A (zh) * 2017-10-23 2018-02-02 伟创力电子技术(苏州)有限公司 一种散热片加热装置
WO2018113290A1 (zh) * 2016-12-19 2018-06-28 杰群电子科技（东莞）有限公司 半导体元件以及制造方法
CN110416093A (zh) * 2018-04-26 2019-11-05 珠海格力电器股份有限公司 一种半导体器件及其封装方法、集成半导体器件
CN110661169A (zh) * 2018-06-28 2020-01-07 潍坊华光光电子有限公司 一种小尺寸低成本smd封装vcsel的制备方法
CN112992819A (zh) * 2021-04-26 2021-06-18 佛山市国星光电股份有限公司 一种封装器件及其制作方法
CN113394177A (zh) * 2021-08-18 2021-09-14 瑞能半导体科技股份有限公司 半导体封装结构及其制造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160276185A1 (en) * 2015-03-17 2016-09-22 Texas Instruments Incorporated Method and apparatus for making integrated circuit packages
CN112117251B (zh) * 2020-09-07 2022-11-25 矽磐微电子(重庆)有限公司 芯片封装结构及其制作方法
CN113066777A (zh) * 2021-03-03 2021-07-02 福建福顺半导体制造有限公司 一种高散热型半导体器件结构
TWI814424B (zh) * 2022-06-07 2023-09-01 強茂股份有限公司 薄型化半導體封裝件及其封裝方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181266A (ja) * 1994-12-21 1996-07-12 Hitachi Ltd リードフレームおよびそれを用いて構成された半導体装置
JP2004066813A (ja) * 1998-07-21 2004-03-04 Ricoh Co Ltd 液体噴射記録装置
JP2004079760A (ja) * 2002-08-19 2004-03-11 Nec Electronics Corp 半導体装置及びその組立方法
US20040080028A1 (en) * 2002-09-05 2004-04-29 Kabushiki Kaisha Toshiba Semiconductor device with semiconductor chip mounted in package
CN1851913A (zh) * 2005-04-22 2006-10-25 晶致半导体股份有限公司 导线架及应用该导线架的封装结构
JP2009295713A (ja) * 2008-06-04 2009-12-17 Denso Corp モールドパッケージの実装構造
CN203536411U (zh) * 2013-09-26 2014-04-09 杰群电子科技（东莞）有限公司 一种半导体封装结构

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5653556Y2 (zh) * 1976-08-09 1981-12-14
JP2844316B2 (ja) * 1994-10-28 1999-01-06 株式会社日立製作所 半導体装置およびその実装構造
US5822848A (en) * 1996-06-04 1998-10-20 Industrial Technology Research Institute Lead frame having a detachable and interchangeable die-attach paddle
US5798570A (en) * 1996-06-28 1998-08-25 Kabushiki Kaisha Gotoh Seisakusho Plastic molded semiconductor package with thermal dissipation means
TW423124B (en) 1998-11-27 2001-02-21 Walsin Advanced Electronics Lead frame with heat dissipation plate
TWI264096B (en) 2002-04-02 2006-10-11 Siliconware Precision Industries Co Ltd Semiconductor package with heat-dissipating structure
JP2004153234A (ja) * 2002-09-05 2004-05-27 Toshiba Corp 半導体装置
CN1567585A (zh) 2003-06-20 2005-01-19 晶致半导体股份有限公司 具有散热片的半导体封装体
JP4468115B2 (ja) * 2004-08-30 2010-05-26 株式会社ルネサステクノロジ 半導体装置
US7915728B2 (en) * 2007-07-12 2011-03-29 Vishay General Semiconductor Llc Subassembly that includes a power semiconductor die and a heat sink having an exposed surface portion thereof
JP2012033665A (ja) * 2010-07-30 2012-02-16 On Semiconductor Trading Ltd 半導体装置及びその製造方法
CN103531551A (zh) 2013-09-26 2014-01-22 杰群电子科技（东莞）有限公司 一种半导体封装结构及其成型方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181266A (ja) * 1994-12-21 1996-07-12 Hitachi Ltd リードフレームおよびそれを用いて構成された半導体装置
JP2004066813A (ja) * 1998-07-21 2004-03-04 Ricoh Co Ltd 液体噴射記録装置
JP2004079760A (ja) * 2002-08-19 2004-03-11 Nec Electronics Corp 半導体装置及びその組立方法
US20040080028A1 (en) * 2002-09-05 2004-04-29 Kabushiki Kaisha Toshiba Semiconductor device with semiconductor chip mounted in package
CN1851913A (zh) * 2005-04-22 2006-10-25 晶致半导体股份有限公司 导线架及应用该导线架的封装结构
JP2009295713A (ja) * 2008-06-04 2009-12-17 Denso Corp モールドパッケージの実装構造
CN203536411U (zh) * 2013-09-26 2014-04-09 杰群电子科技（东莞）有限公司 一种半导体封装结构

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015043499A1 (zh) * 2013-09-26 2015-04-02 杰群电子科技（东莞）有限公司 一种半导体封装结构及其成型方法
US9673138B2 (en) 2013-09-26 2017-06-06 Great Team Backend Foundry (Dongguan), Ltd. Semiconductor package structure having a heat sink frame connected to a lead frame
CN104465597B (zh) * 2014-12-08 2018-02-16 杰群电子科技（东莞）有限公司 一种四面无引脚扁平半导体器件封装结构及封装方法
CN104465597A (zh) * 2014-12-08 2015-03-25 杰群电子科技（东莞）有限公司 一种四面无引脚扁平半导体器件封装结构及封装方法
CN105810648A (zh) * 2016-05-06 2016-07-27 上海凯虹科技电子有限公司 封装体及封装方法
WO2018113290A1 (zh) * 2016-12-19 2018-06-28 杰群电子科技（东莞）有限公司 半导体元件以及制造方法
CN107660003A (zh) * 2017-10-23 2018-02-02 伟创力电子技术(苏州)有限公司 一种散热片加热装置
CN107660003B (zh) * 2017-10-23 2024-04-16 伟创力电子技术(苏州)有限公司 一种散热片加热装置
CN110416093A (zh) * 2018-04-26 2019-11-05 珠海格力电器股份有限公司 一种半导体器件及其封装方法、集成半导体器件
CN110661169A (zh) * 2018-06-28 2020-01-07 潍坊华光光电子有限公司 一种小尺寸低成本smd封装vcsel的制备方法
CN112992819A (zh) * 2021-04-26 2021-06-18 佛山市国星光电股份有限公司 一种封装器件及其制作方法
CN112992819B (zh) * 2021-04-26 2022-03-18 佛山市国星光电股份有限公司 一种封装器件及其制作方法
CN113394177A (zh) * 2021-08-18 2021-09-14 瑞能半导体科技股份有限公司 半导体封装结构及其制造方法

Also Published As

Publication number Publication date
US9673138B2 (en) 2017-06-06
WO2015043499A1 (zh) 2015-04-02
US20160225704A1 (en) 2016-08-04
JP2016532297A (ja) 2016-10-13

Similar Documents

Publication Publication Date Title
CN103531551A (zh) 一种半导体封装结构及其成型方法
CN203103285U (zh) 一种高密度蚀刻引线框架fcaaqfn封装件
CN204966534U (zh) 一种大功率led支架
CN203536411U (zh) 一种半导体封装结构
CN207558821U (zh) 一种具有溢流通道和溢流槽的led支架
CN205751528U (zh) 移动固态硬盘
CN203871320U (zh) Ac-dc电源电路的封装结构
CN210628280U (zh) 一种集成芯片封装结构
CN201629329U (zh) 一种引线框架
CN205122576U (zh) 用于无引脚封装结构的引线框架及封装结构
CN105070813A (zh) 一种大功率led支架及其封装方法
CN210607238U (zh) 一种集成芯片封装塑胶引线支架
CN106024647B (zh) 一种cob封装器件低成本生产工艺
CN204375733U (zh) 一种双引线框架
CN203553212U (zh) 一种可组合的晶片直接封装cob支架
CN203617344U (zh) 贴片式led引线框架
CN206401306U (zh) 大功率二端表面引出脚电子元器件立体封装结构
CN207250490U (zh) 高密度光电鼠标芯片封装结构
CN206789535U (zh) 一种电力电子器件的扇出型封装结构
CN206774524U (zh) 音频功放封装电路
CN201345361Y (zh) 引线框架
CN104369322A (zh) 一种贴片整流桥注塑模具
CN204834676U (zh) 基于镜面铝基板的led光源模块
CN207558829U (zh) 一种用于倒装或垂直led芯片的led支架
CN204179109U (zh) 一种新型的发光单元

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
AD01 Patent right deemed abandoned

Effective date of abandoning: 20191108

AD01 Patent right deemed abandoned