CN103531551A - Semiconductor packaging structure and forming method thereof - Google Patents

Semiconductor packaging structure and forming method thereof Download PDF

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Publication number
CN103531551A
CN103531551A CN201310443963.4A CN201310443963A CN103531551A CN 103531551 A CN103531551 A CN 103531551A CN 201310443963 A CN201310443963 A CN 201310443963A CN 103531551 A CN103531551 A CN 103531551A
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China
Prior art keywords
pin
lead frame
fin
chip
framework
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CN201310443963.4A
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Chinese (zh)
Inventor
曹周
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Great Team Backend Foundry Dongguan Co Ltd
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Great Team Backend Foundry Dongguan Co Ltd
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Priority to CN201310443963.4A priority Critical patent/CN103531551A/en
Publication of CN103531551A publication Critical patent/CN103531551A/en
Priority to PCT/CN2014/087508 priority patent/WO2015043499A1/en
Priority to US15/022,055 priority patent/US9673138B2/en
Priority to JP2016537120A priority patent/JP2016532297A/en
Pending legal-status Critical Current

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

The invention discloses a semiconductor packaging structure and a forming method thereof. The semiconductor packaging structure comprises a radiating fin frame and a lead frame, wherein the radiating fin frame is connected with a radiating fin, a chip is stuck on a chip holder of the lead frame, the radiating fin is connected with the chip through a combining material, the lead frame is provided with a first pin, and second pins and a third pin are arranged on the radiating fin frame. The forming method of the semiconductor packaging structure comprises the following steps: the second pins and the third pin are arranged on the radiating fin, the first pin is connected with a bottom electrode of the chip holder as a current input end; three second pins on the radiating fin frame are connected with an electrode on the upper surface of the chip as current output ends; the third pin on the radiating fin frame is welded with a lead as a current control end, so that application of the lead is greatly reduced, a work flow is reduced and the heat dissipation is accelerated; after injection molding, colloids are exposed on the two faces of a semiconductor, so that the double-faced heat dissipation is realized, and a radiating function of the semiconductor is improved.

Description

A kind of semiconductor package and forming method thereof
Technical field
The invention belongs to semiconductor packages field, be specifically related to a kind of semiconductor package and forming method thereof.
Background technology
In the last few years, the integrated level of semiconductor device was more and more higher, and its memory space, conversion speed and power develops rapidly, but volume is more and more less, and this trend has been accelerated the high speed development of semiconductor integrated circuit.Wherein, lead frame is the skeleton of semiconductor integrated circuit, lead frame is as the chip carrier of integrated circuit or discrete device, it is a kind of electrical connection that realizes chip internal circuit exit and outer lead by means of bonding gold wire, the key structure part that forms electric loop, it has played the function served as bridge being connected with outer lead.Lead frame is mainly comprised of two parts: chip carrier and pin.Wherein chip carrier provides mechanical support at encapsulation process meta chip, and pin is to connect chip to arrive the electric path outside encapsulation.The function of lead frame is apparent, and first it has played the supporting role of encasing electronic components, prevent simultaneously resin lead-in wire between gush out suddenly, for plastics provide support; Secondly it makes chip be connected to substrate, and electricity and the passage of heat of chip wiring board is provided.Integrated circuit in use, inevitably can produce heat, especially the larger circuit of power consumption, the heat producing just more strengthens, therefore when work, just require lead frame must there is good thermal conductivity, otherwise at work will be because heat is compared with large and can not exhale in time and burn out chip.The major function of lead frame is for integrated circuit (IC) chip provides mechanical support carrier, and connects integrated circuit external circuit as conducting medium, transmits the signal of telecommunication, and together with encapsulating material, the heat producing while outwards distributing chip operation.
Existing lead frame dispels the heat by fin, but shortcoming is because pin on chip is too much, causes dissipation of heat excessively slow, and the combination of existing lead frame and fin simultaneously also has a lot of other defects, such as: in conjunction with inaccuracy, inefficiency etc.
A kind of heat-dissipation packaging structure of lead frame is disclosed in Chinese utility model patent specification CN201629305U, comprise a lead frame and fin, it is characterized in that: described lead frame surrounding offers through hole and described through hole and is engaged in and on fin, offers projection, described lead frame and fin via through holes and projection punching press engagement connection.Described encapsulating structure is by this mode of projection punching press engagement connection, and heat sinking function is limited.
In Chinese utility model patent specification CN202394951U, circuit lead frame fin is disclosed, circuit lead frame fin of the present utility model, at middle part, lamellar body bottom surface, establish a groove, in groove, be provided with one and mate consistent mold insert, silver coating on the outer surface of mold insert with groove.Described circuit lead frame fin heat sinking function is limited.
Summary of the invention
The invention provides a kind of semiconductor package, a kind ofly construct clear succinct, semiconductor package that heat sinking function is good; The present invention provides a kind of forming method of semiconductor package simultaneously, a kind of clear succinct, forming method that heat sinking function is good of encapsulating structure structure of at least realizing.
First the present invention provides a kind of semiconductor package, comprise fin framework and lead frame, described fin framework is connected with fin, on the chip carrier of described lead frame, post chip, described fin and chip are by linking together in conjunction with material, described lead frame is provided with the first pin, and described fin framework is provided with the second pin and three-prong.
Wherein, on described lead frame, 4 the first pins are connected with chip carrier bottom electrode, are current input terminal; 3 the second pins on fin framework are connected with chip upper surface electrode, are current output terminal; Three-prong welding lead on fin framework is current controling end.
Preferably, superimposed for the exact position of control lead frame and fin framework, described lead frame is provided with location notch, and described fin framework is provided with angle.
Preferably, for chip carrier is connected and improves bonding strength with corresponding framework with fin, on described lead frame and fin framework, be respectively equipped with first connecting rod and second connecting rod.
The present invention provides a kind of semiconductor package forming method simultaneously, and it comprises the following steps:
Prepare lead frame: the chip carrier surrounding of described lead frame is provided with partially etching area, the first pin connection-core bar, by direct conducting the first pin of chip carrier electrode, described the first pin is provided with first and climbs tin hole, is also provided with location notch and first connecting rod on described lead frame;
Welding chip: use in conjunction with material welding chip on chip carrier;
Prepare fin framework: described fin framework is provided with the second pin and three-prong, is all provided with second and climbs tin hole on the second pin and three-prong, on described fin framework, is also provided with second connecting rod and angle, on described fin framework, is connected with fin;
Chips welding fin: use is in conjunction with material by fin and chips welding, and the angle on fin framework is inserted in the location notch on lead frame simultaneously;
Bonding wire: use wire that three-prong is connected with chip, realize conducting;
Be written into tool baking: the semiconductor after bonding wire is put into tool, then send into baking box baking, after baking, in conjunction with material, solidify, and then semiconductor whole height is determined;
Injection mo(u)lding: stick one time glued membrane at the lead frame back side, thereby upper semiconductor and glued membrane surface label are combined in the upper and lower surface of grinding tool in injection moulding, and then after moulding, two surfaces all go out colloid in roads;
Electroplate: will on exposed the first pin, the second pin, three-prong and lead frame outside colloid, plate tin layer, now, first climbs tin hole and second climbs tin hole and also can plate tin layer;
Cutting moulding: use mould that unnecessary lead frame and fin framework, first connecting rod, second connecting rod are excised, simultaneously by the first pin, the second pin and the excision of three-prong redundance.
Preferably, described fin framework is provided with for balance fin and stand on the feet on chip.
Preferably, in order to prevent from cannot distinguishing when mounted the pin position of each pin, semiconductor is anti-loaded,, described lead frame is provided with pin position identifying hole.
Wherein, during for injection moulding, can firmly pin resin, described lead frame and fin framework are provided with back side partially etching area and front partially etching area.
More preferably, for increasing the tin layer that contains as much as possible after the first pin, the second pin and three-prong excision redundance, when excision the first pin, the second pin and three-prong, cutting position is first to climb tin hole and second and climb Xi Kongchu.
More preferably, for increasing welding efficiency, when chips welding fin, 100 fin of one piece of lead frame welding while at every turn welding.
The present invention at least has the following advantages:
1) the second pin, three-prong are arranged on above fin, the use that has reduced wire has reduced work flow and has accelerated heat radiation, has reduced the use of second connecting rod simultaneously, has solved follow-up injection mo(u)lding and second connecting rod cutting problem.
2) the first pin is connected with chip carrier bottom electrode, is current input terminal; 3 the second pins on fin framework are connected with chip upper surface electrode, are current output terminal; Three-prong welding lead on fin framework is current controling end; Greatly reduce the application of wire, and then reduced the loss of heat.
3), after injection mo(u)lding, the two-sided colloid that all exposes of semiconductor, realizes two-side radiation, improves semi-conductive heat sinking function.
4), by location notch and angle, can accurately control the position folded of lead frame and fin framework.
5) first climb tin hole and the second setting of climbing tin hole, the tin layer on cutting moulding rear wall can be remained, improved the reliability of semiconductor and welding circuit board.
6) by fin protrusion height, tool, compress the techniques such as rear baking and lead frame rubberizing film and effectively prevented the generation of excessive glue and breaking of chip.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is semiconductor package structural representation of the present invention;
Fig. 2 is lead frame structure schematic diagram of the present invention;
Fig. 3 is lead frame end view of the present invention;
Fig. 4 is the present invention's half fin frame structure schematic diagram;
Fig. 5 is fin frame side view of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
Embodiment 1
Referring to figs. 1 to Fig. 5, a kind of semiconductor package forming method, it comprises the following steps:
Prepare lead frame 1: chip carrier 21 surroundings of described lead frame 1 are provided with partially etching area 23, the first pin two 2 connection-core bars 21, by direct conducting the first pin two 2 of chip carrier 21 electrode, described the first pin two 2 is provided with first and climbs tin hole 24, is also provided with location notch 25, pin position identifying hole 26 and first connecting rod 27 on described lead frame 1;
Welding chip 3: use in conjunction with material 5 welding chip 3 on chip carrier 21;
Prepare fin framework 2: described fin framework 2 is provided with back side partially etching area 41 and front partially etching area 42, be provided with the second pin 43 and three-prong 44 simultaneously, on the second pin 43 and three-prong 44, be all provided with second and climb tin hole 45, on described fin framework 2, be also provided with second connecting rod 46, feet 47 and angle 48, on described fin framework 2, be connected with fin 4;
Chip 3 welding fin 4: use in conjunction with material 5 fin 4 and chip 3 are welded, the angle 48 on fin framework 2 is inserted in the location notch 25 on lead frame 1 simultaneously;
Bonding wire: use wire that three-prong 44 is connected with chip 3, realize conducting;
Be written into tool baking: the semiconductor after bonding wire is put into tool, then send into baking box baking, after baking, in conjunction with material, solidify, and then semiconductor whole height is determined;
Injection mo(u)lding: stick glued membrane one time at lead frame 1 back side, thereby upper semiconductor and glued membrane surface label are combined in the upper and lower surface of grinding tool in injection moulding, and then after moulding, two surfaces all go out colloid in roads;
Electroplate: will on exposed the first pin two 2, the second pin 43, three-prong 44 and lead frame 1 outside colloid, plate tin layer, now, first climbs tin hole 24 and second climbs tin hole 45 and also can plate tin layer;
Cutting moulding: use mould that unnecessary lead frame 1 and fin framework 2, first connecting rod 27, second connecting rod 46 are excised, simultaneously by the first pin two 2, the second pin 43 and three-prong 44 redundances excisions.
Above content is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that specific embodiment of the invention is confined to these explanations.For general technical staff of the technical field of the invention, without departing from the inventive concept of the premise, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.

Claims (10)

1. a semiconductor package, comprise fin framework and lead frame, described fin framework is connected with fin, on the chip carrier of described lead frame, post chip, described fin and chip are by linking together in conjunction with material, it is characterized in that, described lead frame is provided with the first pin, and described fin framework is provided with the second pin and three-prong.
2. a kind of semiconductor package according to claim 1, is characterized in that, on described lead frame, 4 the first pins are connected with chip carrier bottom electrode, are current input terminal; 3 the second pins on fin framework are connected with chip upper surface electrode, are current output terminal; Three-prong welding lead on fin framework is current controling end.
3. a kind of semiconductor package according to claim 2, is characterized in that, described lead frame is provided with location notch, and described fin framework is provided with angle.
4. a kind of semiconductor package according to claim 1, is characterized in that, on described lead frame and fin framework, is respectively equipped with first connecting rod and second connecting rod.
5. a semiconductor package forming method, is characterized in that, it comprises the following steps:
Prepare lead frame: the chip carrier surrounding of described lead frame is provided with partially etching area, the first pin connection-core bar, by direct conducting the first pin of chip carrier electrode, described the first pin is provided with first and climbs tin hole, is also provided with location notch and first connecting rod on described lead frame;
Welding chip: use in conjunction with material welding chip on chip carrier;
Prepare fin framework: described fin framework is provided with the second pin and three-prong, is all provided with second and climbs tin hole on the second pin and three-prong, on described fin framework, is also provided with second connecting rod and angle, on described fin framework, is connected with fin;
Chips welding fin: use is in conjunction with material by fin and chips welding, and the angle on fin framework is inserted in the location notch on lead frame simultaneously;
Bonding wire: use wire that three-prong is connected with chip, realize conducting;
Be written into tool baking: the semiconductor after bonding wire is put into tool, then send into baking box baking, after baking, in conjunction with material, solidify, and then semiconductor whole height is determined;
Injection mo(u)lding: stick one time glued membrane at the lead frame back side, thereby upper semiconductor and glued membrane surface label are combined in the upper and lower surface of grinding tool in injection moulding, and then after moulding, two surfaces all go out colloid in roads;
Electroplate: will on exposed the first pin, the second pin, three-prong and lead frame outside colloid, plate tin layer, now, first climbs tin hole and second climbs tin hole and also can plate tin layer;
Cutting moulding: use mould that unnecessary lead frame and fin framework, first connecting rod, second connecting rod are excised, simultaneously by the first pin, the second pin and the excision of three-prong redundance.
6. a kind of semiconductor package forming method according to claim 5, is characterized in that, described fin framework is provided with for balance fin and stand on the feet on chip.
7. a kind of semiconductor package forming method according to claim 5, is characterized in that, described lead frame is provided with pin position identifying hole.
8. a kind of semiconductor package forming method according to claim 5, is characterized in that, described fin framework is provided with back side partially etching area and front partially etching area.
9. a kind of semiconductor package forming method according to claim 5, is characterized in that, when excision the first pin, the second pin and three-prong, cutting position is first to climb tin hole and second and climb Xi Kongchu.
10. a kind of semiconductor package forming method according to claim 5, is characterized in that, when chips welding fin, and 100 fin of one piece of lead frame welding while at every turn welding.
CN201310443963.4A 2013-09-26 2013-09-26 Semiconductor packaging structure and forming method thereof Pending CN103531551A (en)

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PCT/CN2014/087508 WO2015043499A1 (en) 2013-09-26 2014-09-26 Semiconductor encapsulation structure and forming method thereof
US15/022,055 US9673138B2 (en) 2013-09-26 2014-09-26 Semiconductor package structure having a heat sink frame connected to a lead frame
JP2016537120A JP2016532297A (en) 2013-09-26 2014-09-26 Semiconductor package structure and molding method thereof

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CN110661169A (en) * 2018-06-28 2020-01-07 潍坊华光光电子有限公司 Preparation method of small-size low-cost SMD (surface mounted device) packaged VCSEL (vertical surface emitting laser)
CN112992819A (en) * 2021-04-26 2021-06-18 佛山市国星光电股份有限公司 Packaging device and manufacturing method thereof
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