CN210805761U

CN210805761U - Semiconductor chip

Info

Publication number: CN210805761U
Application number: CN201921666984.1U
Authority: CN
Inventors: 谢云云; 闫世亮
Original assignee: Shanghai Bei Xin Semiconductor Technology Co ltd
Current assignee: Shanghai Bei Xin Semiconductor Technology Co ltd
Priority date: 2019-10-08
Filing date: 2019-10-08
Publication date: 2020-06-19
Anticipated expiration: 2029-10-08

Abstract

The utility model discloses a semiconductor chip, including moulding fat, base plate and semiconductor die, install the lead frame in the base plate, install the gold thread in the lead frame, the semiconductor die installation is fixed at the base plate, and the embedding is fixed with the wire in the semiconductor die, and the wire is connected with lead frame interior installation gold thread electricity, installs false connection pad in the semiconductor die, false connection pad and lead frame one-to-one, and outer electrical property node has been seted up to the rear end face of base plate, and the even spot welding has the guide pin in the outer electrical property node, and the surface of semiconductor die and base plate adopts to mould fat material encapsulation, and semiconductor die and base plate all adopt to electroplate the encapsulation with moulding fat material, and the semiconductor die is the logic die, and the semiconductor die is high bandwidth memory. The utility model discloses possess the import raw materials cost and the time cost's of saving the semiconductor package test advantage.

Description

Semiconductor chip

Technical Field

The utility model relates to a semiconductor chip technical field specifically is a semiconductor chip.

Background

The semiconductor chip means: the semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: a wafer from a wafer previous process is cut into small chips after a scribing process, then the cut chips are pasted on a small island of a corresponding substrate (Lead frame) frame by glue, and then a Bond Pad (Bond Pad) of the chip is connected to a corresponding pin (Lead) of the substrate by using an ultrafine metal (gold tin copper aluminum) wire or conductive resin to form a required circuit; and then packaging and protecting the independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, and carrying out finished product testing after packaging is finished.

However, the cost of imported raw materials for the existing semiconductor packaging test is high, so that the personnel maintenance and use cost is high, and the waste practicability in working time is poor.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a semiconductor chip possesses the import raw materials cost and the time cost's of saving the semiconductor package test advantage, and the import raw materials cost who has solved the test of current semiconductor package is higher, causes personnel to maintain to use and consumes great, causes the not good problem of the extravagant practicality in the operating time simultaneously.

In order to achieve the above object, the utility model provides a following technical scheme: the utility model provides a semiconductor chip, is including moulding fat, base plate and semiconductor die, install the lead frame in the base plate, install the gold thread in the lead frame, the installation of semiconductor die is fixed at the base plate.

Preferably, a lead is embedded and fixed in the semiconductor die, and the lead is electrically connected with a gold wire installed in the lead frame.

Preferably, dummy connection pads are mounted in the semiconductor die, and the dummy connection pads correspond to the lead frames one to one.

Preferably, the rear end face of the substrate is provided with an outer electrical node, and guide pins are uniformly spot-welded in the outer electrical node.

Preferably, the outer surfaces of the semiconductor tube core and the substrate are encapsulated by a plastic material, and the semiconductor tube core, the substrate and the plastic material are encapsulated by electroplating.

Preferably, the semiconductor die is a logic die and the semiconductor die is a high bandwidth memory.

Compared with the prior art, the beneficial effects of the utility model are as follows:

1. the utility model discloses a through setting up the plastic resin, when having reached the semiconductor chip and using, paste the semiconductor die that is cut well on corresponding base plate with glue, recycle superfine gold thread and wire and connect to the corresponding pin of base plate to constitute the required circuit; and then the independent semiconductor tube core is packaged and protected by the plastic grease shell, so that the cost of imported raw materials and time for semiconductor packaging test can be effectively further saved, the cost can be saved by replacing materials and replacing plastic grease with ceramic, and the semiconductor chip has better practical effect, lower cost and higher practicability when in use.

Drawings

Fig. 1 is a schematic top view of the present invention;

fig. 2 is a schematic view of the rear view appearance structure of the present invention;

fig. 3 is a schematic view of the rear view internal structure of the present invention;

fig. 4 is a schematic front view of the structure of the present invention.

In the figure: 1. plastic fat; 2. gold thread; 3. a substrate; 4. a lead frame; 5. a wire; 6. guiding a needle; 7. an outer electrical node; 8. a semiconductor die.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "front end", "rear end", "both ends", "one end", "the other end" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element to which the reference is made must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "disposed," "connected," and the like are to be construed broadly, and for example, "connected" may be either fixedly connected or detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Referring to fig. 1 to 4, the present invention provides an embodiment: a semiconductor chip comprises a plastic 1, a substrate 3 and a semiconductor tube core 8, wherein a lead frame 4 is arranged in the substrate 3, gold wires 2 are arranged in the lead frame 4, the semiconductor tube core 8 is fixedly arranged on the substrate 3, a lead 5 is embedded and fixed in the semiconductor tube core 8, the lead 5 is electrically connected with the gold wires 2 arranged in the lead frame 4, false connection pads are arranged in the semiconductor tube core 8, the false connection pads are in one-to-one correspondence with the lead frame 4, an external electrical node 7 is arranged on the rear end face of the substrate 3, guide pins 6 are uniformly spot-welded in the external electrical node 7, the outer surfaces of the semiconductor tube core 8 and the substrate 3 are packaged by adopting a plastic 1 material, the semiconductor tube core 8, the substrate 3 and the plastic 1 material are all packaged by electroplating, the semiconductor tube core 8 is a logic tube core, the semiconductor tube core 8 is a high-bandwidth memory, and when the semiconductor chip, the cut semiconductor tube core 8 is pasted on the corresponding substrate 3 by glue, and then the superfine gold wire 2 and the lead 5 are connected to the corresponding pin of the substrate 3 to form the required circuit; then, the independent semiconductor tube core 8 is packaged and protected by the plastic grease 1 shell, so that the cost of imported raw materials and time for semiconductor packaging test are effectively further saved, the cost is saved by replacing materials and replacing plastic grease with ceramic, the practical effect is better when the semiconductor chip is used, the cost is lower, and the practicability is better.

The working principle is as follows: the cut semiconductor tube core 8 is pasted on the corresponding substrate 3 by glue, and then the superfine gold wire 2 and the lead 5 are connected to the corresponding pin of the substrate 3 to form the required circuit; then, the independent semiconductor tube core 8 is packaged and protected by the plastic grease 1 shell, so that the cost of imported raw materials and time for semiconductor packaging test are effectively further saved, the cost is saved by replacing materials and replacing plastic grease with ceramic, the practical effect is better when the semiconductor chip is used, the cost is lower, and the practicability is better.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims

1. A semiconductor chip comprising a mastic (1), a substrate (3) and a semiconductor die (8), characterized in that: install lead frame (4) in base plate (3), install gold thread (2) in lead frame (4), semiconductor die (8) installation is fixed at base plate (3).

2. A semiconductor chip according to claim 1, wherein: a lead (5) is embedded and fixed in the semiconductor tube core (8), and the lead (5) is electrically connected with a gold wire (2) arranged in the lead frame (4).

3. A semiconductor chip according to claim 1, wherein: false connecting pads are arranged in the semiconductor tube core (8) and correspond to the lead frames (4) one by one.

4. A semiconductor chip according to claim 1, wherein: the rear end face of the substrate (3) is provided with an outer electrical node (7), and guide pins (6) are uniformly spot-welded in the outer electrical node (7).

5. A semiconductor chip according to claim 1, wherein: the outer surfaces of the semiconductor tube core (8) and the base plate (3) are packaged by adopting a plastic resin (1), and the semiconductor tube core (8), the base plate (3) and the plastic resin (1) are packaged by adopting electroplating.

6. A semiconductor chip according to claim 1, wherein: the semiconductor die (8) is a logic die and the semiconductor die (8) is a high bandwidth memory.