WO2018113290A1 - 半导体元件以及制造方法 - Google Patents

半导体元件以及制造方法 Download PDF

Info

Publication number
WO2018113290A1
WO2018113290A1 PCT/CN2017/093874 CN2017093874W WO2018113290A1 WO 2018113290 A1 WO2018113290 A1 WO 2018113290A1 CN 2017093874 W CN2017093874 W CN 2017093874W WO 2018113290 A1 WO2018113290 A1 WO 2018113290A1
Authority
WO
WIPO (PCT)
Prior art keywords
frame
barrier layer
copper bridge
lead frame
bridge frame
Prior art date
Application number
PCT/CN2017/093874
Other languages
English (en)
French (fr)
Inventor
曹周
Original Assignee
杰群电子科技（东莞）有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 杰群电子科技（东莞）有限公司 filed Critical 杰群电子科技（东莞）有限公司
Publication of WO2018113290A1 publication Critical patent/WO2018113290A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H01L21/566—Release layers for moulds, e.g. release layers, layers against residue during moulding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/38—Structure, shape, material or disposition of the strap connectors prior to the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present disclosure relates to the technical field of semiconductors, for example, to a method of fabricating a semiconductor device.
  • High-performance semiconductor components mean high power and high current, which means that the heat generated by semiconductor components is very large, and heat dissipation has yet to be solved.
  • the problem if the heat dissipation problem is not well solved, can only sacrifice part of the performance of the semiconductor component to reduce heat dissipation.
  • the semiconductor component is generally exposed by the lead frame under the chip, and the copper bridge frame above the chip is molded inside, so that the heat of the chip is only radiated by one side of the lead frame, so that the heat dissipation effect of the semiconductor component is poor.
  • the present disclosure provides a method for manufacturing a semiconductor device, which utilizes a liquid encapsulating material to cure the package, and achieves double-sided heat dissipation without generating a large pressure on the copper bridge frame and the chip, thereby avoiding damage to the chip, and the process and equipment are simple. Reduced production costs.
  • a method of manufacturing a double-sided heat dissipating semiconductor component comprising the steps of:
  • a laminated frame having a barrier layer including a lead frame, a chip, and a copper bridge frame stacked one above another, the lead frame being provided with the barrier layer, the barrier layer surrounding the copper bridge frame The outside of the setting is continuous;
  • the superposed frame filled with the liquid encapsulating material is cured.
  • the height of the barrier layer is 0-0.1 mm lower than the height of the copper bridge frame.
  • the liquid encapsulating material comprises liquid epoxy or green lacquer.
  • the liquid encapsulating material is filled by printing or filling.
  • the material of the barrier layer comprises plastic, and the barrier layer is injection molded or coated.
  • the method is disposed on the lead frame.
  • the barrier layer is disposed on the lead frame by 3D printing.
  • the barrier layer is formed from 3D printing of metal, high polymer material or ceramic.
  • the forming a superposed frame having a barrier layer comprises:
  • a laminated frame including a lead frame, a chip, and a copper bridge frame sequentially stacked, on which the barrier layer is continuously formed around an outer side of the copper bridge frame;
  • a barrier layer is continuously disposed on a region of the lead frame surrounding the copper bridge frame, and the lead frame having the barrier layer, the chip, and the copper bridge frame are formed into a laminated frame having a barrier layer.
  • the forming the overlapping frame comprises:
  • the wire is welded to form a laminated frame.
  • the present disclosure provides a method for manufacturing a semiconductor device, further comprising: providing a glue layer on a lower surface of the stacking frame, the glue layer being disposed to prevent the liquid package material from leaking to a lower surface of the lead frame.
  • the present disclosure also provides a semiconductor device fabricated by the manufacturing method of any of the above, comprising a laminated frame comprising a lead frame, a chip and a copper bridge frame stacked one above another;
  • a liquid encapsulating material is filled between the lead frame and the copper bridge frame, and an upper top surface of the liquid encapsulating material does not exceed an upper surface of the copper bridge frame.
  • the present disclosure provides a method of fabricating a semiconductor device and a semiconductor device, wherein the method of fabricating the semiconductor device includes the steps of: forming a stacked frame having a barrier layer, the stacked frame including a lead frame, a chip, and a layer which are sequentially stacked upward a copper bridge frame, the lead frame is provided with the barrier layer, the barrier layer is continuously disposed around an outer side of the copper bridge frame; and a liquid encapsulating material is filled between the barrier layer and the copper bridge frame The upper top surface of the liquid encapsulating material does not exceed the copper bridge frame; the superposed frame filled with the liquid encapsulating material is cured.
  • FIG. 1 is a schematic structural view of a lead frame of the related art.
  • Fig. 2 is a cross-sectional view taken along line A-A of Fig. 1;
  • FIG. 3 is a schematic structural view of a copper bridge frame of the related art.
  • Fig. 4 is a cross-sectional view taken along line B-B of Fig. 3;
  • Fig. 5 is a schematic structural view of a laminated frame of the related art.
  • Fig. 6 is a cross-sectional view taken along line C-C of Fig. 5;
  • Fig. 7 is a partial enlarged view of the portion D of Fig. 6.
  • Fig. 8 is a schematic view showing the cooperation of the mold of the related art in forming a double-sided heat-dissipating semiconductor element.
  • Fig. 9 is a schematic view showing a state in which a laminated frame of the related art forms a double-sided heat-dissipating semiconductor element by a buffer silicone film at the time of injection molding.
  • Fig. 10 is a schematic view showing a double-sided heat-dissipating semiconductor element formed by a buffer silicone film by a laminated frame of the related art.
  • Fig. 11 is a schematic view showing a state in which a laminated frame of the related art is formed by grinding to form a double-sided heat-dissipating semiconductor element.
  • Fig. 12 is a schematic view of a double-sided heat-dissipating semiconductor element formed by grinding of a laminated frame of the related art.
  • Figure 13 is a schematic view showing the structure of a laminated frame having a barrier layer of the present embodiment.
  • Fig. 14 is a cross-sectional view taken along line E-E of Fig. 13;
  • Figure 15 is a partial enlarged view of the portion F of Figure 14.
  • Fig. 16 is a structural schematic view showing the laminated frame having the barrier layer filled with the liquid encapsulating material of the present embodiment.
  • Fig. 17 is a cross-sectional view taken along line G-G of Fig. 16;
  • Fig. 18 is a partial enlarged view of the portion H of Fig. 17;
  • Figure 19 is a schematic view showing the structure of the laminated frame at H in Figure 18 after curing.
  • Fig. 20 is a schematic view showing the front surface of the double-sided heat-dissipating semiconductor element of the present embodiment separated into a single body.
  • Figure 21 is a side view of the double-sided heat-dissipating semiconductor device of the present embodiment.
  • Fig. 22 is a view showing the back surface of the double-sided heat-dissipating semiconductor element of the present embodiment separated into a single body.
  • Figure 23 is a cross-sectional view taken along line J-J of Figure 20 .
  • Fig. 24 is a flow chart showing the manufacture of the double-sided heat-dissipating semiconductor device of the present embodiment.
  • Figure 25 is a flow chart showing the manufacture of the laminated frame of the present embodiment.
  • the double-sided heat dissipating semiconductor component is exposed due to the copper bridge frame above the chip and the lead frame under the chip, so that the heat of the chip can be radiated through the copper bridge frame and the lead frame on both sides, the semiconductor component
  • the heat dissipation performance has been greatly improved, and it can meet the demand of high power and high current, and is increasingly favored by the market.
  • the semiconductor element is a laminated frame 1' before being encapsulated by a material such as epoxy resin.
  • the laminated frame 1' includes a lead frame 11' which is sequentially stacked (as shown in FIGS. 1 and 2). , the chip 12' and the copper bridge frame 13' (as shown in Figures 3 and 4), the laminated frame 1' is molded and packaged, the injection mold will firmly press the product when clamping, to prevent plastic Leakage between the mold and the product.
  • the copper bridge frame 13' is plastically wrapped inside, the mold can be directly pressed against the lead frame 11', the lead frame 11' can withstand the pressure of the mold, and the copper bridge frame 13' is located in the cavity.
  • the copper bridge frame 13' and the chip 12' under the copper bridge frame 13' only need to withstand the injection pressure during injection molding, the injection pressure is much smaller than the mold clamping pressure, and the copper bridge frame 13' and the chip 12' are not Crushed.
  • Both the lead frame 11' and the copper bridge frame 13' of the double-sided heat-dissipating semiconductor element need to be exposed and cannot be encapsulated by a plastic package, as shown in Fig. 8, so that the upper mold 6' is directly pressed against the outer surface of the copper bridge frame 13', The die 7' is directly pressed against the outer surface of the lead frame 11', and the force against the copper bridge frame 13' when the mold is clamped is directly pressed against the chip 12', which is sufficient to crush the chip 12'.
  • a special buffered silicone film 8' is disposed on the upper surface of the copper bridge frame 13' and the lower surface of the lead frame 11', and is strictly controlled. The position of the mold clamping mold is clamped, and the upper mold 6' and the lower mold 7' are pressed from the upper side and the lower side to the buffer silicone film 8' on both sides, respectively, and then the ordinary plastic sealing layer 5' is formed by using an injection mold to form a figure.
  • Fig. 11 Another method is shown in Fig. 11: when using injection molding, the thickness of the ordinary plastic sealing layer 5' on the copper bridge frame 13' is made as thin as possible, and then the ordinary above the copper bridge frame 13' is passed through the grinding wheel 9'.
  • the plastic seal layer 5' is removed by grinding to form a double-sided heat-dissipating semiconductor element as shown in FIG.
  • the thickness of the ordinary plastic sealing layer 5' on the surface of the copper bridge frame 13' is controlled to a small extent, and the grinding precision is particularly high, and the ordinary plastic sealing layer 5' on the copper bridge frame 13' is removed. Moreover, it is impossible to damage the copper bridge frame 13' itself, the processing is very difficult, and the cost of the equipment is high.
  • the present embodiment provides a method of fabricating a semiconductor device, as shown in FIG. 24, which may include the following steps.
  • step 10 a laminated frame 1 having a barrier layer 2 is formed.
  • the laminated frame 1 includes a lead frame 11, a chip 12, and a copper bridge frame 13 which are sequentially stacked upward, and the lead frame 11 is provided with a barrier layer 2 which surrounds the outer side of the copper bridge frame 13. Continuous setting.
  • step 20 a liquid encapsulating material 3 is filled between the barrier layer 2 and the copper bridge frame 13, and the upper top surface of the liquid encapsulating material 3 does not exceed the upper surface of the copper bridge frame 13, as shown in Figs.
  • step 30 the laminated frame 1 filled with the liquid encapsulating material 3 is cured as shown in FIG.
  • the manufacturing method of the semiconductor device provided in this embodiment utilizes the barrier layer 2 disposed continuously around the outer side of the copper bridge frame 13 to prevent leakage of the liquid encapsulating material 3 when it is filled, since the upper top surface of the liquid encapsulating material 3 does not exceed the upper surface of the copper bridge frame 13. On the surface, the liquid encapsulating material 3 is slightly trapped during curing. Therefore, after the liquid encapsulating material 3 is cured, the copper bridge frame 13 and the lead frame 11 can be exposed to form a semiconductor element having a double-sided heat dissipating function. The method is directly cured after being filled with the liquid encapsulating material 3, and does not generate a large pressure on the copper bridge frame 13 and the chip 12, thereby avoiding damage to the chip 12, and the process and equipment are simple, and the production cost is reduced.
  • a stack having the barrier layer 2 is formed.
  • the frame 1 is formed by forming a barrier layer 2 on the lead frame 11.
  • the laminated frame 1 having the barrier layer 2 may be formed by first forming the laminated frame 1, wherein the laminated frame 1 includes the lead frame 11, the chip 12, and the copper bridge frame 13 which are sequentially stacked, and then the lead frame 11
  • the barrier layer 2 is continuously formed on the outer side of the surrounding copper bridge frame 13, that is, the laminated frame 1 is formed first, and then the barrier layer is disposed on the lead frame 11 of the laminated frame 1; or the copper bridge may be first wrapped around the lead frame 11.
  • the barrier layer 2 is continuously disposed in the region of the frame 13, and the lead frame 11, the chip 12, and the copper bridge frame 13 having the barrier layer 2 are formed into the laminated frame 1 having the barrier layer 2, that is, the barrier layer is formed on the lead frame 11 first. 2.
  • the lead frame 2 is reused to form the laminated frame 1. Both of these methods can form the laminated frame 1 having the barrier layer 2 well.
  • the process of forming the lead frame 11, the chip 12, and the copper bridge frame 13 to form the laminated frame 1 is as shown in FIG. 25, and includes the following steps.
  • step 110 a chip 12 is placed on the lead frame 11.
  • step 120 a copper bridge frame 13 is placed on the chip 12.
  • step 130 the lead frame 11, the chip 12, and the copper bridge frame 13 are soldered using a reflow process.
  • step 140 the wire is welded to form the laminated frame 1.
  • the adhesive layer 4 may be disposed on the lower surface of the laminated frame 1 to prevent the liquid encapsulating material 3 from leaking down to the lower surface of the lead frame 11.
  • the adhesive layer 4 may be a film or the like as long as the liquid encapsulating material 3 can be prevented from leaking.
  • a step 150 may be added after the step 140, and a glue layer 4 such as a film or the like may be disposed on the lower surface of the laminated frame 1.
  • a semiconductor element manufactured according to the above method provided by the present embodiment, as shown in FIG. 23, includes a laminated frame (1) including a lead frame (11) and a chip (12) which are sequentially stacked upward. And a copper bridge frame (13); the lead frame (11) and the copper bridge frame (13) are filled with a liquid encapsulating material (3), and the upper top surface of the liquid encapsulating material (3) does not exceed The upper surface of the copper bridge frame (13).
  • the liquid encapsulating material 3 can be maintained by controlling the filling amount of the liquid encapsulating material 3.
  • the upper top surface is lower than the upper surface of the copper bridge frame 13; the height of the barrier layer 2 may also be set to be lower than the height of the copper bridge frame 13 by 0-0.1 mm, since the height of the barrier layer 2 is at most the same as the copper bridge frame 13, Therefore, in the case where the height of the barrier layer 2 is lower than the height of the copper bridge frame 13, when the filled liquid encapsulating material 3 is excessive, the liquid encapsulating material 3 overflows from one side of the barrier layer 2 to avoid overflowing to the copper bridge frame.
  • the height of the barrier layer 2 is not more than 0.1 mm below the copper bridge frame 13, because in the case where the height of the barrier layer 2 itself is also relatively low, the liquid encapsulating material 2 easily overflows, and it is not easy to fill the internal space of the semiconductor element.
  • the liquid encapsulating material 3 may be a liquid encapsulating material having fluidity such as liquid epoxy resin or green lacquer, or may be other materials, as long as it has fluidity under normal temperature and the like, and can be solidified to form a package structure at a high temperature, the liquid ring Oxygen resin and green paint are better packaging materials, the strength after curing is relatively high, and the thermal resistance is relatively low, and the cost is relatively low.
  • the filling method of the liquid encapsulating material 3 is many, for example, it can be filled by printing or filling, etc., as long as it can be well filled, relatively speaking, the printing work efficiency is relatively high.
  • the material of the barrier layer 2 is not limited as long as it can block the leakage of the liquid encapsulating material 3.
  • the barrier layer 2 can be a plastic, such as a conventional injection molded epoxy material, which is disposed on the lead frame 11 by injection molding or coating. The process is mature and the cost is relatively low.
  • the barrier layer 2 can also be disposed on the lead frame 11 by means of 3D printing. The 3D printing method has fewer restrictions on the material, and the barrier layer 2 can be formed by 3D printing of metal, high polymer material or ceramic.
  • the manufacturing method and the semiconductor element of the semiconductor device provided by the present disclosure use a barrier layer continuously disposed around the outer side of the copper bridge frame to avoid leakage of the liquid package material when the liquid package material is filled, and the copper bridge frame and the lead frame can be exposed after the liquid package material is cured.
  • the semiconductor component with double-sided heat dissipation function, the method is directly solidified by filling with a liquid encapsulating material, does not generate large pressure on the copper bridge frame and the chip, avoids damage to the chip, and has simple process and equipment, and reduces production cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种半导体元件的制造方法，包括：形成具有阻挡层（2）的叠合框架（1），叠合框架包括依次向上层叠的引线框架（11）、芯片（12）和铜桥框架（13），引线框架上设有阻挡层，阻挡层环绕铜桥框架的外侧连续设置；向阻挡层和铜桥框架之间填充液态封装材料（3），液态封装材料的上顶面不超过铜桥框架；将填充有液态封装材料的叠合框架固化。

Description

[根据细则37.2由ISA制定的发明名称]　半导体元件以及制造方法 技术领域
本公开涉及半导体的技术领域，例如涉及一种半导体元件的制造方法。
背景技术
随着半导体元件技术的发展，半导体元件一直在往高性能的方向发展，高性能的半导体元件意味着高功率和大电流，也意味着半导体元件工作时产生的热量很大，散热成了有待解决的问题，如果散热问题不能很好地解决，那么只能牺牲半导体元件的部分性能以减少散热。半导体元件一般是芯片下方的引线框架外露，芯片上方的铜桥框架被塑封在内部，因此芯片的热量只是通过引线框架单面散热，使得半导体元件的散热效果较差。
发明内容
本公开提出一种半导体元件的制造方法，利用液态封装材料固化封装，在实现双面散热的同时，不会对铜桥框架和芯片产生大的压力，避免损坏芯片，且工艺和设备均简单，降低了生产成本。
一种双面散热半导体元件的制造方法，包括以下步骤：
形成具有阻挡层的叠合框架，所述叠合框架包括依次向上层叠的引线框架、芯片和铜桥框架，所述引线框架上设有所述阻挡层，所述阻挡层环绕所述铜桥框架的外侧连续设置；
向所述阻挡层和所述铜桥框架之间填充液态封装材料，所述液态封装材料的上顶面不超过所述铜桥框架的上表面；
将填充有液态封装材料的叠合框架固化。
可选地，所述阻挡层的高度比所述铜桥框架的高度低0-0.1mm。
可选地，所述液态封装材料包括液态环氧树脂或绿漆。
可选地，所述液态封装材料通过印刷或者灌入的方式进行填充。
可选地，所述阻挡层的材料包括塑胶，所述阻挡层通过注塑成型或涂覆的 方式设置于所述引线框架上。
可选地，所述阻挡层通过3D打印设置于所述引线框架上。
可选地，所述阻挡层由金属、高聚合物材料或陶瓷经过3D打印形成。
可选地，所述形成具有阻挡层的叠合框架，包括：
形成叠合框架，所述叠合框架包括依次层叠的引线框架、芯片和铜桥框架，在所述引线框架上环绕所述铜桥框架的外侧连续形成所述阻挡层；或
在引线框架上环绕铜桥框架的区域连续设置阻挡层，再将具有阻挡层的引线框架、芯片和铜桥框架形成具有阻挡层的叠合框架。
可选地，所述形成叠合框架，包括：
在引线框架上设置芯片；
在芯片上设置铜桥框架；
采用回流焊工艺，对引线框架、芯片和铜桥框架进行焊接；
焊线，形成叠合框架。
可选地，本公开提供了一种半导体元件的制造方法还包括：在叠合框架的下表面设置有胶层，所述胶层设置为防止液态封装材料下漏到引线框架下表面。
本公开还提供了一种半导体元件，所述半导体元件由上述任一所述的制造方法制成，包括叠合框架，所述叠合框架包括依次向上层叠的引线框架、芯片和铜桥框架；
所述引线框架和所述铜桥框架之间填充有液态封装材料，所述液态封装材料的上顶面不超过所述铜桥框架的上表面。
本公开提供了一种半导体元件的制造方法和半导体元件，其中，半导体元件的制造方法包括以下步骤：形成具有阻挡层的叠合框架，所述叠合框架包括依次向上层叠的引线框架、芯片和铜桥框架，所述引线框架上设有所述阻挡层，所述阻挡层环绕所述铜桥框架的外侧连续设置；向所述阻挡层和所述铜桥框架之间填充液态封装材料，所述液态封装材料的上顶面不超过所述铜桥框架；将填充有液态封装材料的叠合框架固化。
附图说明
图1是相关技术的引线框架的结构示意图。
图2是图1的A-A向剖视图。
图3是相关技术的铜桥框架的结构示意图。
图4是图3的B-B向剖视图。
图5是相关技术的叠合框架的结构示意图。
图6是图5的C-C向剖视图。
图7是图6的D处的局部放大图。
图8是相关技术的叠合框架形成双面散热半导体元件时和模具的配合示意图。
图9是相关技术的叠合框架通过缓冲硅胶膜形成双面散热半导体元件在注塑时的示意图。
图10是相关技术的叠合框架通过缓冲硅胶膜形成的双面散热半导体元件的示意图。
图11是相关技术的叠合框架通过研磨形成双面散热半导体元件在研磨时的示意图。
图12是相关技术的叠合框架通过研磨形成的双面散热半导体元件的示意图。
图13是本实施例的具有阻挡层的叠合框架的结构示意图。
图14是图13的E-E向剖视图。
图15是图14的F处的局部放大图。
图16是本实施例的具有阻挡层的叠合框架填充液态封装材料后的结构示意图。
图17是图16的G-G向剖视图。
图18是图17的H处的局部放大图。
图19是图18的H处的叠合框架固化后的结构示意图。
图20是本实施例的双面散热半导体元件分离成单个后的正面的示意图。
图21是本实施例的双面散热半导体元件的侧视图。
图22是本实施例的双面散热半导体元件分离成单个后的背面的示意图。
图23是图20的J-J向剖视图。
图24是本实施例的双面散热半导体元件的制造流程图。
图25是本实施例的叠合框架的制造流程图。
其中：
1-叠合框架，11-引线框架，12-芯片，13-铜桥框架，2-阻挡层，3-液态封装材料，4-胶层。1′-叠合框架，11′-引线框架，12′-芯片，13′-铜桥框架，5′-普通塑封层，6′-上模，7′-下模，8′-缓冲硅胶膜，9′-研磨轮。
具体实施方式
下面结合附图并通过具体实施方式来说明本公开的技术方案。
与单面散热的半导体元件相比，双面散热半导体元件由于芯片上方的铜桥框架和芯片下方的引线框架皆外露，因此，芯片的热量可以通过铜桥框架和引线框架双面散发，半导体元件的散热性能有大幅度提升，能满足高功率大电流的需求，越来越受到市场青睐。
半导体元件在被环氧树脂等材料封装前主体为叠合框架1′，如图5-图7所示，叠合框架1′包括依次层叠的引线框架11′(如图1和图2所示)、芯片12′和铜桥框架13′(如图3和图4所示)，叠合框架1′在注塑封装时，注塑的模具在合模时会将产品牢固地压紧，以防止塑胶从模具和产品之间漏出。单面散热的半导体元件中，铜桥框架13′被塑胶包裹在内部，模具可以直接压在引线框架11′上，引线框架11′可以承受模具的压力，而铜桥框架13′位于型腔中，在注塑时铜桥框架13′以及铜桥框架13′下方的芯片12′只需要承受注塑压力即可，注塑压力远小于模具合模的压力，铜桥框架13′和芯片12′不会被压坏。
双面散热的半导体元件的引线框架11′和铜桥框架13′均需要外露，不能被塑封包裹，如图8所示，因此上模6′直接压在铜桥框架13′的外表面，下模7′直接压在引线框架11′的外表面，模具合模时对铜桥框架13′的力会直接压向芯片12′，足以将芯片12′压坏。为了避免芯片12′被压坏，双面散热半导体元件制造方法一般有两种。一种方法如图9所示：在铜桥框架13′的上表面和引线框架11′的下表面均设置一层特殊的缓冲硅胶膜8′，通过严格控 制注塑模具合模的位置，上模6′和下模7′分别从上侧和下侧压在两侧的缓冲硅胶膜8′上，再利用注塑模具形成普通塑封层5′，形成如图10所示的双面散热半导体元件。由于既要保证密封性能，避免注塑时塑胶进入缓冲硅胶膜8′和铜桥框架13′之间以及缓冲硅胶膜8′和引线框架11′之间，模具合模的位置需要控制非常精准，且此种缓冲硅胶膜8′的性能也要非常优异，价格昂贵，使得双面散热的半导体元件的制造成本很高。另一种方法如图11所示：采用注塑封装时，将铜桥框架13′的上面的普通塑封层5′的厚度尽量做薄，再通过研磨轮9′将铜桥框架13′上面的普通塑封层5′研磨去除，以形成如图12所示的双面散热半导体元件。此种方法在铜桥框架13′表面的普通塑封层5′的厚度要控制在很小的范围，且研磨精度要求特别高，既要将铜桥框架13′上的普通塑封层5′去除干净，又不能对铜桥框架13′本身造成损伤，加工难度非常大，设备的成本很高。
本实施例提供了一种半导体元件的制造方法，如图24所示，可以包括以下步骤。
在步骤10中，形成具有阻挡层2的叠合框架1。
如图13-图15所示，叠合框架1包括依次向上层叠的引线框架11、芯片12和铜桥框架13，引线框架11上设有阻挡层2，阻挡层2环绕铜桥框架13的外侧连续设置。
在步骤20中，向阻挡层2和铜桥框架13之间填充液态封装材料3，液态封装材料3的上顶面不超过铜桥框架13的上表面，如图16-图18所示。
在步骤30中，将填充有液态封装材料3的叠合框架1固化，如图19所示。
本实施例提供的半导体元件的制造方法利用环绕铜桥框架13外侧连续设置的阻挡层2避免液态封装材料3填充时外漏，由于液态封装材料3的上顶面不超过铜桥框架13的上表面，固化时液态封装材料3还会有些许内陷，因此，液态封装材料3固化后，铜桥框架13和引线框架11均可以外露，形成具有双面散热功能的半导体元件。本方法使用液态封装材料3填充后直接固化，不会对铜桥框架13和芯片12产生大的压力，避免损坏芯片12，且工艺和设备均简单，降低了生产成本。
本实施例提供的半导体元件制造方法的步骤10中，形成具有阻挡层2的叠 合框架1，是通过在引线框架上11上形成阻挡层2。可选地，形成具有阻挡层2的叠合框架1可以是先形成叠合框架1，其中，叠合框架1包括依次层叠的引线框架11、芯片12和铜桥框架13，再在引线框架11上环绕铜桥框架13的外侧连续形成阻挡层2，即，先形成叠合框架1，再在叠合框架1的引线框架11上设置阻挡层；也可以是先在引线框架11上环绕铜桥框架13的区域连续设置阻挡层2，再将具有阻挡层2的引线框架11、芯片12和铜桥框架13形成具有阻挡层2的叠合框架1，即，先在引线框架11上形成阻挡层2，再利用此引线框架2形成叠合框架1。此两种方法均可以很好地形成具有阻挡层2的叠合框架1。其中，将引线框架11、芯片12和铜桥框架13形成叠合框架1的过程如图25所示，包括以下步骤。
在步骤110中，在引线框架11上设置芯片12。
在步骤120中，在芯片12上设置铜桥框架13。
在步骤130中，采用回流焊工艺，对引线框架11、芯片12和铜桥框架13进行焊接。
在步骤140中，焊线，形成叠合框架1。
本实施例可以在叠合框架1的下表面设置胶层4，以防止液态封装材料3下漏到引线框架11下表面。胶层4可以是薄膜等，只要能防止液体封装材料3下漏即可。
为了形成胶层4，可以在步骤140后增加步骤150，在叠合框架1的下表面设置胶层4，比如贴膜等。
固化后的半成品还需要进行电镀和分离，因此，在步骤30后还可以包括步骤40，在步骤40中，将固化后的叠合框架1电镀，再分离成单颗半导体元件，如图20-图23所示。按照本实施例提供的上述方法制造而成的半导体元件如图23所示，包括叠合框架(1)，所述叠合框架(1)包括依次向上层叠的引线框架(11)、芯片(12)和铜桥框架(13)；所述引线框架(11)和所述铜桥框架(13)之间填充有液态封装材料(3)，所述液态封装材料(3)的上顶面不超过所述铜桥框架(13)的上表面。
为了防止液态封装材料3的上顶面超出铜桥框架13的上表面，而溢出到铜桥框架13上，可以通过控制液态封装材料3的填充量，保持液态封装材料3的 上顶面低于铜桥框架13的上表面；也可以将阻挡层2的高度设置成比铜桥框架13的高度低0-0.1mm，由于阻挡层2的高度最多与铜桥框架13持平，因此，在阻挡层2的高度比铜桥框架13的高度低的情况下，当填充的液体封装材料3过多时，液体封装材料3会从阻挡层2的一侧溢出，避免溢出到铜桥框架3的表面。阻挡层2的高度低于铜桥框架13不宜超过0.1mm，因为，在阻挡层2本身的高度也比较低的情况下，液体封装材料2很容易溢出，不容易使得半导体元件内部空间填实。
液态封装材料3可以为液态环氧树脂或绿漆等具有流动性的液态封装材料，也可以是其他材料，只要在常温等环境下具有流动性，高温下可以固化形成封装结构即可，液态环氧树脂和绿漆均是比较好的封装材料，固化后强度比较高，且热阻比较低，成本也比较低。
液态封装材料3的填充方法很多，比如可以通过印刷或者灌入的方式等进行填充，只要能很好的填充进去即可，相对而言，印刷的工作效率比较高。
阻挡层2的材料没有限制，只要能阻挡液态封装材料3外漏即可，阻挡层2可以为塑胶，比如常规注塑的环氧树脂材料，通过注塑成型或涂覆的方式设置于引线框架11上，工艺成熟，成本比较低。阻挡层2也可以通过3D打印的方式设置于引线框架11上，3D打印的方式对材料的限制更少，阻挡层2可以由金属、高聚合物材料或陶瓷等经过3D打印形成。
工业实用性
本公开提供的半导体元件的制造方法和半导体元件，利用环绕铜桥框架外侧连续设置的阻挡层避免液态封装材料填充时外漏，液态封装材料固化后，铜桥框架和引线框架均可以外露，形成具有双面散热功能的半导体元件，本方法使用液态封装材料填充后直接固化，不会对铜桥框架和芯片产生大的压力，避免损坏芯片，且工艺和设备均简单，降低了生产成本。

Claims (11)

  1. 一种半导体元件的制造方法，包括：
    形成具有阻挡层(2)的叠合框架(1)，所述叠合框架(1)包括依次向上层叠的引线框架(11)、芯片(12)和铜桥框架(13)，所述引线框架(11)上设有所述阻挡层(2)，所述阻挡层(2)环绕所述铜桥框架(13)的外侧连续设置；
    向所述阻挡层(2)和所述铜桥框架(13)之间填充液态封装材料(3)，填充后，所述液态封装材料(3)的上顶面不超过所述铜桥框架(13)的上表面；
    将填充有液态封装材料(3)的叠合框架(1)固化。
  2. 如权利要求1所述的制造方法，其中，所述阻挡层(2)的高度比所述铜桥框架(13)的高度低0-0.1mm。
  3. 如权利要求1或2所述的制造方法，其中，所述液态封装材料(3)包括液态环氧树脂或绿漆。
  4. 如权利要求1或2所述的制造方法，其中，所述液态封装材料(3)通过印刷或者灌入的方式进行填充。
  5. 如权利要求1或2所述的制造方法，其中，所述阻挡层(2)的材料包括塑胶，所述阻挡层(2)通过注塑成型或涂覆的方式设置于所述引线框架(11)上。
  6. 如权利要求1或2所述的制造方法，其中，所述阻挡层(2)通过3D打印设置于所述引线框架(11)上。
  7. 如权利要求6所述的制造方法，其中，所述阻挡层(2)由金属、高聚合物材料或陶瓷经过3D打印形成。
  8. 如权利要求1或2所述的制造方法，其中，所述形成具有阻挡层(2)的叠合框架(1)，包括：
    形成叠合框架(1)，所述叠合框架(1)包括依次层叠的引线框架(11)、芯片(12)和铜桥框架(13)，在所述引线框架(11)上环绕所述铜桥框架(13)的外侧连续形成所述阻挡层(2)；或
    在引线框架(11)上环绕铜桥框架(13)的区域连续设置阻挡层(2)，再将具有阻挡层(2)的引线框架(11)、芯片(12)和铜桥框架(13)形成具有阻挡层(2)的叠合框架(1)。
  9. 如权利要求8所述的制造方法，其中，所述形成叠合框架(1)，包括：
    在引线框架(11)上设置芯片(12)；
    在芯片(12)上设置铜桥框架(13)；
    采用回流焊工艺，对引线框架(11)、芯片(12)和铜桥框架(13)进行焊接；
    焊线，形成叠合框架(1)。
  10. 如权利要求1或2所述的制造方法，还包括：在叠合框架(1)的下表面设置有胶层(4)，所述胶层(4)设置为防止液态封装材料(3)下漏到引线框架(11)下表面。
  11. 一种半导体元件，所述半导体元件由权利要求1-10任一所述的制造方法制成，包括叠合框架(1)，所述叠合框架(1)包括依次向上层叠的引线框架(11)、芯片(12)和铜桥框架(13)；
    所述引线框架(11)和所述铜桥框架(13)之间填充有液态封装材料(3)，所述液态封装材料(3)的上顶面不超过所述铜桥框架(13)的上表面。
PCT/CN2017/093874 2016-12-19 2017-07-21 半导体元件以及制造方法 WO2018113290A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201611179082.6 2016-12-19
CN201611179082.6A CN106876342A (zh) 2016-12-19 2016-12-19 一种双面散热半导体元件的制造方法

Publications (1)

Publication Number Publication Date
WO2018113290A1 true WO2018113290A1 (zh) 2018-06-28

Family

ID=59164719

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/093874 WO2018113290A1 (zh) 2016-12-19 2017-07-21 半导体元件以及制造方法

Country Status (2)

Country Link
CN (1) CN106876342A (zh)
WO (1) WO2018113290A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876342A (zh) * 2016-12-19 2017-06-20 杰群电子科技（东莞）有限公司 一种双面散热半导体元件的制造方法
CN110416093A (zh) * 2018-04-26 2019-11-05 珠海格力电器股份有限公司 一种半导体器件及其封装方法、集成半导体器件
CN112992836B (zh) * 2019-12-12 2023-01-17 珠海格力电器股份有限公司 一种铜桥双面散热的芯片及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101567333A (zh) * 2008-04-25 2009-10-28 印像科技股份有限公司 图像感测装置及其封装方法
CN103531551A (zh) * 2013-09-26 2014-01-22 杰群电子科技（东莞）有限公司 一种半导体封装结构及其成型方法
CN104821300A (zh) * 2014-01-31 2015-08-05 株式会社东芝 半导体装置及其制造方法
CN106876342A (zh) * 2016-12-19 2017-06-20 杰群电子科技（东莞）有限公司 一种双面散热半导体元件的制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130473A (en) * 1998-04-02 2000-10-10 National Semiconductor Corporation Lead frame chip scale package
JP4152855B2 (ja) * 2003-10-01 2008-09-17 リンテック株式会社 樹脂封止型の電子デバイスの製造方法。
US20120306031A1 (en) * 2011-05-31 2012-12-06 Freescale Semiconductor, Inc. Semiconductor sensor device and method of packaging same
JP6386746B2 (ja) * 2014-02-26 2018-09-05 株式会社ジェイデバイス 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101567333A (zh) * 2008-04-25 2009-10-28 印像科技股份有限公司 图像感测装置及其封装方法
CN103531551A (zh) * 2013-09-26 2014-01-22 杰群电子科技（东莞）有限公司 一种半导体封装结构及其成型方法
CN104821300A (zh) * 2014-01-31 2015-08-05 株式会社东芝 半导体装置及其制造方法
CN106876342A (zh) * 2016-12-19 2017-06-20 杰群电子科技（东莞）有限公司 一种双面散热半导体元件的制造方法

Also Published As

Publication number Publication date
CN106876342A (zh) 2017-06-20

Similar Documents

Publication Publication Date Title
US8558367B2 (en) Semiconductor module
JP4326786B2 (ja) 樹脂封止装置
JP5073756B2 (ja) 回路ダイの熱的性能の高いパッケージング
WO2018113356A1 (zh) 芯片封装结构及其制造方法
KR101316289B1 (ko) 회로 장치 및 그 제조 방법
JPH11505962A (ja) 電子パッケージをトランスファーモールドする方法と同法によるパッケージ
CN104465577A (zh) 半导体装置以及其制造方法
WO2018113290A1 (zh) 半导体元件以及制造方法
WO2011150879A2 (zh) 半导体器件封装方法及其结构
JP2011029589A (ja) 半導体装置およびその製造方法
JP6438794B2 (ja) モールド金型、樹脂モールド装置及び樹脂モールド方法
TWI698940B (zh) 基於模製技術的半導體封裝方法、影像處理元件、攝像裝置及電子設備
TWI244707B (en) Method for fabricating semiconductor package
US9076802B1 (en) Dual-sided film-assist molding process
CN104112733B (zh) 用于封装半导体芯片的模制材料和方法
TW201419466A (zh) 半導體封裝件之製法
CN104051373B (zh) 散热结构及半导体封装件的制法
TWM482842U (zh) 四方形扁平無引腳封裝（ｑｆｎ）之內封外露散熱裝置結構改良
KR101316273B1 (ko) 회로 장치
CN115472640B (zh) 一种图像传感器的封装结构和方法
JP5758823B2 (ja) 電子部品の樹脂封止成形品の製造方法、圧縮成形用下金型及び樹脂封止装置
JP2004055609A (ja) 樹脂封止方法
JP2010021347A (ja) 多層チップ型半導体装置及びその製造方法
CN104051386B (zh) 具有模塑料形成的台阶的封装件
JP2015088519A (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17884753

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 21/10/2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17884753

Country of ref document: EP

Kind code of ref document: A1