CN104821300A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN104821300A
CN104821300A CN201410286488.9A CN201410286488A CN104821300A CN 104821300 A CN104821300 A CN 104821300A CN 201410286488 A CN201410286488 A CN 201410286488A CN 104821300 A CN104821300 A CN 104821300A
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China
Prior art keywords
framework
slab portion
thin plate
plate part
semiconductor chip
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CN201410286488.9A
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English (en)
Inventor
田村幸治
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Toshiba Corp
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Toshiba Corp
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Publication of CN104821300A publication Critical patent/CN104821300A/zh
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Abstract

本发明提供厚度精度高的半导体装置及其制造方法。实施方式中,第1框架具有第1薄板部和第1厚板部。第2框架具有第2薄板部和第2厚板部。半导体芯片具有接合于第1框架的第1薄板部的第1内表面的第1电极、以及接合于第2框架的第2厚板部的第2内表面的第2电极。树脂将半导体芯片进行密封,并且使第1框架的第1外表面以及第2框架的第2外表面露出。

Description

半导体装置及其制造方法
相关申请的交叉引用
本申请享受以日本专利申请2014-17326号(申请日:2014年1月31日)为基础申请的优先权。本申请通过参照该基础申请而包括基础申请的全部内容。
技术领域
本发明的实施方式涉及半导体装置及其制造方法。
背景技术
近年来,在功率半导体装置中,为了低电阻化,提出了作为芯片与外部引线的连接构造、不使用引线接合而使用铜等的板状的连接器或者搭板(strap)的构造,这样的产品也在变多。
此外,提出了使搭载在芯片上的连接器从树脂露出、从安装基板侧的封装下表面和封装上表面这两面进行散热的构造。在使连接器上表面从树脂露出时,有在树脂模制工序中暂时用树脂覆盖连接器上表面之后,对树脂进行研磨的方法,但从成本等的观点出发,优选不进行研磨工序。
发明内容
本发明的实施方式提供一种厚度精度高的半导体装置及其制造方法。
根据实施方式,半导体装置具备第1框架、第2框架、半导体芯片以及树脂。所述第1框架具有:第1薄板部,具有第1外表面和所述第1外表面的相反侧的第1内表面;以及比所述第1薄板部厚的第1厚板部。所述第2框架具有:第2薄板部;以及第2厚板部,具有第2外表面和所述第2外表面的相反侧的第2内表面,并且所述第2厚板部比所述第2薄板部厚。所述半导体芯片设置在所述第1框架的所述第1薄板部与所述第2框架的所述第2厚板部之间。所述半导体芯片具备:半导体层,具有第1面和所述第1面的相反侧的第2面;第1电极,设置于所述第1面,与所述第1框架的所述第1薄板部的所述第1内表面接合;以及第2电极,设置于所述第2面,与所述第2框架的所述第2厚板部的所述第2内表面接合。所述树脂将所述半导体芯片进行密封,并且使所述第1框架的所述第1外表面以及所述第2框架的所述第2外表面露出。
附图说明
图1(a)是实施方式的半导体装置的示意俯视图,图1(b)是实施方式的半导体装置的示意剖视图。
图2是实施方式的半导体芯片的示意俯视图。
图3(a)是实施方式的半导体装置的示意剖视图,图3(b)是表示实施方式的半导体装置的制造方法的示意剖视图。
图4是实施方式的半导体装置的示意剖视图。
具体实施方式
以下,参照附图对实施方式进行说明。另外,各附图中对相同的要素赋予了相同的附图标记。
图1(a)是实施方式的半导体装置1的示意俯视图。
图1(b)是实施方式的半导体装置1的示意剖视图。
另外,图1(a)中,树脂80仅图示了外形线。
实施方式的半导体装置1具有半导体芯片10、与半导体芯片10电连接的框架20、30、以及将半导体芯片10进行密封的树脂80。
半导体芯片10是将设置在半导体层的一面侧的第1电极与设置在另一面侧的第2电极之间连结的、在纵向上形成电流路径的纵型设备。半导体芯片10例如是纵型MOSFET(Metal-Oxide-Semiconductor Field EffectTransistor,金属氧化物半导体场效应晶体管)。或者,半导体芯片10是纵型IGBT(Insulated Gate Bipolar Transistor)、纵型二极管。
作为半导体使用硅。或者也可以使用硅以外的半导体(例如SiC、GaN等化合物半导体)。
图2(a)是半导体芯片10的第1面12的示意俯视图,图2(b)是第1面12的相反侧的第2面14的示意俯视图。
如图2(a)所示,在半导体层11的第1面12形成有第1电极13。例如在MOSFET中,第1电极13是漏极电极。第1电极13占用第1面12的大部分而形成。
如图2(b)所示,在半导体层11的第2面14上,第2电极15和第3电极16相互绝缘分离地形成。第2电极15占用第2面14的大部分而形成,例如在MOSFET中是源极电极。第3电极16的面积小于第2电极15的面积,例如在MOSFET中是栅极电极。
半导体芯片10如图1(b)所示设置在第1框架20与第2框架30之间。
第1框架20具有第1薄板部21和第1厚板部22。第1薄板部21和第1厚板部22的厚度相对不同,第1厚板部22比第1薄板部21厚。
第1框架20通过金属板的模具加工而成形,第1薄板部21和第1厚板部22以L字状一体地设置。第1框架20例如由电传导及热传导优良的铜构成。另外,作为第1框架20,也可以使用以铜为主成分的铜合金,或者其他金属。
第1薄板部21具有第1外表面21a和其相反侧的第1内表面21b。第1厚板部22在第1薄板部21的一端部向第1内表面21b侧突出。
在第1厚板部22的突出方向的相反侧的面22b与第1薄板部21的第1外表面21a之间不形成台阶,第1厚板部22的面22b与第1薄板部21的第1外表面21a平直地相连。
半导体芯片10搭载在第1框架20的第1薄板部21的第1内表面21b上。半导体芯片10的形成有第1电极13的第1面12朝向第1薄板部21的第1内表面21b侧。
半导体芯片10的第1电极13经由导电性接合件(例如焊料)61而接合于第1薄板部21的第1内表面21b。因此,半导体芯片10的第1电极13与第1框架20电连接。
第2框架30具有第2厚板部31和第2薄板部32。第2厚板部31和第2薄板部32的厚度相对不同,第2厚板部31比第2薄板部32厚。
第2框架30通过金属板的模具加工而成形,第2厚板部31和第2薄板部32一体地设置。第2框架30例如由电传导以及热传导优良的铜构成。另外,作为第2框架30,也可以使用以铜为主成分的铜合金或者其他金属。
第2厚板部31具有第2外表面31a和其相反侧的第2内表面31b。在第2厚板部31的一端侧,相对于第2厚板部31隔开间隔地配置有第1框架20的第1厚板部22。第2薄板部32从第2厚板部31的另一端部朝向第1框架20的设有第1厚板部22的位置的相反侧突出。
在第2厚板部31的第2内表面31b与第2薄板部32之间形成有台阶。在第2厚板部31的第1外表面31a与第2薄板部32中的半导体芯片10的相反侧的面32a之间没有形成台阶,第2厚板部31的第1外表面31a与第2薄板部32的面32a平直地相连。
第2框架30的第2厚板部31搭载在半导体芯片10的第2面14上。第2框架30的第2厚板部31的第2内表面31b朝向半导体芯片10的第2面14侧。
半导体芯片10的形成在第2面14上的第2电极15经由导电性接合件(例如,焊料)62接合于第2框架30的第2厚板部31的第2内表面31b。因此,半导体芯片10的第2电极15与第2框架30电连接。
此外,如图1(a)所示,在半导体芯片10的第2面14侧,相对于第2框架30隔开间隔地设有栅极连接器40。
栅极连接器40的一端部40a例如经由焊料等的导电性接合件而与形成在半导体芯片10的第2面14上的第3电极(栅极电极)16连接。或者,也可以使第3电极16以引线接合连接的方式与另行设置的栅极用的引线框架连接。
半导体芯片10被树脂密封,从外部环境保护。树脂80覆盖半导体芯片10、第1框架20的第1薄板部21与半导体芯片10的第1电极13的接合部、第2框架30的第2厚板部31与半导体芯片10的第2电极15的接合部、以及栅极连接器40与第3电极16的接合部。
此外,树脂80被填充在第1框架20的第1厚板部22的内壁与第2框架30的第2厚板部31的侧面之间。进而,树脂80被填充在第2框架30的第2薄板部32与第1框架20的第1薄板部21之间。此外,第1框架20的第1薄板部21中的、第1厚板部22的相反侧的端部也被树脂80覆盖。
第1框架20的第1薄板部21的第1外表面21a、第1框架20的第1厚板部22的厚度方向(高度方向)的两面、第1厚板部22的外侧的侧面、第2框架30的第2厚板部31的第2外表面31a、以及第2框架30的第2薄板部32中的半导体芯片10的相反侧的面32a不被树脂80覆盖,而是从树脂80露出。
此外,在第2框架30的第2薄板部32一体地设有多条引线32b,这些引线32b从树脂80突出。此外,栅极连接器40的另一端部(引线)40b也从树脂80突出。
如图3(a)所示,第2框架30的第2厚板部31的第2外表面31a、以及从树脂80突出的引线32b的下表面例如经由焊料等的接合件63而接合于安装基板(布线基板)100的导体图案(源极用图案)。
此外,第1框架20的第1厚板部22的面22a例如经由焊料等的接合件65而接合于安装基板100的导体图案(漏极用图案)。
此外,图1(a)所示的栅极连接器40例如形成为鸥翼(gull wing)形状,该栅极连接器40的从树脂80突出的引线40b的表面(图1(a)中纸面近前侧的面)例如经由焊料等的接合件而接合于安装基板100的导体图案(栅极用图案)。
这些在安装面的相反侧从树脂80露出的第1框架20的第1薄板部21的第1外表面21a、以及与第1外表面21a接续的第1厚板部22的面22b作为散热面发挥功能。在该散热面上,还能够根据需要接合散热器。
半导体芯片10所发生的热通过第2框架30散热至安装基板100,并且通过比第1电极13更大面积的第1框架20的第1外表面21a散热至半导体装置1的外部(例如空气中)。
即,实施方式的半导体装置1具有两面散热封装构造,尤其在芯片发热量容易变大的功率用途的情况下能够提高散热性。
第1框架20不仅发挥使半导体芯片10的第1电极13与外部电路电连接的功能,而且作为承担向安装面的相反方向的散热的散热体发挥功能。
此外,如参照图4(b)后述的那样,第2框架30还能够作为承担向安装面的相反方向的散热的散热体来使用。
第2框架30不是使整体变厚,而是通过设置比第2厚板部31薄的第2薄板部32,能够在第2厚板部31与第2薄板部32的台阶部挤入树脂80,能够提高树脂80的剥离强度。
第1框架20的第1外表面21a与第2框架30的第2外表面31a是相互平行的平坦面。半导体装置1的厚度如后述那样,由第1框架20的第1厚板部22的厚度(高度)t规定。
第1框架20的第1厚板部22的厚度(高度)t比第1框架20的第1薄板部21的厚度、半导体芯片10的厚度、以及第2框架30的第2厚板部31的厚度厚。
此外,第1框架20的第1厚板部22的厚度(高度)t与经由接合件61、62而层叠的第1框架20的第1薄板部21、半导体芯片10、以及第2框架30的第2厚板部31的总厚度(高度)大致相同。
作为上述的接合件,并不限于焊料,也可以使用例如银膏那样的导电性膏。不管怎样接合件都从通过加热而熔化的状态或者具有流动性的状态起发生固化,将作为对象的2个要素之间固定并且电连接。
由于部件公差或作为接合件的焊料厚度的偏差,若将第1框架20、半导体芯片10、以及第2框架30仅仅经由接合件61、62而层叠,则在半导体装置1的厚度(高度)上会产生偏差。为了消除该偏差,有效的方法是将第1框架20、半导体芯片10、以及第2框架30的层叠体通过模具或夹具等从框架侧夹持并施力。
即,根据实施方式,如图3(b)所示,首先,在第1框架20的第1薄板部21上供给接合件(例如焊料)61,在该接合件61上搭载半导体芯片10,在半导体芯片10上供给接合件(例如焊料)62,在该接合件62上搭载第2框架30的第2厚板部31。接合件61、62例如通过基于调合器的涂敷等的方法而供给。
并且,将第1框架20、半导体芯片10、以及第2框架30的层叠体通过一对模具(或者夹具)91、92从层叠方向夹持。在模具(例如下模)92的平坦面上搭载第1框架20,模具(例如上模)91的平坦面压抵于第2框架30的第2外表面31a以及第1框架20的第1厚板部22的面22a。
在使接合件61、62回流(熔化)前的状态下,上述层叠体的厚度与第1框架20的第1厚板部22的厚度t相同,或者比厚度t稍厚。
并且,在通过一对模具91、92在层叠方向上对上述层叠体施力的状态下,由回流炉对接合件61、62进行加热而使其熔化。
对于此时的加压,第1框架20的第1厚板部22成为挡板而能够防止多余的力施加到上述层叠体。因此,能够防止对半导体芯片10的损坏(破裂等)。
熔化后的接合件61、62在层叠方向上受压力,部件公差或接合件供给时的厚度偏差被吸收,半导体装置的厚度(高度)由第1框架20的第1厚板部22的厚度(高度)t规定。
在回流工序中熔化的接合件61、62此后固化,半导体芯片10相对于第1框架20以及第2框架30被接合。
然后,使用树脂模制用的模具,模制树脂80。树脂80使第1框架20的第1外表面21a以及第2框架30的第2外表面31a露出,并且将半导体芯片10密封。
另外,还可以考虑在第2框架30的第2外表面31a上也较厚地模制树脂,在为了使第2外表面31a露出而对树脂上表面进行研磨时,通过研磨量的调整来调整封装高度。但是,在研磨工序中,研磨磨刀石、粘贴研磨对象的UV(紫外光,ultraviolet)板等的间接材料费较贵,此外需要UV板粘贴机、上表面研磨机、UV照射器、UV板剥离机等的附带设备,因此工序较长、生产性、开发周期(lead time)差。
根据实施方式,即使不进行研磨工序也能够在图3(b)所示的加压工序中消除半导体装置的厚度(高度)偏差。而且,通过第1框架20的第1厚板部22能够抑制芯片损坏。因此,不需要随附于研磨的间接材料费及设备,生产性良好,能够提供低成本的半导体装置。
第2框架30的第2薄板部32的面32a不限于相对于第2厚板部31的第2外表面31a平直地接续的构造,也可以如图4(a)所示,使第2框架30的第2薄板部32在与第2厚板部31的第2外表面31a之间形成台阶而弯曲,从树脂80的侧面突出。
通过将第2框架30的第2薄板部32中的从树脂80突出的引线32b向第1外表面21a侧弯曲或是向第2外表面31a侧弯曲,来形成所谓鸥翼,能够对应图4(b)所示的安装形态和图4(c)所示的安装形态双方,能够灵活地应对顾客的要求。
图4(b)中,第1框架20的第1外表面21a、和与第1外表面21a接续的第1厚板部22的面22b经由接合件(例如焊料)63而接合于安装基板100的导体图案,第2框架30的引线32b的下表面经由接合件(例如焊料)64而接合于安装基板100的导体图案。
将与第2电极(源极电极)15连接的第2框架30的第2外表面31a作为散热面而使其从封装上表面露出。
此外,从半导体芯片10传导至第1框架20的热经由第1薄板部21散热至安装基板,并且经由第1厚板部22还散热至封装上表面侧以及侧面侧。
图4(c)中,第2框架30的第2外表面31a经由接合件63接合于安装基板100的导体图案,第1框架20的第1厚板部22的面22a经由接合件65接合于安装基板100的导体图案,第2框架30的引线32b的下表面经由接合件64接合于安装基板100的导体图案。
将与第1电极(漏极电极)13连接的第1框架20的第1外表面21a作为散热面而使其从封装上表面露出。
此外,从半导体芯片10传导至第1框架20的热经由第1薄板部21散热至上表面侧,并且经由第1厚板部22还散热至封装侧面侧以及安装基板侧。
对本发明的几个实施方式进行了说明,但这些实施方式是作为例来提示的,并没有要限定发明的范围。这些新的实施方式能够以其他多种形态实施,并且在不脱离发明的主旨的范围内能够进行各种省略、置换、变更。这些实施方式及其变形包含于发明的范围及主旨,并且包含于权利要求书记载的发明及其等效的范围中。

Claims (6)

1.一种半导体装置,具备:
第1框架,具有第1薄板部和第1厚板部,所述第1薄板部具有第1外表面和所述第1外表面的相反侧的第1内表面,所述第1厚板部比所述第1薄板部厚;
第2框架,具有第2薄板部和第2厚板部,所述第2厚板部具有第2外表面和所述第2外表面的相反侧的第2内表面,并且所述第2厚板部比所述第2薄板部厚;
半导体芯片,设置在所述第1框架的所述第1薄板部与所述第2框架的所述第2厚板部之间,具有半导体层、第1电极以及第2电极,所述半导体层具有第1面和所述第1面的相反侧的第2面,所述第1电极设置于所述第1面,并接合于所述第1框架的所述第1薄板部的所述第1内表面,所述第2电极设置于所述第2面,并接合于所述第2框架的所述第2厚板部的所述第2内表面;以及
树脂,将所述半导体芯片密封,并且使所述第1框架的所述第1外表面以及所述第2框架的所述第2外表面露出。
2.如权利要求1所述的半导体装置,
所述第1框架的所述第1厚板部的厚度比所述第1框架的所述第1薄板部的厚度、所述半导体芯片的厚度、以及所述第2框架的所述第2厚板部的厚度厚。
3.如权利要求1或2所述的半导体装置,
所述第2框架的所述第2薄板部在与所述第2厚板部的所述第2外表面之间形成台阶而弯曲,从所述树脂的侧面突出。
4.一种半导体装置的制造方法,
针对下述层叠体进行如下工序:
该层叠体包括:
第1框架,具有第1薄板部和第1厚板部,所述第1薄板部具有第1外表面和所述第1外表面的相反侧的第1内表面,所述第1厚板部比所述第1薄板部厚;
半导体芯片,经由第1接合件层叠在所述第1框架的所述第1内表面上;以及
第2框架,具有第2薄板部和第2厚板部,所述第2厚板部具有第2外表面和形成于所述第2外表面的相反侧且经由第2接合件接合于所述半导体芯片的第2内表面,并且所述第2厚板部比所述第2薄板部厚,
上述工序是指:将所述第1框架的所述第1厚板部作为挡板,在从所述第1框架的所述第1外表面侧以及所述第2框架的所述第2外表面侧施力的状态下,对所述第1接合件以及所述第2接合件进行加热而使其熔化。
5.如权利要求4所述的半导体装置的制造方法,
在使所述第1接合件以及所述第2接合件熔化前的状态下,所述层叠体的厚度大于等于所述第1框架的所述第1厚板部的厚度。
6.如权利要求4或5所述的半导体装置的制造方法,
还具备如下工序:
在通过所述第1接合件以及所述第2接合件的熔化后的固化而使所述半导体芯片与所述第1框架以及所述第2框架接合后,使所述第1框架的所述第1外表面以及所述第2框架的所述第2外表面露出,并且通过树脂将所述半导体芯片密封。
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