WO2018113356A1 - 芯片封装结构及其制造方法 - Google Patents

芯片封装结构及其制造方法 Download PDF

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Publication number
WO2018113356A1
WO2018113356A1 PCT/CN2017/102434 CN2017102434W WO2018113356A1 WO 2018113356 A1 WO2018113356 A1 WO 2018113356A1 CN 2017102434 W CN2017102434 W CN 2017102434W WO 2018113356 A1 WO2018113356 A1 WO 2018113356A1
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WIPO (PCT)
Prior art keywords
chip
mold
substrate
hard cover
package structure
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Application number
PCT/CN2017/102434
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English (en)
French (fr)
Inventor
李扬渊
皮孟月
Original Assignee
苏州迈瑞微电子有限公司
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Publication of WO2018113356A1 publication Critical patent/WO2018113356A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors

Definitions

  • the present invention relates to the field of thermal packaged chips, and more particularly to a chip package structure and a method of fabricating the same.
  • the substrate with the chip fixed is placed in the laminating device, and the fluid formed by the encapsulating material fluid or the molten encapsulating material is injected into the laminating device to encapsulate the chip and the substrate, and after cooling, the package module is formed.
  • the fluid formed by the encapsulating material fluid or the molten encapsulating material is injected into the laminating device to encapsulate the chip and the substrate, and after cooling, the package module is formed.
  • an adhesive is used to bond the hard cover to the surface of the chip, and then the adhesive is cured by high temperature baking.
  • the process speed is slow and the efficiency is low.
  • the steps include surface cleaning, gluing, capping, baking, etc.
  • the process is unstable and the yield is low; if the thickness of the adhesive is unstable, the surface of the final product is not flat; if the thermal expansion coefficient of the packaging material is larger than the thermal expansion coefficient of the substrate is greater than the thermal expansion coefficient of the chip, the chip is highly unstable, and the package surface is Produces a concave warp that requires advanced flattening before fitting a hard cover.
  • the application number is: 20510336488.X
  • the Chinese patent entitled "IC packaging method and its package structure” proposes a new packaging method.
  • the chips are arranged on the substrate in an array manner, and the chip is electrically connected to the substrate by a wire bonding or through-silicon via process; the hard cover plate is pre-placed in the laminating device, and then sprinkled
  • the encapsulating material is inserted into the laminating device, and the molten encapsulating fluid material in the laminating device enters the peripheral space of the chip on the substrate, and the encapsulating material also covers the surface of the chip, and the encapsulating material is less in volume;
  • the characteristics of the material itself, the thermal expansion coefficient of the encapsulating material, substrate, chip and hard cover are large (20ppm/°C), medium (10-15ppm/°C), small (4ppm/°C), and small (less than 10ppm/°C).
  • a package material having a large coefficient of thermal expansion differs from a chip having a small coefficient of thermal expansion in contraction speed to produce a "W" type warp, that is, a central portion of the chip protrudes outward, and a portion between the chip and the chip is recessed inward.
  • the warped encapsulation material can exhibit uneven chromatic aberration through the ink layer of the hard cover, which affects the aesthetics and reliability of the electronic product.
  • the present invention provides a chip package structure and a method of fabricating the same that can improve warpage in a semiconductor package process.
  • the present invention provides a chip package structure comprising:
  • a chip comprising a functional surface and a non-functional surface disposed opposite to the functional surface, and the non-functional surface of the chip is mounted on the first surface of the substrate;
  • the chip, substrate, filler material, and hard cover have coefficients of thermal expansion that match each other.
  • the chip, substrate, filler material and hard cover have a coefficient of thermal expansion of less than 15 ppm/° C.
  • the filler material is formed by the curing of the molten fluid by the chip at the time of encapsulation, the chip, substrate, hard cover and filler material having a coefficient of thermal expansion of less than 15 ppm/° C.
  • the filler material is a prefabricated rigid structure.
  • the prefabricated rigid structure is provided with a hole for receiving the chip.
  • a package is further included, the seal being disposed between the chip, the filler material, and the hard cover.
  • the filling material is a granular filler, which is melted into a fluid when the chip is packaged, and embedded between the filling materials, and then cured to fill the material, the chip and the hard cover The plates are sealed together.
  • the chip, the substrate and the hard cover have a coefficient of thermal expansion of less than 10 ppm/° C. and the package has a coefficient of thermal expansion of more than 10 ppm/° C. and less than 15 ppm/° C.
  • the functional surface of the chip is provided with a capacitive sensing array for detecting a fingerprint
  • the chip is electrically connected to the substrate
  • the second surface of the substrate is provided with a pad.
  • the present invention also provides a method of fabricating a chip package structure, comprising the steps of:
  • S2 providing a substrate having opposite first and second surfaces, and electrically connecting one or more chips to the first surface of the substrate;
  • S3 providing a hard cover plate and a filling material, the hard cover plate comprising a first surface facing the chip and a second surface corresponding to the first surface;
  • the filling material is a prefabricated rigid structure having a hole for receiving the chip.
  • the method further includes:
  • the filling material, and the substrate on which the chip is fixed are placed in the molding apparatus, the filling material is previously adhered to the first surface of the substrate, and the one or more chips are housed in the filling material. Inside the hole.
  • the method further includes:
  • the filling material Before the hard cover, the filling material, and the substrate on which the chip is fixed are placed in the laminating apparatus, the filling material is previously bonded to the first surface of the hard cover.
  • the step S4 specifically includes:
  • the step S4 specifically includes:
  • the step S4 specifically includes:
  • the step S4 specifically includes:
  • the filler material and the encapsulant are of the same material and are used to form a molten fluid.
  • the step S4 specifically includes:
  • the step S4 specifically includes:
  • the filling material is a granular filler
  • the step S4 specifically includes:
  • the step S2 further comprises electrically connecting one or more chips to the substrate through a wire bonding process.
  • the method further includes the step S5: cutting the structure of the completed package to obtain a packaged chip package structure.
  • the invention has the beneficial effects that the filling material is disposed around the chip, and the filling material has a lower coefficient of thermal expansion, which neutralizes the packaging material with a higher coefficient of thermal expansion, so that the chip, the hard cover plate and the substrate are removed.
  • the filler material also has a low coefficient of thermal expansion, and the coefficient of thermal expansion of the chip is about 4 ppm/° C., and the thermal expansion coefficient of the filling material formed by the filler material and the encapsulant is less than 10 ppm/° C., which can be combined with a chip having a small thermal expansion coefficient and hard.
  • the quality cover plate is matched with the substrate and the filling material. During the curing process, the chip, the hard cover plate, the substrate and the filler body have similar shrinkage speeds, which do not cause industrial unacceptable warpage or affect the finished chip module. Aesthetics.
  • the special die-pressing equipment and process are used to form the chip and the hard cover plate in one step, which eliminates the cumbersome surface cleaning, gluing, capping, baking and the like in the conventional manner, greatly reducing the process.
  • the process step reduces the process cost and shortens the process time; in the invention, the package material and the hard cover plate do not need to be demolded, and the package material can completely improve the adhesion without using the release agent, thereby greatly improving the entire chip.
  • the mechanical strength and reliability of the package structure are used to form the chip and the hard cover plate in one step, which eliminates the cumbersome surface cleaning, gluing, capping, baking and the like in the conventional manner, greatly reducing the process.
  • the process step reduces the process cost and shortens the process time; in the invention, the package material and the hard cover plate do not need to be demolded, and the package material can completely improve the adhesion without using the release agent, thereby greatly improving the entire chip.
  • the mechanical strength and reliability of the package structure are used to
  • Figure 1 is a schematic cross-sectional view of a single chip and a fill material after packaging is completed.
  • FIG. 2 is a schematic cross-sectional view of a whole substrate and a plurality of chip packages after the package is completed.
  • FIG. 3 is a schematic exploded view of a prefabricated hard structure filling material and a substrate on which a chip is fixed.
  • 4a-4h are schematic diagrams showing the packaging process of the chip package structure in the first embodiment of the present invention.
  • FIGS. 5a-5b are schematic flow diagrams of a portion of a chip package in the second embodiment. For the sake of brevity, FIGS. 5a and 5b are simultaneously implemented. A schematic diagram of Example 5.
  • FIG. 6a-6b are schematic diagrams showing the flow of a chip package portion in the third embodiment.
  • FIG. 6b is also a schematic diagram of the fourth embodiment.
  • FIG. 7a-7c are schematic flow diagrams of a portion of a six-chip package of the embodiment, which show the fluid state of the filling material and the packaging material after the vacuuming device is clamped, and FIG. 7c is also a schematic diagram of the seventh embodiment. .
  • 8a-8b are schematic cross-sectional views showing the chip package structure after the chip package is completed in the eighth embodiment.
  • 9a-9b are cross-sectional views showing the package structure after the chip package is completed in the ninth embodiment.
  • 10a-10b are schematic cross-sectional views showing the package structure after the chip package is completed in the tenth embodiment, and are shown as a schematic diagram of the fifth embodiment for the sake of brevity.
  • FIG. 11 is a flow chart of a packaging method of the chip package structure of the present invention.
  • the bottom of the chip 3 is a substrate 2 for mounting a chip.
  • the chip 3 is electrically connected to the substrate 2 .
  • the substrate 2 includes an uppermost solder mask (a solder mask), a corelayer (metal layer) under the solder mask, and a solder mask located under the metal layer.
  • Soldermask solder mask
  • the thickness of the substrate 2 composed of a plurality of layers is between 100 micrometers and 300 micrometers.
  • the chip has a functional surface 31 and a non-functional surface 32 disposed opposite the functional surface 31.
  • the functional surface 31 is provided with a circuit that performs a target function, which includes a sensing component and a driving circuit for sensing a fingerprint characteristic.
  • the functional surface 31 is disposed on the upper layer of the chip 3 to be as close as possible to the target finger to be detected during use by the user.
  • Functional surface 31 includes a capacitive sensing array for detection and a driving circuit for driving the capacitive sensing array, and in some embodiments may also include functional circuitry for reading and processing fingerprint images or for performing image processing logic Circuit.
  • the substrate 2 has opposing first and second surfaces 21, 22.
  • a pad 23 for electrical connection is provided on the second surface 22 of the substrate 2, and an output interface of the circuit of the functional surface 31 of the chip 3 is electrically connected to the pad 23, and finally the pad 23 and the processor or The processing unit is electrically connected, and the processor is responsible for processing the fingerprint image detected by the functional surface 31.
  • the non-functional surface 32 of the chip 3 is electrically connected to the first surface 21 of the substrate 2, and the chip 3 is electrically connected to the substrate 2 through a wire bonding process.
  • the chip 3 known to those skilled in the art can also pass through the TSV.
  • the hole process is electrically connected to the substrate 2.
  • a filling material 4 is provided on the first surface 21 of the substrate 2.
  • the filling material 4 surrounds the chip 3 and has a thickness substantially the same as the thickness of the chip 3 such that the upper surface 41 of the filling material 4 and the functional surface 31 of the chip 3 are substantially flush.
  • the thickness of the filling material 4 is substantially flush with the thickness of the chip 3, which is only a preferred embodiment in this embodiment. It is not a final solution.
  • the filling material 4 may be higher than the chip 3 ( Refer to Figures 9a to 10a).
  • the filling material 4 is seamlessly joined to the chip 3 as much as possible during filling, so that the encapsulation material flows into the gap 34 between the filling material 4 and the chip 3 when it is packaged in the mold.
  • the gap 34 is minimized as a preferred embodiment of the present embodiment, and is not a final solution. In some embodiments of the present invention, a certain gap may be reserved for the filling material or the filling material (refer to FIG. 9a to FIG. 9b). ).
  • the upper surface 41 of the chip 3 and the filling material 4 includes an encapsulation layer 5 formed by a packaging process. The thickness of the encapsulation layer 5 is maintained between 50 micrometers and 80 micrometers, and the thickness is set to prevent the package layer 5 from being too thick to cause the fingerprint sensing array signal to be inaccessible.
  • a hard cover 6 is disposed immediately above the encapsulation layer 5. The encapsulation layer 5 is connected to the fixed hard cover 6 and the chip 3 and the filling material 4.
  • the hard cover 6 comprises a conventional material such as a material well known to those skilled in the art including a material having a high dielectric constant such as sapphire, glass, ceramic, etc., having oppositely disposed first surface 51 and second surface 52, said first The surface 51 covers the functional surface 31 of the chip 3, and the second surface 52 is used to carry the direct contact of the finger when the user operates, and the functional surface of the user's finger and the chip 3 under the interface of the hard cover 6 A measurement capacitance is formed between them.
  • a conventional material such as a material well known to those skilled in the art including a material having a high dielectric constant such as sapphire, glass, ceramic, etc., having oppositely disposed first surface 51 and second surface 52, said first The surface 51 covers the functional surface 31 of the chip 3, and the second surface 52 is used to carry the direct contact of the finger when the user operates, and the functional surface of the user's finger and the chip 3 under the interface of the hard cover 6 A measurement capacitance is formed between them.
  • the chip 3, the substrate 2, the filling material 4 and the hard cover 6 have mutually matched coefficients of thermal expansion.
  • the mutual matching of the thermal expansion coefficients means that the difference between the thermal expansion coefficients of the materials used for packaging the chips is not particularly large; for example, the chip 3 is made of a silicon wafer, and its thermal expansion coefficient is fixed at about 4 ppm/° C.
  • a hard cover 6 having a thermal expansion coefficient of less than 15 ppm/° C., a filler material 4, a substrate 2, and a package 53 for forming the encapsulation layer 5 are selected.
  • the above fingerprint sensing chip package structure is packaged according to the following steps:
  • S2 providing a substrate 2 having opposite first and second surfaces 21 and 22, and electrically connecting one or more chips 3 to the first surface 21 of the substrate 2;
  • the hard cover plate 6 includes a first surface 61 facing the chip 3 and a second surface 62 corresponding to the first surface 61;
  • step S1 Further included in step S1,
  • S11-S15 is a conventional technical solution in the art, and it is obvious that those skilled in the art can adjust the processing steps therein, as long as the technical solution of thinning the chip 3 can be achieved as an embodiment of the present invention.
  • step S2 first, the substrate 2 is prepared, preferably the substrate 2 having a thermal expansion coefficient of less than 15 ppm/° C., and the substrate 2 is baked; then the chip 3 is attached to the substrate 2 by a die bonding material (patch adhesive).
  • the plurality of chips 3 are arranged in a row-column alignment manner, the chips 3 are evenly spaced, and then the patch glue is baked, and the chip 3 can be fixed on the substrate 2; then between the substrate 2 and the chip 3.
  • WireBonding is performed to establish an electrical connection between the chip 3 and the substrate 2 to transmit a fingerprint sensing signal.
  • the surface of the chip 3 and the substrate 2 may be plasma-cleaned before the wire is cleaned; after the plasma cleaning is completed, the wire is wired.
  • the gold wire is preferably an alloy wire or a copper wire; after the wire is completed, the chip 3 and the substrate 2 may be again The surface is plasma cleaned.
  • the chip 3 and the substrate 2 may be electrically connected by a tsv (through silicon via) process, and the substrate 2 outputs a signal through the pad 23 disposed on the second surface 22.
  • step S3 Further included in step S3 is:
  • a hard cover 6 having a high dielectric constant (see FIG. 1 or FIG. 2) is prepared.
  • the hard cover 6 may be a high dielectric constant glass, or may be a material known to those skilled in the art such as sapphire glass or ceramics.
  • the second surface of the hard cover 6 is covered with an ink layer to block the components inside the module of the chip 3 from being directly viewed by the user.
  • the sapphire or glass or ceramic preferably has a coefficient of thermal expansion of less than 15 ppm/° C., and other alternative materials used by those skilled in the art have thermal expansion coefficients. It should also be less than 15 ppm/°C.
  • the hard cover 6 is a flat structure, and the opposite side of the hard cover 6 is subjected to plasma cleaning before being placed in the package mold to ensure the adhesion of the package 53 to the hard cover 6 and the cleaning is completed.
  • the standard is that the contact angle of the water droplet on the reverse side of the hard cover 6 should be less than or equal to 30 degrees.
  • the filling material 4 is prepared, the filling material 4 comprises a prefabricated hard structure, the filling material 4 has a planar structure, and the filling material 4 is a material having a thermal expansion coefficient of less than 15 ppm/° C., for example, may be glass fiber; or a thermal expansion coefficient of less than 15 ppm/° C.
  • the composite material for example, may be formed by combining a material having a high coefficient of thermal expansion with a material having a low coefficient of thermal expansion. Referring to FIG. 3, the thickness of the filling material 4 is substantially the same as the thickness of the chip 3.
  • the hole 43 for accommodating the chip 3 is provided thereon. The size, shape and position of the hole 43 are the same as those of the chip 3.
  • step S4 the hard cover 6, the filling material 4, and the substrate 2 to which the chip 3 is fixed are placed in a molding apparatus, and the hard cover 6, the filling material 4, and the substrate on which the chip 3 is fixed are used using the sealing material 53. 2
  • the package is completed in one step in the stamping device to obtain a chip package structure.
  • the prefabricated hard structure 6 and the filling material 4 are bonded to the first surface 21 of the substrate 2 in advance, and The one or more chips 3 are housed in the holes 43 of the filling material 4, and the filling material 4 is adhered to the first surface 21 of the substrate 2, and can be bonded using techniques well known to those skilled in the art, for example, using a crystal glue. fit.
  • a release film 15 is attached to the first mold 11 of the molding apparatus 1; specifically, referring to Figures 4a-4b, the lamination apparatus 1 includes a first mold 11 and a second mold 12, and the first mold 11 includes a support The mold 111 and the press mold 112, the first mold 11 and the second mold 12 form a package cavity 123, and the release film 15 is attached to the first mold 11.
  • the release film 15 is fixed to the support mold 111 and the press mold 112, and the release film 15 is used to support the package 53 particles and the hard cover 6.
  • the role of the release film 15 is to facilitate the removal of the chip package structure formed after the completion of the film curing.
  • a hard cover plate 6 is placed on the release film 15 in the first mold 11, and the first surface 61 faces upward; specifically, as shown in FIG. 4c, above the release film 15 in the first mold 11.
  • the hard cover 6 is placed with the first surface 61 facing upwards, and the hard cover 6 is sized to fit the size of the package cavity 123, and the second surface 62 of the hard cover 6 is in contact with the upper surface of the release film 15.
  • the encapsulant 53 is placed on the first surface 61 of the hard cover 6; specifically, as shown in FIG. 4d, placing a granular encapsulant 53 on the first surface 61 of the hard cover 6, the package
  • the material 53 is a high dielectric constant encapsulant, and may include a molding compound commonly used in the art or other alternative materials known to those skilled in the art.
  • the thermal expansion coefficient of the encapsulant is similar to the thermal expansion coefficient of the chip 3 but less than 15 ppm/° C.
  • a package 53 greater than 10 ppm/° C. and less than 15 ppm/° C. may be selected.
  • the substrate 2 to which the chip 3 is fixed is fixed on the second mold 12; specifically, as shown in FIG. 4e, the substrate 2 electrically connected to the chip 3 is fixed to the second cavity 121 of the second mold 12. Inside (see Fig. 4a), the substrate 2 is fixedly mounted to the second mold, and the functional surface 31 of the chip 3 faces the hard cover 6.
  • the filling material 4 adhered on the substrate 2 is fixed in the second cavity 121 of the second mold 12 as the substrate 2 is fixed, and the fixing of the substrate 2 and the second cavity 121 is non-permanently fixed.
  • the chip package module can be detached from the second cavity 121 when demolding.
  • the encapsulant 53 needs to be added with a small amount of a release agent (wax, silicone oil, etc.) to release the mold, but these small amounts of the release agent affect the adhesion to the surface and the inside of the chip 3 at the same time.
  • the release film 15 is used instead of the conventional release agent, and the package material 53 and the hard cover plate 6 are contacted without demolding, so that the package material 53 can be used without any release agent to greatly improve the adhesion. Greatly improve the mechanical strength and reliability of the entire package structure.
  • the finished chip structure after the package is completed is taken out from the mold by the action of the release film.
  • the packaged substrate 2 is taken out from the package mold 1 and the substrate 2, the chip 3 and the filling material 4 are cut through a dicing process to form a separate chip package module.
  • the first mold 11 includes a support die 111 for supporting the second mold 12 and a press mold 112 for pushing the press forming.
  • the press mold 112 has a cylindrical shape and is disposed inside the support mold 111.
  • a cavity 14 having the same contour as that of the pressing die 112 is formed inside the supporting die 111 to accommodate the pressing die 112.
  • the pressing die 112 can reciprocate in the inner cavity 14 of the supporting die 111, and the cavity 14 is connected to the vacuuming device. (not shown in the figure).
  • the support die 111 is an annular cylinder
  • the press die is a 112 cylinder
  • the support die 111 or the die 112 is coupled to a power unit (not shown) to drive the support die.
  • 111 and the compression mold 112 are relatively moved.
  • the vacuuming device vacuums the inside of the package cavity 123, and the particles of the package material 53 are heated and melted by the heating device (not shown) of the first mold 11, and the support die 111 and The second mold 12 fixes the edge of the substrate 2, the press mold 112 moves upward along the inside of the support mold 111, and the main body portion of the substrate 2 is immersed in the encapsulant 53 in a molten state, and finally on the outer side of the functional surface 31 of the chip 3.
  • the encapsulation layer 5 is formed.
  • the embossing die 112 further includes a buffer mechanism 16 disposed in the accommodating space 113 radially outermost of the embossing die 112.
  • the buffer mechanism 16 has an "L" shape, wherein the main body portion and the accommodating space 113 The top size matches, The shape of the receiving space 113 matches the outer shape of the buffer mechanism 16 to enable the cushioning mechanism 16 to reciprocate within the receiving space 113, including for accommodating a bottom portion of the cushioning mechanism 16 to support the cushioning mechanism to reciprocate.
  • the first receiving space 115 of the spring 163 further includes a second receiving space 114 disposed above the first receiving space 115 and communicating with the package cavity 123 and the first receiving space 115.
  • the extension of the buffer mechanism 16 is disposed at the second Inside the accommodating space 114, the L-shaped space formed by the second accommodating space 114 of the first accommodating space 115 prevents the buffer mechanism 16 from accidentally coming out.
  • the encapsulating material 53 in the encapsulating cavity 123 When the encapsulating material 53 in the encapsulating cavity 123 is excessive, since the encapsulating material 53 is in a molten liquid state, it flows into the second receiving space 114 under the pressing action of the pressing die 112, and the pressing buffer structure 16 moves downward. Filled in the second accommodating space 114 where the buffer structure 16 is vacated, after the package material 53 is solidified and formed, a residual block higher than the package surface is formed on both sides of the whole plate after the package, and can be removed by a cutting step after demolding.
  • the shrinkage of different materials causes a warpage of the surface of the module after curing, in the selection
  • a material having a thermal expansion coefficient (CTE) similar to that of the substrate 2 and the chip 3 should be selected, wherein the thermal expansion coefficient of the chip 3 is 4 ppm/° C., which is determined by the characteristics of the chip 3 made of silicon crystal, in order to be compatible with the chip.
  • the coefficient of thermal expansion of 3 is matched.
  • the preferred coefficient of thermal expansion of the filler material 4 is less than 15 ppm/° C., and is preferably selected from 4 ppm/° C. to 6 ppm/° C.
  • the hard cover 6 should also select a material having a coefficient of thermal expansion close to that of the chip 3.
  • the preferred hard cover 6 has a coefficient of thermal expansion of less than 15 ppm/° C., preferably 4 ppm/° C to 6 ppm/° C.
  • the typical package material 53 has a coefficient of thermal expansion of 15-20 ppm/° C., so that the amount of shrinkage of the package material 53 during packaging is greater than the amount of shrinkage T of the chip 3 and the filler material 4.
  • the calculation formula of the shrinkage amount T is h1*(c1-c2)a/p, where h1 represents the thickness of the material layer; c1 and c2 represent the temperature at the time of packaging and the temperature after cooling; a represents the coefficient of thermal expansion; p is the unit conversion constant.
  • the temperature difference between the filling material 4, the chip 3 and the encapsulant 53 during injection molding and after cooling is c1-c2, and the unit conversion constant p is constant, so the shrinkage of the substrate 2, the filling material 4, the chip 3, and the encapsulant 53 depends on The original height h1 of the material and the coefficient of thermal expansion a; after the encapsulation of the film, the encapsulant gradually solidifies in the filling layer and the upper layer of the chip 3 during the cooling of the encapsulant 53 (refer to FIG. 1), the thickness of the filling material 4 and the thickness of the chip 3.
  • the thickness of the filler material 4 is preferably glass fiber.
  • the glass fiber has a wide range of thermal expansion coefficients, it can be selected to be equal to or similar to the thermal expansion coefficient of the chip 3, for example, 4 ppm/° C. to 6 ppm/° C.
  • the amount of shrinkage in the height direction of the chip 3 and the amount of shrinkage of the filling material 4 are equal or nearly equal, and the speed at which the two are contracted are also nearly the same; further explained, the chip 3 and the package 53 in the height direction.
  • T1 h1 * (c1 - c2) a / p + h2 * (c1 - c2) b / p
  • T2 h3*(c1-c2)e/p+h2*(c1-c2)b/p.
  • the coefficient of thermal expansion a ⁇ e causes h1*(c1-c2)a/p ⁇ h3*(c1-c2)e/p, so the encapsulation layer is located at the height T1 of the upper portion of the chip 3 due to shrinkage and is located
  • the height of the upper portion of the filling material 4 due to shrinkage is approximately equal to T2, that is, T1 ⁇ T2, so that the surface of the sealing material 53 can be kept flat and not warped after cooling.
  • the thickness of the chip 3 and the thickness h3 of the filling material 4 are set to be in the range of 20 um to 400 um, and a material having the same or similar thermal expansion coefficient as the chip 3 is selected as the filling material 4, for example, a thermal expansion coefficient of 4 is selected.
  • the left and right glass fiber layers serve as the filling material 4.
  • the hard cover 6 needs to be adhered to the package layer 5 or the package layer 5 with various adhesives after the package to protect the package layer 5 and isolate the telecommunications. No., or other special effects.
  • the invention adopts a special molding equipment and process to form the chip and the hard cover 6 in one step by means of packaging, thereby eliminating the cumbersome surface cleaning, sizing, affixing, baking, etc. after packaging in the conventional manner. Process, greatly reducing the process steps. Fewer process steps mean lower costs, less process process losses, and shorter process times.
  • the encapsulant 53 needs to be added with a small amount of a release agent (wax, silicone oil, etc.) to release the mold, but these small amounts of the release agent affect the adhesion to the surface and the inside of the chip 3 at the same time.
  • a release agent wax, silicone oil, etc.
  • the encapsulant 53 and the hard cover 6 are contacted without demolding, so that the encapsulant 53 can greatly improve the adhesion without using the release agent at all, thereby greatly improving the mechanical strength and reliability of the entire chip package structure.
  • step S4 Before the hard cover 6, the filler 4, and the substrate 2 to which the chip 3 is attached are placed in the laminating apparatus, the filler 4 and the hard cover 6 are bonded in advance. Then proceed to step S4:
  • step S4 the encapsulant 53 is not pre-placed in the compression molding apparatus 1, but is injected into the fluid encapsulant 53 after vacuum heating, specifically including The following steps:
  • the sealing material 53 is not the liquid encapsulant 53 which is pre-placed in the compression molding apparatus 1 but is vacuum-warmed, and specifically includes the following steps:
  • the difference from the first embodiment or the second embodiment is that the filling material 4 does not overlap the substrate 2 or the hard cover. 6
  • the steps are as follows:
  • the filling material 4 has two options in this embodiment: one is that the filling material 4 is a prefabricated hard structure (refer to FIG. 3). In this case, the packaged chip structure is similar to the structure of the first embodiment.
  • the second filler material 4 is a particulate material or a powder particle (for example, a metal oxide or the like), but the filler material is a non-meltable solid particle, and the formed particles are embedded in the encapsulation layer 5 (refer to FIGS. 10a and 10b).
  • the filling material 4 is used to form a molten fluid instead of a prefabricated hard structure, a filling material and a packaging material.
  • the chip package structure obtained after demolding, the filling material 4 and the encapsulating layer 5 are combined into a single layer of filler as a single powder or granule.
  • the encapsulating material 53 may be mixed in the filling material 4 to form a mixed powder or pellet as an alternative.
  • the filler material 4 may be in the form of a meltable granule or powder, or may be a prefabricated hard structure, but differs from the first embodiment in that the hard structure can be re-solidified after being melted into a fluid in step S45.
  • the difference from the sixth embodiment is that the filling material 4 is not placed on the hard cover 6 in advance, but is vacuumed in the mold clamping.
  • the fluid-filled material injected after warming specifically includes the following steps:
  • step S45 those skilled in the art can easily think of injecting the mixed fluid mixed with the filling material 4 and the encapsulating material 53. As an alternative.
  • a gap 34 is reserved between the side wall of the hole 43 (see FIG. 1) in which the filling material 4 accommodates the chip and the side wall of the chip 3, and the gap 34 can be appropriately enlarged according to actual needs.
  • the slit can be enlarged to accommodate the wire bonding between the chip 3 and the substrate 2. It can be obtained by the encapsulation method described in the first embodiment.
  • the filling material 4 is formed by a molten filling material, and the filling material 4 is fixed as the sealing material 53. Covering the hard cover 6 of the chip 3, the chip module and the imposition structure of the present embodiment can be obtained by the methods disclosed in Embodiment 6 and Embodiment 7.
  • the difference is that the filler material 4 is a pellet material, but the filler material 4 is a non-meltable solid particle, and the formed microparticles are embedded in the encapsulation layer 5, specifically including the following steps:
  • the cured filler material 4 is embedded in the encapsulation layer 5, and the formed particles are uniformly distributed in the encapsulation layer 5, and the filler material 4 has a low coefficient of thermal expansion (4 ppm / ° C - 6 ppm / ° C), the package
  • the material 53 has a high coefficient of thermal expansion (20 ppm / ° C), and the filling body formed by the two exhibits a small coefficient of thermal expansion (less than 15 ppm / ° C), in order to better adapt to the specific application, it can be controlled by the filling material 4
  • the doping ratio controls the thermal expansion coefficient of the filler body, and the more the corresponding filler material 4, the lower the thermal expansion coefficient of the filler body is, the higher the reverse.

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Abstract

一种芯片封装结构及其制造方法，芯片封装结构包括基板（2）、芯片（3）、填充材料（4）和硬质盖板（6）。基板（2）具有相对设置的第一表面（21）和第二表面（22）。芯片（3）包括功能面（31）和与功能面（31）相对设置的非功能面（32），芯片（3）的非功能面（32）安装在基板（2）的第一表面（21）上。填充材料（4）设置在基板（2）的第一表面（21）上围绕芯片（3）。硬质盖板（6）覆盖在芯片（3）的功能面（31）上。芯片（3）、基板（2）、填充材料（4）和硬质盖板（6）具有互相匹配的热膨胀系数；由此能够减少芯片的翘曲。

Description

芯片封装结构及其制造方法
本申请要求了申请日为2016年12月21日，申请号为201611192303.3，发明名称为“芯片封装结构和方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及热封装芯片领域，尤其涉及一种芯片封装结构和构建此种封装结构的制造方法。
背景技术
芯片在封装过程中，将固定有芯片的基板放入压膜设备中，在压膜设备中注入封装料流体或熔融封装料形成的流体来封装芯片和基板，经冷却后形成封装模组。在某些应用需求中，需要在封装模组的表面覆盖硬质盖板。在现有的封装方法中，会使用粘接剂将硬质盖板与芯片表面结合在一起，然后再采用高温烘烤将粘接剂固化。
当前的封装方法的缺点有：
1.工艺速度慢，效率低，步骤多包括表面清洗、上胶、贴盖板、烘烤等步骤；
2.工艺不稳定，良率低；如粘接剂的厚度不稳定，导致最终产品表面不平整；如封装材料的热膨胀系数大于基板的热膨胀系数大于芯片的热膨胀系数导致芯片高度不稳定，封装表面产生内凹翘曲，在贴合硬质盖板前需要先进磨平。
针对上述现有技术存在的缺点，申请号为：20510336488.X，名称为：一种IC封装方法及其封装结构的中国专利提出了一种新的封装方法。该封装方法中将芯片以阵列的方式排布在基板上，并通过焊线或硅通孔工艺使得芯片电性连接固定于基板上；将硬质盖板预先放入压膜设备中，随后撒入封装料，随后固定有芯片的基板被放入压膜设备，压膜设备中熔融的封装流体材料进入基板上芯片外围空间，封装材料还覆盖芯片的表面，此部分封装材料体积较少；由于材料本身的特性，封装材料、基板、芯片和硬质盖板的热膨胀系数分别具有大(20ppm/℃)、中(10～15ppm/℃)、小(4ppm/℃)、小(小于10ppm/℃)的取值。热膨胀系数较大的封装材料与热膨胀系数小的芯片收缩速度不同而产生”W”型翘曲，即芯片的中心部分向外凸出，芯片与芯片之间的部分向内凹陷。在指纹芯片模组等应用中，翘曲的封装材料能够透过硬质盖板的油墨层显像出不均匀的色差，影响电子产品的美观度和可靠性。
因此，有必要提出一种可对芯片封装过程中的翘曲问题进行改进的芯片封装结构及其制造方法，并同时提高工艺速度改良和工艺稳定性。
发明内容
为解决上述技术问题，本发明提供了一种可改善半导体封装过程中的翘曲问题的芯片封装结构及其制造方法。
为达到上述目的，本发明提供了一种芯片封装结构，其包括：
基板，具有相对设置的第一表面和第二表面；
芯片，包括功能面和与功能面相对设置的非功能面，且所述芯片的非功能面安装在所述基板的第一表面上；
填充材料，围绕所述芯片设置在所述基板的第一表面上；
硬质盖板，覆盖在所述芯片的功能面上；
所述的芯片、基板、填充材料和硬质盖板具有互相匹配的热膨胀系数。
优选地，所述芯片、基板、填充材料和硬质盖板的热膨胀系数小于15ppm/℃。
优选地，填充材料是芯片在封装时由熔融的流体固化形成的，所述芯片、基板、硬质盖板和填充材料的热膨胀系数小于15ppm/℃。
优选地，所述填充材料是预制的硬质结构。
优选地，所述预制的硬质结构上开设有用以收容所述芯片的孔。
优选地，还包括封装料，密封设置在所述芯片、填充材料和硬质盖板之间。
优选地，还包括封装料，所述填充材料为颗粒状填充物，所述封装料在芯片封装时熔融为流体，并且嵌入填充材料之间，再经固化后将填充材料、芯片和硬质盖板密封固定在一起。
优选地，所述芯片、基板和硬质盖板的热膨胀系数小于10ppm/℃，所述封装料的热膨胀系数大于10ppm/℃小于15ppm/℃。
优选地，所述芯片的功能面设置有用于检测指纹的电容传感阵列，所述芯片与基板电性连接，且所述基板的第二表面设置焊盘。
为达到上述目的，本发明还提供了一种芯片封装结构的制造方法，其包括以下步骤：
S1：对晶圆进行预处理，并将晶圆切割成若干单颗的芯片；
S2：提供基板，所述基板具有相对设置的第一表面和第二表面，将一个或多个芯片电性连接固定于基板的第一表面上；
S3：提供硬质盖板和填充材料，所述硬质盖板包括朝向芯片的第一表面及与第一表面相对应的第二表面；
S4：将硬质盖板、填充材料和固定有芯片的基板放入压模设备中，使用封装料将硬质盖板、填充材料和固定有芯片的基板在压模设备中一步成型完成封装，得到芯片封装结构。
优选地，所述填充材料是预制的硬质结构，其上开设有收容所述芯片的孔。
优选地，所述步骤S4进行之前还包括：
在硬质盖板、填充材料和固定有芯片的基板放入压模设备前，预先将填充材料与基板的第一表面相贴合，并使所述一个或多个芯片收容于所述填充材料的孔内。
优选地，所述步骤S4进行之前还包括：
在硬质盖板、填充材料和固定有芯片的基板放入压膜设备前，预先将填充材料与硬质盖板的第一表面进行贴合。
优选地，所述步骤S4具体包括：
S41：在压模设备的第一模具中贴入离型膜；
S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
S43：在硬质盖板的第一表面放置封装料；
S44：将固定有芯片的基板固定在第二模具上；
S45：将第二模具和第一模具进行合模，抽真空并加温，使封装料固化形成封装层；
S46：脱模得到芯片封装结构。
优选地，所述步骤S4具体包括：
S41：在压模设备的第一模具中贴入离型膜；
S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
S43：将固定有芯片的基板固定在第二模具上；
S44：将第二模具和第一模具进行合模，抽真空并加温，注入流体封装料，使封装料固化形成封装层；
S45：脱模得到芯片封装结构。
优选地，所述步骤S4具体包括：
S41：在压模设备的第一模具中贴入离型膜；
S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
S43：在硬质盖板第一表面上放置所述填充材料；
S44：将固定有芯片的基板固定在第二模具上；
S45：将第二模具和第一模具进行合模，抽真空并加温，注入流体封装料，使封装料固化形成封装层；
S46：脱模得到芯片封装结构。
优选地，所述步骤S4具体包括：
S41：在压模设备的第一模具中贴入离型膜；
S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
S43：在硬质盖板第一表面上放置填充材料；
S44：在硬质盖板的第一表面和所述填充材料表面放置封装料；
S45：将固定有芯片的基板固定在第二模具上；
S46：将第二模具和第一模具进行合模，抽真空并加温，使封装料固化形成封装层；
S47：脱模得到芯片封装结构。
优选地，所述填充材料和封装料为同一种材料并用于形成熔融的流体。
优选地，所述步骤S4具体包括：
S41：在压模设备的第一模具中贴入离型膜；
S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
S43：在硬质盖板的第一表面放置填充材料；
S44：将固定有芯片的基板固定在第二模具上；
S45：将第二模具和第一模具进行合模，抽真空并加温，使填充材料熔融固化；
S46：脱模得到芯片封装结构。
优选地，所述步骤S4具体包括：
S41：在压模设备的第一模具中贴入离型膜；
S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
S43：将固定有芯片的基板固定在第二模具上；
S44：将第二模具和第一模具进行合模，抽真空并加温，注入填充材料熔融形成的流体，使流体固化；
S45：脱模得到芯片封装结构。
优选地，所述填充材料为颗粒状填充物，所述步骤S4具体包括：
S41：在压模设备的第一模具中贴入离型膜；
S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
S43：在硬质盖板的第一表面放置填充材料和封装料；
S44：将固定有芯片的基板固定在第二模具上；
S45：将第二模具和第一模具进行合模，抽真空并加温，使填充材料熔融固化；
S46：脱模得到芯片封装结构。
优选地，所述步骤S2还包括将一个或多个芯片通过打线工艺与基板电性连接。
优选地，还包括步骤S5：将完成封装的结构进行切割，得到若干封装的芯片封装结构。
本发明的有益效果是：将填充材料围绕芯片设置，同时该填充材料具有较低的热膨胀系数，其会对热膨胀系数较高的封装料产生中和作用，使得除芯片、硬质盖板、基板以及填充材料也具有较低的热膨胀系数，利用芯片的热膨胀系数为4ppm/℃左右，填充材料和封装料形成的填充整体的热膨胀系数小于10ppm/℃，其能够与热膨胀系数较小的芯片、硬质盖板和基板、填充材料相匹配，在固化过程中，上述的芯片、硬质盖板、基板和填充体具有相似的收缩速度不会产生工业上不可接受的翘曲或影响芯片模组成品的美观度。
使用特殊的压模设备和工艺将芯片和硬质盖板用封装的方式一步成型，免去了在传统方式中封装之后繁琐的表面清洗、上胶、贴盖板、烘烤等工艺，大大减少了工艺步骤降低了工艺成本、并缩短了工艺流程时间；本发明中封装料和硬质盖板接触无需脱模，封装料可以完全不用脱模剂而大大提高粘接力，从而大大提高整个芯片封装结构的机械强度和可靠性。
附图说明
图1是封装完成后单一芯片和填充材料剖面示意图。
图2是封装完成后整块基板和多个芯片封装剖面结构示意图。
图3是预制的硬质结构填充材料与固定有芯片的基板分解示意图。
图4a-4h是本发明实施例一中芯片封装结构的封装过程示意图。
图5a-5b是实施例二中芯片封装部分流程示意图，为了简洁表示，图5a和5b同时作为实施 例五的示意图。
图6a-6b是实施例三中芯片封装部分流程示意图，为了简洁表示，图6b同时作为实施例四的示意图。
图7a-7c是实施例六芯片封装部分流程示意图，其展示压膜设备合模后，加温抽真空后填充材料和封装料的流体状态，为了简洁表示，图7c同时作为实施例七的示意图。
图8a-8b是实施例八中芯片封装完成后芯片封装结构的剖面示意图。
图9a-9b是实施例九中芯片封装完成后封装结构的剖面示意图。
图10a-10b是实施例十中芯片封装完成后封装结构的剖面示意图，为了简洁表示，同时作为实施例五的示意图。
图11是本发明芯片封装结构的封装方法流程图。
具体实施方式
以下结合指纹传感器芯片封装过程为例对本发明技术方案进行进一步的详细的说明，需要说明的是附图仅是为了简洁明了的展示本发明的技术思路；附图中展示的结构是作为本发明的一种优选的实施方案不能理解为对本发明的保护范围的一种限制，除指纹传感芯片还可以用于其他半导体封装工艺中，本发明的保护范围以权利要求的内容为准，同时任何根据本发明精神旨意所做的更改或与本发明技术方案构成实质相同或者等同的技术方案均在本发明的保护范围内。
实施例一
请参照图1展示的是芯片封装结构封装完成后的剖面示意图，其中位于芯片3底部的是用于安装芯片的基板2，芯片3与基板2电性连接固定。基板2包括最上层的soldermask(阻焊层)，位于soldermask(阻焊层)下层的corelayer(金属层)，和位于金属层下层的soldermask(阻焊层)。soldermask(阻焊层)用于保护位于中间的corelayer(金属层)，防止corelayer(金属层)电路在焊接过程中发生短路等问题。多层组成的基板2的厚度在100微米至300微米之间。所述芯片具有功能面31和与功能面31相对设置的非功能面32。功能面31设置有执行目标功能的电路，其包括用于感测指纹特性的传感元器件和驱动电路。功能面31设置在芯片3的上层，以在用户使用过程中尽可能的接近待检测目标手指。功能面31包括用于检测的电容传感阵列和用于驱动电容传感阵列的驱动电路，在一些实施方式中还可能包括用于读取和处理指纹图像的功能电路或用于执行图像处理逻辑电路。基板2具有相对的第一表面21和第二表面22。其中，在基板2的第二表面22设置用于电联接的焊盘23，所述芯片3功能面31的电路的输出接口与所述焊盘23电性连接，最终焊盘23与处理器或处理单元电性连接，处理器负责处理功能面31检测到的指纹图像。
芯片3的非功能面32电性固定连接在基板2的第一表面21上，芯片3通过打线工艺与基板2电性连接，当然本领域技术人员公知的芯片3还可以通过TSV(硅通孔)工艺与基板2电性连接。
在基板2的第一表面21上设置有填充材料4。填充材料4围绕在芯片3周围，其厚度与芯片3的厚度大致相同，使得填充材料4的上表面41和芯片3的功能面31大致齐平。填充材料4的厚度与芯片3的厚度大致齐平只是本实施例中一种优选的实施方案，不是终局方案在本发明的另一些实施例中还可以采用填充材料4高于芯片3的方式(参照图9a至图10a)。填充材料4在填充时尽量与所述芯片3无缝连接，使得在模具中封装时，减少封装料流入填充材料4和芯片3之间的缝隙34。尽量减少所述缝隙34作为本实施例一种优选的实施方式，不是终局方案，在另本发明一些实施方式中还可以预留一定的缝隙供填充材料或封装料填充(参照图9a至图9b)。在芯片3和填充材料4的上表面41包括经过封装工艺形成的封装层5。封装层5的厚度保持在50微米至80微米之间，设置此厚度能够防止封装层5过厚造成指纹传感阵列信号无法穿透。紧邻封装层5的上方设置硬质盖板6。封装层5连接固定硬质盖板6和芯片3以及填充材料4。硬质盖板6包括常规的材料例如本领域技术人员熟知的材料包括蓝宝石、玻璃、陶瓷等具有高介电常数的材料，具有相对设置的第一表面51和第二表面52，所述第一表面51覆盖在所述芯片3的功能面31上，所述第二表面52用于承载用户操作时手指的直接接触，在硬质盖板6的介隔下用户手指与芯片3的功能面31之间形成测量电容。
为了减少在芯片封装结构在压膜后固化过程中发生翘曲，所述的芯片3、基板2、填充材料4和硬质盖板6具有互相匹配的热膨胀系数。热膨胀系数的相互匹配是指各种用于封装芯片的材料的热膨胀系数之间的差异不是特别大；例如芯片3是硅晶圆制作而成，其热膨胀系数固定的为4ppm/℃左右，相应的为了匹配芯片3的热膨胀系数选用热膨胀系数小于15ppm/℃的硬质盖板6、填充材料4、基板2和用于形成封装层5的封装料53。还可以进一步优化上述选择方案将硬质盖板6、填充材料4和基板2的选择范围控制在热膨胀系数小于10ppm/℃的材料，将用于形成封装层5的封装料53的选择范围控制在大于10ppm/℃小于15ppm/℃的材料，这样，在某些技术方案中混合了颗粒状的填充材料4(参照图10a)，填充材料4和封装层5形成的填充体中和了填充材料4和封装层5的热膨胀系数，整体表现出较低的热膨胀系数，还可以通过控制填充材料4所占的比例来控制热填充体的膨胀系数。
上述的指纹传感芯片封装结构按照如下的步骤进行封装：
请参见图11
S1：对晶圆进行预处理，并将晶圆切割成若干单颗的芯片3；
S2：提供基板2，所述基板2具有相对设置的第一表面21和第二表面22，将一个或多个芯片3电性连接固定于基板2的第一表面21上；
S3：提供硬质盖板6和填充材料4，所述硬质盖板6包括朝向芯片3的第一表面61及与第一表面61相对应的第二表面62；
S4：将硬质盖板6、填充材料4和固定有芯片3的基板2放入压模设备中，使用封装料53将硬质盖板6、填充材料4和固定有芯片3的基板2在压模设备中一步成型完成封装，得到芯片封装结构。
步骤S1中进一步包括，
S11在晶圆表面贴减薄膜；
S12：对晶圆进行减薄；
S13：去除晶圆表面的减薄膜；
S14：在晶圆背面贴切割膜；
S15：将晶圆切割成若干单颗的芯片3。
S11-S15为本领域常规的技术方案，显然本领域技术人员可以对其中的处理步骤进行调整，只要能够达到减薄芯片3的技术方案都可作为本发明的实施方式。
在步骤S2中具体的包括：首先，准备基板2，优选热膨胀系数小于15ppm/℃的基板2，并将基板2进行烘烤；然后用固晶材料(贴片胶)将芯片3贴至基板2上，多个芯片3以行列对齐的方式排列程矩阵，芯片3之间保持均匀的间距，然后烘烤贴片胶，芯片3即可固定于基板2上；然后在基板2和芯片3之间进行打线(WireBonding)，其目的是在芯片3和基板2之间建立电性连接以传递指纹传感信号。打线前可以对芯片3和基板2表面进行等离子清洗；等离子清洗完成后进行打线，本实施例中金线优选地为合金线或铜线；打线完成后可再次对芯片3和基板2表面进行等离子清洗。
除了打线工艺还可以采用tsv(硅通孔)工艺电性连接芯片3和基板2，基板2通过设置在第二表面22的焊盘23输出信号。
在步骤S3中进一步包括：
准备高介电常数的硬质盖板6(参照图1或图2)，硬质盖板6可以为高介电常数玻璃，也可以为蓝宝石玻璃或陶瓷等本领域技术人员公知的材料，通常在所述硬质盖板6的第二表面覆盖有油墨层以阻隔芯片3模组内部的元件被用户直视。在本实施中所述蓝宝石或玻璃或陶瓷优选热膨胀系数小于15ppm/℃，本领域技术人员选用的其他的可替代材料热膨胀系数 也应当小于15ppm/℃。本实施例中硬质盖板6为平面结构，放入封装模具之前还需对硬质盖板6的反面进行等离子清洗，以保证封装料53对硬质盖板6的粘接力，清洗完成的标准为硬质盖板6反面的水滴接触角应小于或等于30度。
准备填充材料4，填充材料4包括预制的硬质结构，填充材料4呈平面结构，填充材料4是热膨胀系数小于15ppm/℃的材料，例如可以是玻璃纤维；也可以是热膨胀系数小于15ppm/℃的复合材料，例如，可以是热膨胀系数高的材料与热膨胀系数低的材料复合形成的。请参照图3，填充材料4的厚度与芯片3的厚度大致相同，其上设置有收容芯片3的孔43，孔43的大小和形状以及位置与芯片3相同。在步骤S4中将硬质盖板6、填充材料4和固定有芯片3的基板2放入压模设备中，使用封装料53将硬质盖板6、填充材料4和固定有芯片3的基板2在压模设备中一步成型完成封装，得到芯片封装结构。
在硬质盖板6、填充材料4和固定有芯片3的基板2放入压膜设备前，预先将预制的硬质结构6、填充材料4与基板2的第一表面21相贴合，并使所述一个或多个芯片3收容在填充材料4的孔43内，填充材料4与基板2的第一表面21贴合，可使用本领域技术人员公知的技术进行贴合例如使用晶固胶贴合。
参照图4a-4h所示，在上述填充材料4和基板2贴合后进一步进行步骤：
S41：在压模设备1的第一模具11中贴入离型膜15；具体地，参照图4a-4b，压膜设备1包括第一模具11和第二模具12，第一模具11包括支撑模111和压合模112，第一模具11和第二模具12形成封装腔123，在第一模具11贴入离型膜15。离型膜15被固定在支撑模111和压合模112上，离型膜15用于承托封装料53颗粒和硬质盖板6。离型膜15的作用是在完成压膜固化后形成的芯片封装结构易于从模具中脱出。
S42：在第一模具11中的离型膜15上放入硬质盖板6，第一表面61朝上；具体地，参图4c所示，在第一模具11中离型膜15的上方放入硬质盖板6，第一表面61朝上，硬质盖板6的尺寸应刚好符合封装腔123的尺寸，硬质盖板6的第二表面62与离型膜15上表面接触。
S43：在硬质盖板6第一表面61上放置所述封装料53；具体地，参图4d所示，在硬质盖板6的第一表面61放置颗粒状的封装料53，该封装料53为高介电常数封装料，可以包括本领域常用的塑封料或本领域技术人员公知的其他替代原料，优选的，封装料的热膨胀系数与芯片3的热膨胀系数近似但小于15ppm/℃，例如可选大于10ppm/℃小于15ppm/℃的封装料53。
S44：将固定有芯片3的基板2固定在第二模具12上；具体地，参图4e所示，将电性连接固定有芯片3的基板2固定在第二模具12的第二模腔121内(参照图4a)，基板2与第二模具固定安装，芯片3的功能面31朝向硬质盖板6。基板2上贴合的填充材料4随着基板2被固定在第二模具12的第二模腔内121内，所述的基板2与第二模腔121的固定为非永久性固定，其在芯片封装模组脱模时可以与第二模腔121脱离。
S45：将第二模具12和第一模具11进行合模，抽真空并加温，使封装料53固化形成封装层5；具体地，参照图4f和图4g，将第一模具11和第二模具12进行沿着图中箭头指示的方向进行合模，抽真空并加温至170℃～180℃，使封装料53颗粒熔融，并对第一模具11和第二模具12进行压膜，使封装料53压缩后固化成型。
S46：脱模得到芯片封装结构。
通常在传统封装工艺中，封装料53需要加入少量的脱模剂(蜡，硅油等)以便脱模，但是这些少量的脱模剂会同时影响对芯片3表面和内部的粘接力。在本实施例中，使用离型膜15代替传统的脱模剂，封装料53和硬质盖板6接触无需脱模，所以封装料53可以完全不用脱模剂而大大提高粘接力，从而大大提高整个封装结构的机械强度和可靠性。
参照图4h封装完成后的整版芯片结构在脱模膜的作用下从模具中脱出，
冷却后将封装后的基板2从封装模具1中取出并经过切割工艺将基板2、芯片3和填充材料4切割形成独立的芯片封装模块。
进一步对上述压膜设备和压膜过程中设备的部件配合关系和工作状态描述如下：
继续参照图4f和图4g第一模具11包括用于承托第二模具12的支撑模111和用于推动施压成型的压合模112。压合模112呈柱体状，设置在支撑模111的内部。所述支撑模111内部形成与压合模112轮廓相同的腔体14，以容纳压合模112，压合模112可在支撑模111内腔体内14往复运动，腔体14与抽真空设备连通(图中未示出)。典型地，所述支撑模111为环形柱体，所述压合模为112圆柱体，所述支撑模111或压合模112与动力装置连接(图中未示出)动力装置可推动支撑模111和压合模112相对运动。
继续参照图4f和图4g，进行芯片封装时，抽真空设备将封装腔123内部抽真空，封装料53颗粒通过第一模具11的加热装置(图中未示出)加热熔融，支撑模111和第二模具12固定基板2的边缘，压合模112沿着支撑模111内部向上移动，基板2的主体部分被浸没在熔融状态下的封装料53中，最终在芯片3的功能面31的外侧形成封装层5。
压合模112还包括缓冲机构16，两个缓冲机构16设置在压合模112径向最外侧的收容空间内113，所述缓冲机构16的呈“L”型，其中主体部分与收容空间113的顶部大小匹配， 收容空间113的形状与缓冲机构16的外形相匹配，以使得缓冲机构16能够在收容空间113内往复运动，其中包括用于收容设置在所述缓冲机构16的底部以支撑所述缓冲机构往复运动的弹簧163的第一收容空间115，还包括设置在第一收容空间115上方并连通封装腔123和第一收容空间115的第二收容空间114，所述缓冲机构16的延伸部设置在第二收容空间114内部，第一收容空间115的第二收容空间114形成的L形空间防止缓冲机构16意外脱出。
当封装腔123中的封装料53过多时，由于封装料53处于熔融的液态，其在压合模112的挤压作用下流转到第二收容空间114内，并挤压缓冲结构16向下移动填充在缓冲结构16空出的部分第二收容空间114处，封装料53固化成型后在封装后整板两侧形成高出封装表面的余料块，可在脱模后通过切割步骤去除。
进一步对填充材料4减小翘曲的原理进行阐述：
在上述封装过程中：在步骤S41至S46中为了减少封装料53冷却固化的过程因不同材料热膨胀系数(CTE)不同导致不同材料的收缩量不同造成固化后模组表面翘曲的现象，在选择填充材料4时应当选择与基板2和芯片3热膨胀系数(CTE)相近的材料，其中芯片3的热膨胀系数为4ppm/℃，其是由于芯片3由硅晶体制作而成的特性决定，为了与芯片3的热膨胀系数匹配，优选的填充材料4的热膨胀系数小于15ppm/℃，以4ppm/℃-6ppm/℃为最佳选择。同样的，硬质盖板6也应当选择热膨胀系数与芯片3接近的材料，优选的硬质盖板6的热膨胀系数小于15ppm/℃，以4ppm/℃-6ppm/℃为最佳。
参照图4h典型的封装料53的热膨胀系数为15-20ppm/℃，因此封装过程中封装料53的收缩量大于芯片3和填充材料4的收缩量T。收缩量T的计算公式是h1*(c1-c2)a/p，其中h1代表材料层的厚度；c1、c2分别代表封装时的温度和冷却后的温度；a代表热膨胀系数；p是单位换算常量。填充材料4、芯片3和封装料53的注塑封装时和冷却后的温差都是c1-c2，单位换算常量p不变，因此基板2、填充材料4、芯片3和封装料53的收缩量依赖材料的原始高度h1和热膨胀系数a；在封装压膜后，封装料53冷却的过程中封装料逐渐固化在填充层和芯片3的上层(参照图1)，填充材料4的厚度和芯片3的厚度相等，填充材料4优选玻璃纤维，因为玻璃纤维的热膨胀系数可选的范围大，因此可选择与芯片3热膨胀系数相等或近似，例如4ppm/℃-6ppm/℃。在封装冷却的过程中，芯片3高度方向上收缩量和填充材料4的收缩量相等或几乎相等，两者收缩的速度也几近相同；进一步地解释，在高度方向上芯片3和封装料53颗粒的收缩总量T1＝h1*(c1-c2)a/p+h2*(c1-c2)b/p,相似的在剖面方向上的封装层5和填充材料4产生的收缩总量是T2＝h3*(c1-c2)e/p+h2*(c1-c2)b/p。两等式共有部分 h2*(c1-c2)b/p表示封装层5收缩的高度，两等式区别部分中除热膨胀系数部分h1*(c1-c2)/p＝h3*(c1-c2)/p，芯片3热膨胀系数a≈e(填充材料热膨胀系数)致使h1*(c1-c2)a/p≈h3*(c1-c2)e/p，因此封装层位于芯片3上方部分因收缩下降的高度T1与位于填充材料4上部分因收缩下降的高度近似相等T2即T1≈T2，致使封装料53在冷却后也表面能够保持平整不翘曲。
本发明设置芯片3的厚度h1与填充材料4的厚度h3相等两者的厚度在20um至400um的范围内，选择热膨胀系数与芯片3相同或近似的材料作为填充材料4，例如选用热膨胀系数为4左右的玻璃纤维层作为填充材料4。在厚度相同热膨胀系数相同或相近的情况下芯片3和填充材料4从模具封装温度下降到室温时收缩量相同，封装层5在芯片3和填充材料4形成的平面上，因此封装层5在冷却收缩的过程中仍然能过够保持其上表面水平不出现翘曲的情况，能够保持指纹芯片的美观度同时提高工艺水平。
另外，现有普通的芯片封装工艺中，硬质盖板6需要在封装之后用各种粘接剂粘接在封装层5上或是封装层5周围，以起到保护封装层5、隔绝电讯号、或者其他的特殊作用。而本发明用特殊的压模设备和工艺将芯片和硬质盖板6用封装的方式一步成型，免去了在传统方式中封装之后繁琐的表面清洗、上胶、贴盖板、烘烤等工艺，大大减少了工艺步骤。较少的工艺步骤意味着更低的成本，更少的过程工艺损失，更短的工艺流程时间。通常在传统封装工艺中，封装料53需要加入少量的脱模剂(蜡，硅油等)以便脱模，但是这些少量的脱模剂会同时影响对芯片3表面和内部的粘接力。但是在发明，封装料53和硬质盖板6接触无需脱模，所以封装料53可以完全不用脱模剂而大大提高粘接力，从而大大提高整个芯片封装结构的机械强度和可靠性。
实施例二
参照图5a和图5b与实施例一相比区别技术方案在于在步骤S4。在硬质盖板6、填充材料4和固定有芯片3的基板2放入压膜设备前，预先将填充材料4和硬质盖板6进行贴合。随后进行S4步骤：
S41：在压模设备的第一模具11中贴入离型膜15
S42：在第一模具中的离型膜15上放入硬质盖板6，第一表面61朝上；
S43：在硬质盖板6的第一表面61放置封装料53；
S44：将固定有芯片3的基板2固定在第二模具12上；
S45：将第二模具12和第一模具11进行合模，抽真空并加温，使封装料53固化形成封装层5；
S46：脱模得到芯片3封装结构。
其余结构及封装方法均与实施例一相同，不再进行赘述。
实施例三
参照图6a和图6b，其与实施例一或实施例二的区别在于步骤S4，封装料53不是预先放置在压模设备1中而是抽真空加温后注入的流体封装料53，具体包括如下步骤：
S41：在压模设备的第一模具中贴入离型膜15；
S42：在第一模具11中的离型膜上放入硬质盖板6，第一表面61朝上；
S43：将固定有芯片4的基板2固定在第二模具12上；
S44：将第二模具12和第一模具11进行合模，抽真空并加温，注入流体封装料53，使封装料53固化形成封装层5；
S45：脱模得到芯片封装结构。
其余结构及封装方法均与实施例一相同，不再进行赘述。
实施例四
参照图6b(与填充材料和硬质盖板贴合的情形共用)，其与实施例一或实施例二不同在于，在进行步骤S4前填充材料51不预先与基板2或硬质盖板6贴合，同时封装料53不是预先放置在压模设备1中而是抽真空加温后注入的流体封装料53，具体地，包括以下步骤：
S41：在压模设备1的第一模具11中贴入离型膜15；
S42：在第一模具11中的离型膜15上放入硬质盖板6，第一表面朝61上；
S43：在硬质盖板第一表面62上放置所述填充材料4；
S44：将固定有芯片3的基板2固定在第二模具12上；
S45：将第二模具12和第一模具11进行合模，抽真空并加温，注入流体封装料53，使封装料53固化形成封装层5；
S46：脱模得到芯片封装结构。
其余结构及封装方法均与实施例一相同，不再进行赘述。
实施例五
参照图5a和图5b(与填充材料和硬质盖板贴合的情形共用)，其与实施例一或实施例二相比区别在于步骤S4，填充材料4不与基板2或者硬质盖板6进行任何预先贴合，步骤如下：
S41：在压模设备1的第一模具11中贴入离型膜15；
S42：在第一模具11中的离型膜15上放入硬质盖板6，第一表面61朝上；
S43：在硬质盖板6第一表面61上放置所述填充材料4；
S44：在硬质盖板6的第一表面61和所述填充材料4表面放置封装料53；
S45：将固定有芯片3的基板2固定在第二模具12上；
S46：将第二模具12和第一模具11进行合模，抽真空并加温，使封装料53固化形成封装层5；
S47：脱模得到芯片封装结构。其余结构及封装方法均与实施例一相同，在此不再进行赘述。
需要注意的是填充材料4，在此实施例中有两种选择：其一是填充材料4是一种预制的硬质结构(参照图3)此种情况封装后芯片结构与实施例一结构类似；其二填充材料4是颗粒料或粉末微粒(例如金属氧化物等)，但填充材料是不可熔融的固态颗粒，其形成的微粒嵌在封装层5中(参照图10a和图10b)。
实施例六
参照图7a-7c，与实施例一或实施例二相比，区别技术方案在于步骤S4，所述填充材料4用于形成熔融的流体而不是预制的硬质结构、填充材料同时起到封装料53封装的作用。
具体包括以下步骤：
S41：在压模设备的第一模具11中贴入离型膜15；
S42：在第一模具11中的离型膜15上放入硬质盖板6，第一表面61朝上；
S43：在硬质盖板6的第一表面61放置填充材料4；
S44：将固定有芯片3的基板2固定在第二模具12上；
S45：将第二模具12和第一模具11进行合模，抽真空并加温，使填充材料4熔融料固化；
S46：脱模得到芯片封装结构。
参照图9a和9b，脱模后得到的芯片封装结构，填充材料4和封装层5合为同一层填充料为单一的粉末料或颗粒。另外，在步骤S43中，本领域技术人员易于想到可以在填充材料4中混合封装料53，以形成一种混合的粉末或颗粒料作为替代方案。填充材料4形态可以为可熔融的颗粒或粉末状，还可以是一种预制的硬质结构，但与实施例一不同之处在于硬质结构可在步骤S45熔融成为流体后再重新固化。
其余结构及封装方法均与实施例一相同，在此不再进行赘述。
实施例七
参照图7c(与填充材料用于形成熔融的流体的情形共用)，与实施例六相比区别在于，填充材料4不是预先放置在硬质盖板6上，而是在合模抽真空并加温后注入的流体填充材料，具体地包括以下步骤：
S41：在压模设备的第一模具11中贴入离型膜15；
S42：在第一模具中11的离型膜15上放入硬质盖板6，第一表面61朝上；
S43：将固定有芯片3的基板2固定在第二模具12上；
S44：将第二模具12和第一模具11进行合模，抽真空并加温，注入填充材料熔融形成的流体，使流体固化；
S45：脱模得到芯片封装结构。
参照图9a和9b脱模后得到的芯片封装结构，填充材料4和封装层5合为同一层，另外在步骤S45，本领域技术人员易于想到注入混合有填充材料4和封装料53的混合流体作为替代方案。
其余结构及封装方法均与实施例六相同，在此不再进行赘述。
实施例八
参照图8a-8b中展示的单颗芯片模组和整板结构剖面图，其中包括硬质盖板6、填充材料4、封装层5和基板2。与实施例1的区别在于，在填充材料4收容芯片的孔43(参照图1)的侧壁和芯片3的侧壁之间预留一缝隙34，可根据实际需求适当扩大所述缝隙34，例如可扩大所述缝隙用于收容芯片3和基板2之间的打线。其可通过实施例一中描述的封装方法获得。
实施例九
参照图9a-9b中展示的单颗芯片模组和整板结构剖面图，与实施例一的区别在于，填充材料4是通过熔融的填充材料形成的，同时填充材料4作为封装料53使用固定覆盖芯片3的硬质盖板6，本实施例芯片模组和整版结构可通过实施例六和实施例七中披露的方法获得。
实施例十
与实施例五相比，区别是填充材料4是颗粒料，但填充材料4是不可熔融的固态颗粒，其形成的微粒嵌在封装层5中，具体地包括以下步骤：
S41：在压模设备1的第一模具11中贴入离型膜15；
S42：在第一模具11中的离型膜15上放入硬质盖板6，第一表面朝上；
S43：在硬质盖板6的第一表面放置填充材料4和封装料53；
S44：将固定有芯片3的基板2固定在第二模具12上；
S45：将第二模具12和第一模具11进行合模，抽真空并加温，使填充材料4熔融固化；
S46：脱模得到芯片封装结构。
参照图10a和10b，固化后的填充材料4嵌在封装层5中，其形成微粒均匀分布在封装层5内，填充材料4具有较低的热膨胀系数(4ppm/℃-6ppm/℃)，封装料53具有较高的热膨胀系数(20ppm/℃)，两者形成的填充体对外表现出的热膨胀系数较小(小于15ppm/℃)，为了更好的适应具体应用，可以通过控制填充材料4的参杂比例控制填充体的热膨胀系数，相应的参杂越多的填充材料4填充体的热膨胀系数越低相反则越高。

Claims (23)

  1. 一种芯片封装结构，其特征在于，包括：
    基板，具有相对设置的第一表面和第二表面；
    芯片，包括功能面和与功能面相对设置的非功能面，且所述芯片的非功能面安装在所述基板的第一表面上；
    填充材料，围绕所述芯片设置在所述基板的第一表面上；
    硬质盖板，覆盖在所述芯片的功能面上；
    所述的芯片、基板、填充材料和硬质盖板具有互相匹配的热膨胀系数。
  2. 根据权利要求1所述的芯片封装结构，其特征在于，所述芯片、基板、填充材料和硬质盖板的热膨胀系数小于15ppm/℃。
  3. 根据权利要求1所述的芯片封装结构，其特征在于，填充材料是芯片在封装时由熔融的流体固化形成的，所述芯片、基板、硬质盖板和填充材料的热膨胀系数小于15ppm/℃。
  4. 根据权利要求2所述的芯片封装结构，其特征在于，所述填充材料是预制的硬质结构。
  5. 根据权利要求4所述的芯片封装结构，其特征在于，所述预制的硬质结构上开设有用以收容所述芯片的孔。
  6. 根据权利要求4所述的芯片封装结构，其特征在于，还包括封装料，密封设置在所述芯片、填充材料和硬质盖板之间。
  7. 根据权利要求1所述的芯片封装结构，其特征在于，还包括封装料，所述填充材料为颗粒状填充物，所述封装料在芯片封装时熔融为流体，并且嵌入填充材料之间，再经固化后将填充材料、芯片和硬质盖板密封固定在一起。
  8. 根据权利要求6或7所述的芯片封装结构，其特征在于，所述芯片、基板和硬质盖板的热膨胀系数小于10ppm/℃，所述封装料的热膨胀系数大于10ppm/℃小于15ppm/℃。
  9. 根据权利要求1-7任一项所述的芯片封装结构，其特征在于，所述芯片的功能面设置有用于检测指纹的电容传感阵列，所述芯片与基板电性连接，且所述基板的第二表面设置焊盘。
  10. 一种芯片封装结构的制造方法，其特征在于，包括以下步骤：
    S1：对晶圆进行预处理，并将晶圆切割成若干单颗的芯片；
    S2：提供基板，所述基板具有相对设置的第一表面和第二表面，将一个或多个芯片电性连接固定于基板的第一表面上；
    S3：提供硬质盖板和填充材料，所述硬质盖板包括朝向芯片的第一表面及与第一表面相对应的第二表面；
    S4：将硬质盖板、填充材料和固定有芯片的基板放入压模设备中，使用封装料将硬质盖板、填充材料和固定有芯片的基板在压模设备中一步成型完成封装，得到芯片封装结构。
  11. 根据权利要求10所述的芯片封装结构的制造方法，其特征在于，所述填充材料是预制的硬质结构，其上开设有收容所述芯片的孔。
  12. 根据权利要求11所述的芯片封装结构的制造方法，其特征在于，所述步骤S4进行之前还包括：
    在硬质盖板、填充材料和固定有芯片的基板放入压模设备前，预先将填充材料与基板的第一表面相贴合，并使所述一个或多个芯片收容于所述填充材料的孔内。
  13. 根据权利要求11所述的芯片封装结构的制造方法，其特征在于，所述步骤S4进行之前还包括：
    在硬质盖板、填充材料和固定有芯片的基板放入压膜设备前，预先将填充材料与硬质盖板的第一表面进行贴合。
  14. 根据权利要求12或13所述的芯片封装结构的制造方法，其特征在于，所述步骤S4具体包括：
    S41：在压模设备的第一模具中贴入离型膜；
    S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
    S43：在硬质盖板的第一表面放置封装料；
    S44：将固定有芯片的基板固定在第二模具上；
    S45：将第二模具和第一模具进行合模，抽真空并加温，使封装料固化形成封装层；
    S46：脱模得到芯片封装结构。
  15. 根据权利要求12或13所述的芯片封装结构的制造方法，其特征在于，所述步骤S4具体包括：
    S41：在压模设备的第一模具中贴入离型膜；
    S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
    S43：将固定有芯片的基板固定在第二模具上；
    S44：将第二模具和第一模具进行合模，抽真空并加温，注入流体封装料，使封装料固化形成封装层；
    S45：脱模得到芯片封装结构。
  16. 根据权利要求11所述的芯片封装结构的制造方法，其特征在于，所述步骤S4具体包括：
    S41：在压模设备的第一模具中贴入离型膜；
    S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
    S43：在硬质盖板第一表面上放置所述填充材料；
    S44：将固定有芯片的基板固定在第二模具上；
    S45：将第二模具和第一模具进行合模，抽真空并加温，注入流体封装料，使封装料固化形成封装层；
    S46：脱模得到芯片封装结构。
  17. 根据权利要求10或11所述的芯片封装结构的制造方法，其特征在于，所述步骤S4具体包括：
    S41：在压模设备的第一模具中贴入离型膜；
    S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
    S43：在硬质盖板第一表面上放置填充材料；
    S44：在硬质盖板的第一表面和所述填充材料表面放置封装料；
    S45：将固定有芯片的基板固定在第二模具上；
    S46：将第二模具和第一模具进行合模，抽真空并加温，使封装料固化形成封装层；
    S47：脱模得到芯片封装结构。
  18. 根据权利要求10所述的芯片封装结构的制造方法，其特征在于，所述填充材料和封装料为同一种材料并用于形成熔融的流体。
  19. 根据权利要求18所述的芯片封装结构的制造方法，其特征在于，所述步骤S4具体包括：
    S41：在压模设备的第一模具中贴入离型膜；
    S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
    S43：在硬质盖板的第一表面放置填充材料；
    S44：将固定有芯片的基板固定在第二模具上；
    S45：将第二模具和第一模具进行合模，抽真空并加温，使填充材料熔融固化；
    S46：脱模得到芯片封装结构。
  20. 根据权利要求18所述的芯片封装结构的制造方法，其特征在于，所述步骤S4具体包括：
    S41：在压模设备的第一模具中贴入离型膜；
    S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
    S43：将固定有芯片的基板固定在第二模具上；
    S44：将第二模具和第一模具进行合模，抽真空并加温，注入填充材料熔融形成的流体，使流体固化；
    S45：脱模得到芯片封装结构。
  21. 根据权利要求10所述的芯片封装结构的制造方法，其特征在于，所述填充材料为颗粒状填充物，所述步骤S4具体包括：
    S41：在压模设备的第一模具中贴入离型膜；
    S42：在第一模具中的离型膜上放入硬质盖板，第一表面朝上；
    S43：在硬质盖板的第一表面放置填充材料和封装料；
    S44：将固定有芯片的基板固定在第二模具上；
    S45：将第二模具和第一模具进行合模，抽真空并加温，使填充材料熔融固化；
    S46：脱模得到芯片封装结构。
  22. 根据权利要求10所述的芯片封装结构制造方法，其特征在于，所述步骤S2还包括将一个或多个芯片通过打线工艺与基板电性连接。
  23. 根据权利要求10所述的芯片封装结构制造方法，其特征在于，还包括步骤S5：将完成封装的结构进行切割，得到若干封装的芯片封装结构。
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