CN201134426Y - 芯片封装结构 - Google Patents

芯片封装结构 Download PDF

Info

Publication number
CN201134426Y
CN201134426Y CNU2007201753494U CN200720175349U CN201134426Y CN 201134426 Y CN201134426 Y CN 201134426Y CN U2007201753494 U CNU2007201753494 U CN U2007201753494U CN 200720175349 U CN200720175349 U CN 200720175349U CN 201134426 Y CN201134426 Y CN 201134426Y
Authority
CN
China
Prior art keywords
chip
layer
plastic packaging
cementing layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNU2007201753494U
Other languages
English (en)
Inventor
周健威
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
Original Assignee
Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Semiconductor China R&D Co Ltd, Samsung Electronics Co Ltd filed Critical Samsung Semiconductor China R&D Co Ltd
Priority to CNU2007201753494U priority Critical patent/CN201134426Y/zh
Application granted granted Critical
Publication of CN201134426Y publication Critical patent/CN201134426Y/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

本实用新型公开了一种包括保护胶合层的芯片封装结构，该保护胶合层在芯片的上表面与塑封层之间形成隔离层，从而能够防止水气扩散并能有效释放由塑封层和芯片的热膨胀系数失配造成的内应力。该芯片封装结构包括：基板；芯片，设置在基板上；塑封层，形成在基板上并包封芯片；保护胶合层，形成在芯片的上表面与塑封层之间。

Description

芯片封装结构
技术领域
本实用新型涉及一种芯片封装结构，更具体地讲，涉及一种在芯片表面设置保护胶合层的芯片封装结构。
背景技术
集成电路的制造主要分为三个阶段：硅芯片的制造、集成电路的制作以及集成电路的封装。集成电路的封装是完成集成电路成品的最后步骤，封装的目的在于实现芯片与基板(通常为印刷电路板)或基板上的其它适当元件的电连接，以及更好地保护芯片。
图1是示意性地示出传统的球栅阵列(Ball Grid Array，BGA)封装或芯片尺寸封装(Chip Scale Package，CSP)的结构的剖视图。参照图1，芯片封装结构100包括基板110、芯片120、导线130、塑封层140、焊球150、底胶160和通孔170。在对芯片120进行封装的工艺中，首先用底胶160将芯片固定在基板110上，然后利用导线130使芯片120上的引出端通过通孔170电连接到焊球150，从而实现芯片120与基板110的电连接。随后，利用塑封层140将芯片120和导线130包封起来，以保护芯片120和导线130。
图2是示意性地示出传统的引线框架(Lead Frame)封装结构200的剖视图，图2中与图1中相同的标号表示相同的元件。参照图2，通过在引线框架280的内引脚和芯片120上的引出端之间焊接导线130来实现两者的电连接，这扩大了芯片120的输入输出接口，使得电信号可以通过引线框架280的外引脚到达芯片120，从而方便地实现了芯片120与基板上的其它芯片的电连接。
图3是示意性地示出传统的多芯片封装(MCP)结构300的剖视图，图3中与图1中相同的标号表示相同的元件。参照图3，多个芯片120堆叠在基板110上，每个芯片120上的引出端通过导线130电连接到基板110，从而实现芯片120和基板110或基板110上的其它芯片的电连接。在图1、图2和图3示出的封装结构中，底胶160可将芯片120固定住，从而避免芯片120在打线时滑动，另外底胶160还可以适当地缓冲由于各个元件之间的热膨胀系数失配(CTE Mismatch)引起的内应力。塑封层140可以对芯片120和导线130提供支撑保护，防止导线130在外应力下变形。
目前无论对于单芯片封装还是多芯片堆叠封装，由塑封层的吸水性而造成的芯片表面导线腐蚀(Wire Corrosion)、焊盘腐蚀(Pad Corrosion)，以及由于上层芯片和塑封层热膨胀系数失配引起的芯片表面与塑封层界面的开裂分层(Delamination)，进而造成开路(Open)都是常见的封装失效模式。
实用新型内容
本实用新型的一方面提供了一种包括保护胶合层的芯片封装结构，该保护胶合层在芯片的上表面与塑封层之间形成隔离层，从而能够防止水气扩散并能有效释放由塑封层和芯片的热膨胀系数失配造成的内应力。
根据本实用新型的一方面，一种芯片封装结构包括：基板；芯片，设置在所述基板上；塑封层，形成在所述基板上并包封所述芯片；保护胶合层，形成在所述芯片的上表面与所述塑封层之间。
优选地，所述保护胶合层在所述芯片的上表面与所述塑封层之间形成为隔离层。
优选地，所述保护胶合层的热膨胀系数介于所述芯片的热膨胀系数与所述塑封层的热膨胀系数之间。
优选地，所述保护胶合层不具有吸水性。
优选地，所述保护胶合层覆盖所述芯片的焊盘。
优选地，所述保护胶合层包括至少一种有机物和至少一种无机物，所述至少一种有机物包括树脂。
本实用新型另外的方面和/或优点将在随后的描述中阐明，从描述中将变得明显，或者可通过实践本实用新型而获知。
附图说明
通过参照附图详细描述本实用新型的示例性实施例，本实用新型的以上和其它特征及方面将变得更加清楚，在附图中：
图1是示意性地示出传统的BGA或CSP的结构的剖视图；
图2是示意性地示出传统的引线框架(Lead Frame)封装结构的剖视图；
图3是示意性地示出传统的多芯片封装(MCP)结构的剖视图；
图4是示出根据本实用新型的BGA封装结构的剖视图；
图5至图9是示出根据本实用新型的BGA封装结构的制造方法的顺序步骤的示意图。
具体实施方式
在下文中，将参照附图更加充分地描述本实用新型，本实用新型的优选实施例示出在附图中。本领域技术人员将意识到，在不脱离本实用新型的精神或范围的情况下，可以以各种不同的方式修改描述的实施例。
在附图中，为了清楚起见，夸大了层、膜、面板、区域等的厚度。在整个说明书中，相同的标号指代相同的元件。应该理解，当元件例如层、膜、区域或基底被称作在另一元件“上”时，该元件可以直接在该另一元件上，或者也可以存在中间元件。相反，当元件被称作“直接”在另一元件“上”时，不存在中间元件。
图4是示出根据本实用新型的BGA封装结构的剖视图。参照图4，根据本实施例的BGA封装结构400包括基板410、芯片420、塑封层440和胶合层480。芯片420设置在基板410上，用于固定芯片420的贴片胶460设置在芯片420和基板410之间，从而避免芯片420在打线时滑动。另外，贴片胶460还可以适当地缓冲由于各个元件之间的热膨胀系数失配引起的内应力。导线430将芯片420的引出端(未示出)通过通孔(未示出)电连接到焊球450，从而实现芯片420和基板410或基板410上的其它芯片的电连接。
胶合层480形成在芯片420的上表面上，塑封层440形成在基板410上，从而包封基板410、芯片420和导线430。这里，塑封层440可以由环氧塑封料(EMC)或者其它类型的塑封料形成。胶合层480可包括至少一种有机物(包括树脂)和至少一种无机物，在一个实施例中，胶合层480可包括重量百分比为40％～70％的二氧化硅填充物(Silica Filler)、重量百分比为20％～40％的丙烯酸树脂以及其它合适的材料。胶合层480的厚度范围可以为20μm～100μm。
胶合层480不具有吸水性，因此在芯片420的上表面和塑封层440之间形成一层隔离层，从而能够有效地防止来自外部的水气或塑封层440中的水气渗透到芯片420。此外，胶合层480的热膨胀系数(CTE)可介于芯片420的热膨胀系数和塑封层440的热膨胀系数之间，从而能够减小或缓解由于热膨胀而导致的芯片420与塑封层440之间的内应力。同时，胶合层480可具有较高的弹性模量，从而能够释放由塑封层440和芯片420的热膨胀系数失配造成的内应力。
图5至图9是示出图4中的BGA封装结构的制造方法的顺序步骤的示意图。
首先，参照图5，提供传统的已经完成导线连接(Wire Bonding)但未进行封模(Molding)的BGA。
随后，参照图6，利用普通点胶机在芯片420表面涂敷类似“＞-＜”形状的液态或者粘流态的胶合剂481。其中，胶合剂481对芯片420表面的钝化层呈润湿性(Wetting)，从而有利于胶合剂481在随后的压敷工艺中在芯片420的上表面上形成均匀的厚度。
然后，参照图7，对胶合剂481执行压敷工艺。具体地讲，压敷头1先向下移动，接触胶合剂481的表面，把胶合剂481往下挤压，使胶合剂481平铺在芯片420的整个表面且覆盖住芯片420边缘的焊盘(Bond Pad)，然后压敷头1向上移动，脱离胶合剂481。其中，压敷头1表面涂有一层胶合剂481在其上面不润湿(Dewetting)的材料，从而确保压敷头1能够容易地脱离胶合剂481。完成压敷工艺之后，得到如图8所示的器件。在图8中，胶合剂481已经平铺在芯片420的整个表面上。
然后，如图9所示，对胶合剂481执行固化工艺。具体地讲，将经历压敷工艺后的BGA放置在烘箱2中，使胶合剂481在125℃～175℃高温中固化5分钟～15分钟，从而形成固态、玻璃态或者高弹态的胶合层480。胶合剂481在固化后不具有吸水性，弹性优良，且热膨胀系数介于芯片的热膨胀系数与塑封层的热膨胀系数之间。
随后，可采用传统的方法对经历固化工艺后的BGA执行封模工艺和其它后续的封装工艺，以完成整个封装流程，从而获得如图4所示的BGA封装结构400。
虽然以BGA封装结构为示例描述了根据本实用新型实施例的胶合层的应用，但是如本领域技术人员将理解的，图4中示出的根据本实施例的BGA封装结构中的胶合层可容易地应用到CSP、引线框架封装和MCP中。在所述胶合层应用到MCP的情况下，胶合层设置在MCP的顶层芯片的上表面与塑封层之间，从而在MCP的顶层芯片的上表面与塑封层之间形成隔离层。
虽然已经结合当前被认为是实践性的示例性实施例的内容描述了本实用新型，但是应该理解，本实用新型不限于公开的实施例，相反，本实用新型意在覆盖包括在权利要求的精神和范围内的各种修改和等同布置。

Claims (6)

1、一种芯片封装结构，包括基板、设置在所述基板上的芯片以及形成在所述基板上并包封所述芯片的塑封层，其特征是，所述芯片封装结构还包括形成在所述芯片的上表面与所述塑封层之间的保护胶合层。
2、如权利要求1所述的芯片封装结构，其特征是，所述保护胶合层在所述芯片的上表面与所述塑封层之间形成为隔离层。
3、如权利要求1所述的芯片封装结构，其特征是，所述保护胶合层的热膨胀系数介于所述芯片的热膨胀系数与所述塑封层的热膨胀系数之间。
4、如权利要求1所述的芯片封装结构，其特征是，所述保护胶合层不具有吸水性。
5、如权利要求1所述的芯片封装结构，其特征是，所述保护胶合层覆盖所述芯片的焊盘。
6、如权利要求1所述的芯片封装结构，其特征是，所述保护胶合层包括至少一种有机物和至少一种无机物，所述至少一种有机物包括树脂。
CNU2007201753494U 2007-09-05 2007-09-05 芯片封装结构 Expired - Fee Related CN201134426Y (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNU2007201753494U CN201134426Y (zh) 2007-09-05 2007-09-05 芯片封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNU2007201753494U CN201134426Y (zh) 2007-09-05 2007-09-05 芯片封装结构

Publications (1)

Publication Number Publication Date
CN201134426Y true CN201134426Y (zh) 2008-10-15

Family

ID=40062694

Family Applications (1)

Application Number Title Priority Date Filing Date
CNU2007201753494U Expired - Fee Related CN201134426Y (zh) 2007-09-05 2007-09-05 芯片封装结构

Country Status (1)

Country Link
CN (1) CN201134426Y (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097722A (zh) * 2014-05-05 2015-11-25 清华大学 半导体封装结构和封装方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097722A (zh) * 2014-05-05 2015-11-25 清华大学 半导体封装结构和封装方法
CN105097722B (zh) * 2014-05-05 2019-12-13 清华大学 半导体封装结构和封装方法

Similar Documents

Publication Publication Date Title
US20230378153A1 (en) Package-on-Package Structure Including a Thermal Isolation Material
CN208014673U (zh) 芯片封装结构
CN101409266B (zh) 封装结构
CN102569214B (zh) 三维系统级封装堆栈式封装结构
US6177723B1 (en) Integrated circuit package and flat plate molding process for integrated circuit package
TWI239655B (en) Photosensitive semiconductor package with support member and method for fabricating the same
US8815645B2 (en) Multi-chip stacking method to reduce voids between stacked chips
KR101398404B1 (ko) 기계적으로 분리된 리드 부착물을 갖는 플라스틱오버몰딩된 패키지들
CN101171683B (zh) 多芯片模块及制造方法
CN103022021A (zh) 半导体装置及其制造方法
US8093104B1 (en) Multi-chip stacking method to reduce voids between stacked chips
US20070080435A1 (en) Semiconductor packaging process and carrier for semiconductor package
CN101256997A (zh) 可降低封装应力的封装构造
US20140183711A1 (en) Semiconductor Device and Method of Making a Semiconductor Device
CN105609490B (zh) 一种复合传感器模块的封装结构及其制造方法
US20080009096A1 (en) Package-on-package and method of fabricating the same
US7122407B2 (en) Method for fabricating window ball grid array semiconductor package
CN205508874U (zh) 一种柔性led电路板封装模组
CN201134426Y (zh) 芯片封装结构
CN106684003B (zh) 扇出型封装结构及其制作方法
US6710434B1 (en) Window-type semiconductor package and fabrication method thereof
KR100564623B1 (ko) 크랙을 예방하는 반도체 패키지 및 그 제조방법
JP2005142452A (ja) 半導体装置及びその製造方法
TWI241003B (en) Method and device for cavity-down package
TW518732B (en) A semiconductor packaging process for ball grid array (BGA)

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20081015

Termination date: 20160905