WO2019179195A1 - 一种贴片压敏电阻及其制作方法 - Google Patents

一种贴片压敏电阻及其制作方法 Download PDF

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Publication number
WO2019179195A1
WO2019179195A1 PCT/CN2018/124226 CN2018124226W WO2019179195A1 WO 2019179195 A1 WO2019179195 A1 WO 2019179195A1 CN 2018124226 W CN2018124226 W CN 2018124226W WO 2019179195 A1 WO2019179195 A1 WO 2019179195A1
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electrode
varistor
chip
soldering
silver film
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PCT/CN2018/124226
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English (en)
French (fr)
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叶金洪
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东莞市有辰电子有限公司
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Publication of WO2019179195A1 publication Critical patent/WO2019179195A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/02—Housing; Enclosing; Embedding; Filling the housing or enclosure
    • H01C1/024—Housing; Enclosing; Embedding; Filling the housing or enclosure the housing or enclosure being hermetically sealed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/105—Varistor cores
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/02—Housing; Enclosing; Embedding; Filling the housing or enclosure
    • H01C1/028—Housing; Enclosing; Embedding; Filling the housing or enclosure the resistive element being embedded in insulation with outer enclosing sheath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/144—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being welded or soldered
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/102—Varistor boundary, e.g. surface layers

Definitions

  • the invention relates to the technical field of electrical resistance, in particular to a chip varistor and a manufacturing method thereof.
  • a varistor is a very sensitive voltage component that is a non-linear resistor that is used as a voltage surge protection device in the circuit.
  • the magnitude of the protection force is usually determined by the flow rate of the varistor, and the magnitude of the flow rate depends on the surface area of the varistor electrode, so that the varistor with a large flow rate has a large outer shape.
  • the traditional process has made the varistor into the in-line mode to reduce the space occupied by the varistor on the circuit board, so that the varistor can only be mounted on the circuit board by the in-line process. .
  • the current application of varistor companies is gradually shifting to a highly efficient surface mount process, and the varistor of the in-line type cannot meet the production needs of these enterprises.
  • the present invention provides a chip varistor and a manufacturing method thereof, which can produce a chip-type varistor, and make up for the application defects of the varistor in the patch process, thereby improving Production efficiency, cost reduction, and effective solutions to the problems raised by the background art.
  • a chip varistor comprising a varistor chip, a lower electrode, an upper electrode and a potting body, wherein the potting body encapsulates the varistor chip, the lower electrode and the upper electrode by an epoxy resin to form an integrated structure;
  • the upper surface and the lower surface of the varistor chip are respectively provided with an upper silver film and a lower silver film, and the lower electrode and the upper electrode are respectively formed into a "Z" shape by a mechanical mold, and the lower electrode includes a lower connecting surface, a lower inclined surface and a lower welding surface, the upper electrode includes an upper connecting surface, an upper inclined surface and an upper welding surface, and the lower electrode and the upper electrode are respectively disposed at an end portion and a bottom of the varistor chip, the upper silver film and the upper surface
  • the connecting surface is fixedly connected by soldering, and the lower silver film and the lower connecting surface are also fixedly connected by soldering, and the upper soldering surface and the lower soldering surface are located on the same plane, and the upper soldering surface and the lower soldering surface are passed through the potting body After packaging, the cross section is not less than 2mm 2 .
  • the lower electrode and the upper electrode are both made of a tin-plated metal sheet, and the thickness of the lower electrode and the upper electrode are both 0.15-0.30 mm and the width is 2 mm-4 mm.
  • an angle between the upper inclined surface of the upper electrode and the upper welding surface is 90°-105°
  • an angle between the lower inclined surface of the lower electrode and the lower welding surface is 90°-160°.
  • the angle between the side surface of the potting body and the bottom surface of the upper welding surface and the lower welding surface is 90°-95°.
  • the present invention also provides a method for fabricating a chip varistor, comprising the following steps:
  • Step 100 The tin-plated metal piece is made into a "Z"-shaped upper electrode and a lower electrode having a thickness of 0.15-0.3 mm and a width of 2-4 mm through a mechanical mold;
  • Step 200 soldering the upper connecting surface of the upper silver film and the upper electrode of the varistor chip by soldering, and connecting the lower connecting surface of the lower silver film and the lower electrode of the varistor chip by soldering;
  • Step 300 by potting, the epoxy resin seals the varistor chip connecting the upper electrode and the lower electrode to expose only the lower soldering surface of the lower electrode and the upper soldering surface of the upper electrode.
  • the "Z"-shaped structure of the upper electrode includes an upper connecting surface, an upper inclined surface and an upper welding surface, and an angle between the upper inclined surface and the upper welding surface
  • the lower electrode includes a lower joint surface, a lower slope surface, and a lower weld surface, and the angle between the lower slope surface and the lower weld surface is 90°-160°.
  • step 300 the angle between the side of the potting body and the bottom surface of the upper welding surface and the lower welding surface is 90°-95°.
  • the invention has the beneficial effects that the invention can be well adapted to the current high-speed surface mounting process, improve production efficiency, reduce cost, and has good sealing performance and insulating performance of epoxy resin.
  • the safety performance of the fabricated component is safer and more reliable, and the material used for the present invention has a low price of tin-plated metal sheet electrodes and epoxy resin, thereby making the overall manufacturing cost lower.
  • Figure 1 is a schematic view of the overall structure of the present invention
  • Figure 2 is a schematic bottom view of the present invention
  • Figure 3 is a schematic top plan view of the present invention.
  • Figure 4 is a schematic flow chart of the present invention.
  • the present invention provides a chip varistor comprising a varistor chip 1, a lower electrode 4, an upper electrode 5 and a potting body 6, and the potting body 6 is passed through an epoxy.
  • the resin encapsulates the varistor chip 1, the lower electrode 4, and the upper electrode 5 to form an integrated structure.
  • the shape of the varistor chip 1 is a cylindrical shape or a rectangular parallelepiped shape.
  • the upper surface and the lower surface of the varistor chip 1 are respectively provided with an upper silver film 2 and a lower silver film 3, and the lower electrode 4 and the upper electrode 5 are respectively formed into a "Z" shape by a mechanical mold, and the lower electrode 4 includes a lower connecting surface 41, a lower inclined surface 42 and a lower welding surface 43, the upper electrode 5 including an upper connecting surface 51, an upper inclined surface 52 and an upper welding surface 53, and the lower electrode 4 and the upper electrode 5 are respectively provided in pressure sensitive An end portion and a bottom portion of the resistor chip 1, the upper silver film 2 and the upper connection surface 51 are fixedly connected by soldering, and the lower silver film 3 and the lower connection surface 41 are also fixedly connected by soldering, and the upper soldering surface 53 and The lower welding faces 43 are located on the same plane, and the upper welding face 53 and the lower welding face 43 are not less than 2 mm 2 in cross section after being encapsulated by the potting body 6.
  • the lower electrode 4 and the upper electrode 5 are both made of tin-plated metal sheets, and the thickness of the lower electrode 4 and the upper electrode 5 are both 0.15-0.30 mm, and the width is 2 mm-4 mm; the upper electrode 5
  • the angle between the upper inclined surface 52 and the upper welding surface 53 is 90°-105°, and the angle between the lower inclined surface 42 of the lower electrode 4 and the lower welding surface 43 is 90°-160°;
  • the angle between the side of the body 6 and the bottom surface of the upper welding surface 53 and the lower welding surface 43 is 90°-95°.
  • the present invention also provides a method for fabricating a chip varistor, comprising the following steps:
  • Step 100 The tin-plated metal piece is made into a "Z"-shaped upper electrode and a lower electrode having a thickness of 0.15-0.3 mm and a width of 2-4 mm through a mechanical mold;
  • Step 200 soldering the upper connecting surface of the upper silver film and the upper electrode of the varistor chip by soldering, and connecting the lower connecting surface of the lower silver film and the lower electrode of the varistor chip by soldering;
  • Step 300 by potting, the epoxy resin seals the varistor chip connecting the upper electrode and the lower electrode to expose only the lower soldering surface of the lower electrode and the upper soldering surface of the upper electrode.
  • the "Z"-shaped structure of the upper electrode comprises an upper connecting surface, an upper inclined surface and an upper welding surface, and an angle between the upper inclined surface and the upper welding surface is 90°-105°
  • the lower electrode includes a lower connecting surface, a lower inclined surface and a lower welding surface, and an angle between the lower inclined surface and the lower welded surface is 90°-160°.
  • step 300 the angle between the side of the potting body and the bottom surface of the upper welding surface and the lower welding surface is 90°-95°.
  • the soldering process may also use a conductive adhesive bonding method to connect the upper silver film of the varistor chip and the upper connecting surface of the upper electrode, and The lower connection faces of the silver film and the lower electrode are connected.
  • the epoxy potting process may also be replaced with an epoxy molding process.
  • the chip varistor produced by the invention can be well adapted to the current high-speed surface mount process, improve production efficiency, reduce cost, and has good sealing performance and insulation performance.
  • the safety performance of the fabricated component is made safer and more reliable, and the material of the tin-plated metal sheet electrode and the epoxy resin used in the invention is low in price, so that the overall manufacturing cost is low.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Thermistors And Varistors (AREA)

Abstract

本发明公开了一种贴片压敏电阻及其制作方法，一种贴片压敏电阻，包括压敏电阻芯片、下电极、上电极和灌封体，所述灌封体通过环氧树脂将压敏电阻芯片、下电极和上电极封装形成一体化结构；在压敏电阻芯片上表面和下表面分别设有上银膜和下银膜，所述下电极包括下连接面、下斜面和下焊接面，所述上电极包括上连接面、上斜面和上焊接面，所述上银膜和上连接面以及下银膜和下连接面之间均固定连接；首先将镀锡金属片通过机械模具制成"Z"字型的上电极和下电极；其次，通过锡焊将压敏电阻芯片和上电极以及下电极连接起来；最后，通过灌封密封起来；可以生产出贴片式的压敏电阻，弥补压敏电阻在贴片工艺上的应用缺陷，从而提高生产效率，降低成本。

Description

一种贴片压敏电阻及其制作方法 技术领域
本发明涉及电阻技术领域，具体为一种贴片压敏电阻及其制作方法。
背景技术
压敏电阻是一种电压非常敏感的电阻元件,属于非线性电阻，在电路中被用作电压浪涌保护装置。保护力度的大小通常由压敏电阻的通流量来决定，而通流量的大小取决于压敏电阻电极的表面积，致使通流量大的压敏电阻其外形也大。多年以来，传统工艺的做法均把压敏电阻做成直插方式来减少压敏电阻焊接时在线路板上占用的空间，这样就使得压敏电阻只能用直插工艺来安装在线路板上。但是，目前应用压敏电阻的企业其作业方式正逐步转向高效率的表面贴装工艺，直插方式的压敏电阻已经不能满足这些企业的生产需求。
目前市场上通流量较大的压敏电阻大部分是直插方式，而不是贴片方式，不能适应现在的高速表面贴装工艺，特别是面对铝基线路板应用时，由于铝基线路没有过孔焊盘，必需人工焊接，造成人工成本增加，效率低，严重影响企业的生产速度。
发明内容
为了克服现有技术方案的不足，本发明提供一种贴片压敏电阻及其制作方法，可以生产出贴片式的压敏电阻，弥补压敏电阻在贴片工艺上的应用缺陷，从而提高生产效率，降低成本，能有效的解决背景技术提出的问题。
本发明解决其技术问题所采用的技术方案是：
一种贴片压敏电阻，包括压敏电阻芯片、下电极、上电极和灌封体，所述灌封体通过环氧树脂将压敏电阻芯片、下电极和上电极封装形成一体化结 构；
所述压敏电阻芯片上表面和下表面分别设有上银膜和下银膜，所述下电极和上电极均通过机械模具制成“Z”字型，所述下电极包括下连接面、下斜面和下焊接面，所述上电极包括上连接面、上斜面和上焊接面，所述下电极和上电极分别设在压敏电阻芯片的端部和底部，所述上银膜和上连接面通过锡焊固定连接，所述下银膜和下连接面也通过锡焊固定连接，且上焊接面和下焊接面位于同一个平面上，且上焊接面和下焊接面通过灌封体的封装后其截面不小于2mm 2。
作为本发明一种优选的技术方案，所述下电极和上电极均由镀锡金属片制成，且下电极和上电极的厚度均为0.15-0.30mm，宽度均为2mm-4mm。
作为本发明一种优选的技术方案，所述上电极的上斜面和上焊接面之间的夹角为90°-105°，所述下电极的下斜面和下焊接面之间的夹角为90°-160°。
作为本发明一种优选的技术方案，所述灌封体的侧面与上焊接面和下焊接面所在底面之间的夹角为90°-95°。
另外，本发明还提供了一种贴片压敏电阻的制作方法，包括如下步骤：
步骤100、将镀锡金属片通过机械模具制成厚度均为0.15-0.3mm、宽度为2-4mm的“Z”字型的上电极和下电极；
步骤200、通过锡焊将压敏电阻芯片的上银膜和上电极的上连接面焊接起来，并将压敏电阻芯片的下银膜和下电极的下连接面也通过锡焊连接起来；
步骤300、通过灌封使得环氧树脂把连接好上电极和下电极的压敏电阻芯片密封起来，使其只露出下电极的下焊接面和上电极的上焊接面。
作为本发明一种优选的技术方案，在步骤100中，所述上电极的“Z”字型结构包括上连接面、上斜面和上焊接面，且上斜面和上焊接面之间的夹角为90°-105°，所述下电极包括下连接面、下斜面和下焊接面，且下斜面和 下焊接面之间的夹角为90°-160°。
作为本发明一种优选的技术方案，在步骤300中，所述灌封体的侧面与上焊接面和下焊接面所在底面之间的夹角为90°-95°。
与现有技术相比，本发明的有益效果是：本发明能很好的适应当前的高速表面贴装工艺，提高生产效率，降低成本，而且由于环氧树脂密封性能和绝缘性能都好，使制成的元件的安全性能更安全可靠，同时本发明所用材料镀锡金属片电极和环氧树脂的价格低，从而使整体制作成本较低。
附图说明
图1为本发明的整体结构示意图；
图2为本发明的仰视结构示意图；
图3为本发明的俯视结构示意图；
图4为本发明的流程示意图；
图中标号：1-压敏电阻芯片；2-上银膜；3-下银膜；4-下电极；5-上电极；6-灌封体；
41-下连接面；42-下斜面；43-下焊接面；
51-上连接面；52-上斜面；53-上焊接面。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
如图1至图4所示，本发明提供了一种贴片压敏电阻，包括压敏电阻芯片1、下电极4、上电极5和灌封体6，所述灌封体6通过环氧树脂将压敏电 阻芯片1、下电极4和上电极5封装形成一体化结构。
其中压敏电阻芯片1的形状为圆柱状或长方体。
所述压敏电阻芯片1上表面和下表面分别设有上银膜2和下银膜3，所述下电极4和上电极5均通过机械模具制成“Z”字型，所述下电极4包括下连接面41、下斜面42和下焊接面43，所述上电极5包括上连接面51、上斜面52和上焊接面53，所述下电极4和上电极5分别设在压敏电阻芯片1的端部和底部，所述上银膜2和上连接面51通过锡焊固定连接，所述下银膜3和下连接面41也通过锡焊固定连接，且上焊接面53和下焊接面43位于同一个平面上，且上焊接面53和下焊接面43通过灌封体6的封装后其截面不小于2mm 2。
其中，所述下电极4和上电极5均由镀锡金属片制成，且下电极4和上电极5的厚度均为0.15-0.30mm，宽度均为2mm-4mm；所述上电极5的上斜面52和上焊接面53之间的夹角为90°-105°，所述下电极4的下斜面42和下焊接面43之间的夹角为90°-160°；所述灌封体6的侧面与上焊接面53和下焊接面43所在底面之间的夹角为90°-95°。
另外，本发明还提供了一种贴片压敏电阻的制作方法，包括如下步骤：
步骤100、将镀锡金属片通过机械模具制成厚度均为0.15-0.3mm、宽度为2-4mm的“Z”字型的上电极和下电极；
步骤200、通过锡焊将压敏电阻芯片的上银膜和上电极的上连接面焊接起来，并将压敏电阻芯片的下银膜和下电极的下连接面也通过锡焊连接起来；
步骤300、通过灌封使得环氧树脂把连接好上电极和下电极的压敏电阻芯片密封起来，使其只露出下电极的下焊接面和上电极的上焊接面。
根据上述，在步骤100中，所述上电极的“Z”字型结构包括上连接面、上斜面和上焊接面，且上斜面和上焊接面之间的夹角为90°-105°，所述下电极包括下连接面、下斜面和下焊接面，且下斜面和下焊接面之间的夹角为 90°-160°。
另外，在步骤300中，所述灌封体的侧面与上焊接面和下焊接面所在底面之间的夹角为90°-95°。
在本实施方式中，进一步优选的是，在上述步骤200中，锡焊工艺也可以使用导电胶粘接的方式把压敏电阻芯片的上银膜和上电极的上连接面连接起来，将下银膜和下电极的下连接面连接起来。另外，在步骤300中，环氧树脂灌封工艺也可以使用环氧树脂模压工艺来代替。
而且，根据上述内容可知，在现有技术中的热敏电阻芯片以及瓷片电容芯片等也是可以通过本发明来制作出具有贴片功能的元件。
综上所述，通过本发明制作出的贴片压敏电阻，能很好的适应当前的高速表面贴装工艺，提高生产效率，降低成本，而且由于环氧树脂密封性能和绝缘性能都好，使制成的元件的安全性能更安全可靠，同时本发明所用材料镀锡金属片电极和环氧树脂的价格低，从而使整体制作成本较低。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。

Claims (7)

  1. 一种贴片压敏电阻，其特征在于，包括压敏电阻芯片(1)、下电极(4)、上电极(5)和灌封体(6)，所述灌封体(6)通过环氧树脂将压敏电阻芯片(1)、下电极(4)和上电极(5)封装形成一体化结构；
    所述压敏电阻芯片(1)上表面和下表面分别设有上银膜(2)和下银膜(3)，所述下电极(4)和上电极(5)均通过机械模具制成“Z”字型，所述下电极(4)包括下连接面(41)、下斜面(42)和下焊接面(43)，所述上电极(5)包括上连接面(51)、上斜面(52)和上焊接面(53)，所述下电极(4)和上电极(5)分别设在压敏电阻芯片(1)的端部和底部，所述上银膜(2)和上连接面(51)通过锡焊固定连接，所述下银膜(3)和下连接面(41)也通过锡焊固定连接，且上焊接面(53)和下焊接面(43)位于同一个平面上，且上焊接面(53)和下焊接面(43)通过灌封体(6)的封装后其截面不小于2mm 2。
  2. 根据权利要求1所述的一种贴片压敏电阻，其特征在于，所述下电极(4)和上电极(5)均由镀锡金属片制成，且下电极(4)和上电极(5)的厚度均为0.15-0.30mm，宽度均为2mm-4mm。
  3. 根据权利要求1所述的一种贴片压敏电阻，其特征在于，所述上电极(5)的上斜面(52)和上焊接面(53)之间的夹角为90°-105°，所述下电极(4)的下斜面(42)和下焊接面(43)之间的夹角为90°-160°。
  4. 根据权利要求1所述的一种贴片压敏电阻，其特征在于，所述灌封体(6)的侧面与上焊接面(53)和下焊接面(43)所在底面之间的夹角为90°-95°。
  5. 一种贴片压敏电阻的制作方法，其特征在于，包括如下步骤：
    步骤100、将镀锡金属片通过机械模具制成厚度均为0.15-0.3mm、宽度 为2-4mm的“Z”字型的上电极和下电极；
    步骤200、通过锡焊将压敏电阻芯片的上银膜和上电极的上连接面焊接起来，并将压敏电阻芯片的下银膜和下电极的下连接面也通过锡焊连接起来；
    步骤300、通过灌封使得环氧树脂把连接好上电极和下电极的压敏电阻芯片密封起来，使其只露出下电极的下焊接面和上电极的上焊接面。
  6. 根据权利要求5所述的一种贴片压敏电阻的制作方法，其特征在于，在步骤100中，所述上电极的“Z”字型结构包括上连接面、上斜面和上焊接面，且上斜面和上焊接面之间的夹角为90°-105°，所述下电极包括下连接面、下斜面和下焊接面，且下斜面和下焊接面之间的夹角为90°-160°。
  7. 根据权利要求5所述的一种贴片压敏电阻的制作方法，其特征在于，在步骤300中，所述灌封体的侧面与上焊接面和下焊接面所在底面之间的夹角为90°-95°。
PCT/CN2018/124226 2018-03-21 2018-12-27 一种贴片压敏电阻及其制作方法 WO2019179195A1 (zh)

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