CN1154179C - 具薄膜基板的晶片封装组件 - Google Patents

具薄膜基板的晶片封装组件 Download PDF

Info

Publication number
CN1154179C
CN1154179C CNB01104232XA CN01104232A CN1154179C CN 1154179 C CN1154179 C CN 1154179C CN B01104232X A CNB01104232X A CN B01104232XA CN 01104232 A CN01104232 A CN 01104232A CN 1154179 C CN1154179 C CN 1154179C
Authority
CN
China
Prior art keywords
wafer
substrate
package assembling
film substrate
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB01104232XA
Other languages
English (en)
Other versions
CN1372314A (zh
Inventor
谢文乐
庄永成
黄宁
陈慧萍
蒋华文
张衷铭
涂丰昌
黄富裕
张轩睿
胡嘉杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HUATAI ELECTRONICS CO Ltd
Original Assignee
HUATAI ELECTRONICS CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HUATAI ELECTRONICS CO Ltd filed Critical HUATAI ELECTRONICS CO Ltd
Priority to CNB01104232XA priority Critical patent/CN1154179C/zh
Publication of CN1372314A publication Critical patent/CN1372314A/zh
Application granted granted Critical
Publication of CN1154179C publication Critical patent/CN1154179C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种具薄膜基板的晶片封装组件。为提供一种可有效地降低封装后整体厚度、黏合效果好、黏合作业效率高的半导体封装组件，提出本发明，它包括刻设加工的基板、黏胶于基板上的晶片及与晶片电气连接的导电件；基板为薄膜基板，其上设有与晶片接合的凹入状输入/输出脚位；导电件为位于基板凹入状输入/输出脚位下方处呈凸出状并与晶片电气连接的金属垫。

Description

具薄膜基板的晶片封装组件
本发明属于半导体封装组件，特别是一种具薄膜基板的晶片封装组件。
半导体经多年来的发展，其制作技术不断创新，新一代的封装制程(Package)以轻、薄、短、小为目标来发展。为达到前述功能不仅须不断提高半导体的积集度，以缩小晶片尺寸的大小，并须配合搭载晶片的载具得以具备高密度脚距及超薄的特性，方能实现真正轻、薄、短、小的封装模组。
习知的应用于微型薄膜封装技术，主要为MLP(Micro Leadframe Package)技术。如图1所示，其系在引线框架(Leadframe)12’底部贴上耐热胶带11’，在引线框架12’上黏着晶片(Die)13’，并以金属导线14’接合(Wire Bonding)的方式将导线14’与引线框架12’的结合键作电气接合，其承载晶片的结构系使用引线框架12’。由于引线框架12’系于铁、镍合金或铜合金的薄板上利用化学药品蚀刻(Etching)，将不要的部份削除而制成，其引线框架12’本身的厚度、每根由引线框架12’切割后形成的结合键的最小宽度及结合键与结合键之间的间隙皆有所限制，无法作得极薄，若再加上层叠在引线框架12’上的晶片13’厚度及其作电气接合的导线14’的高度，又加上最后保护诸元件的封装材料(树脂Molding Compound)16’的厚度，势必无法有效降低整体封装模组的厚度，如此一来，就算该晶片能发展到极小极薄，无法有效改变引线框架12’的重大缺点亦是枉然；如图2、图3所示，在灌入封装材料16’后切割成单一封装颗粒10’时，其底部为平面，这对该封装颗粒10’与印刷电路板(PCB)接合时，产生接合的困难性及与焊膏点的接着性。
本发明的目的是提供一种可有效地降低封装后整体厚度、黏合效果好、黏合作业效率高的具薄膜基板的晶片封装组件。
本发明包括刻设加工的基板、黏胶于基板上的晶片及与晶片电气连接的导电件；基板为薄膜基板，其上设有与晶片接合的凹入状输入/输出脚位；导电件为位于基板凹入状输入/输出脚位下方处呈凸出状并与晶片电气连接的金属垫。
其中：
基板为以高分子薄膜制作的薄膜基板，并以化学药物蚀刻/用激光加工的方式刻设加工；晶片系以阵列式黏胶于为高分子薄膜基板的基板上。
基板为以聚醯亚胺薄膜制作的薄膜基板，并以化学药物蚀刻或用激光加工的方式刻设加工；晶片系以阵列式黏胶于基板上。
晶片与为金属垫的导电件之间以引线键合方式形成的导线电气连接。
晶片与为金属垫的导电件之间以覆晶方式形成的输入/输出凸块电气连接。
基板相对于晶片位置的背面设有利于晶片散热的金属片。
由于本发明包括刻设加工的基板、黏胶于基板上的晶片及与晶片电气连接的导电件；基板为薄膜基板，其上设有与晶片接合的凹入状输入/输出脚位；导电件为位于基板凹入状输入/输出脚位下方处呈凸出状并与晶片电气连接的金属垫。藉由极薄的薄膜基板及设置于其上与晶片接合的凹入接合脚位，可有效降低本发明的厚度；藉由凸出于基板下方的为金属垫导电件，可方便于本发明切割后的单一封装颗粒与PCB板上的焊膏接点对位焊接，并可直接作业，具有较佳的焊接功能，并提高制程作业的时效。不仅可有效地降低封装后整体厚度，而且黏合效果好、黏合作业效率高，从而达到本发明的目的。
图1、为习用的微型薄膜封装晶片结构示意剖视图。
图2、为习用的微型薄膜封装的单一封装颗粒结构示意剖视图。
图3、为习用的微型薄膜封装晶片的引线框架底部示意图。
图4、为本发明结构示意剖视图(以引线键合电气连接)。
图5、为以本发明切割成单一封装颗粒与印刷电路板焊膏结合示意图(以引线键合电气连接)。
图6、为图5中A向视图。
图7、为本发明单一封装颗粒结构示意剖视图(以引线键合电气连接、基板背面设有散热用金属片)。
图8、为图7中B向视图。
图9、为本发明结构示意剖视图(以覆晶电气连接)。
图10、为本发明结构示意剖视图(以覆晶电气连接、基板背面设有散热用金属片)。
下面结合附图对本发明进一步详细阐述。
如图4、图5、图6所示，本发明系采用高分子薄膜或PI(聚醯亚胺)层11来制作晶片承载器(Carrier)或基板(Substrate)1，并将与晶片2接合的脚位12作成凹入状，使接合晶片2的导线21一端引线键合凹入的脚位12内，以争取降低高分子薄膜或PI晶片承载器或基板1与晶片2接合时的厚度。
本发明的超薄型薄膜封装系先将高分子薄膜或PI层层11作为高分子薄膜晶片承载器或基板或PI晶片承载器或基板1，以阵列式承载晶片2，并以化学药物蚀刻或用激光加工的方式加工基板1，可将PI晶片承载器或基板1制作得极而近乎薄膜状，并预先将输入/输出脚位12作成凹入状，将晶片2以黏胶3贴于高分子薄膜或PI晶片承载器或基板1上，而在电气连接部分则以引线键合的技术形成的导线21的一端黏于晶片2上，另一端则引线键合高分子薄膜或PI晶片承载器或基板1所预留的凹入脚位12内与凸设于基板1下方的为金属垫的导电件13上，续再灌入封装材料4来保护晶片2及导线21。最后再切割为含晶片2的单一封装颗粒5以形成封装单元。
如图7、图8所示，本发明高分子薄膜或PI晶片承载器或基板1相对于黏贴晶片2位置背保留金属片14，使其可有效增加晶片2的散热功效。
如图9所示，本发明高分子薄膜或PI晶片承载器或基板1a与晶片2a电气连接亦可采用先进的覆晶接合方式。其高分子薄膜或PI晶片承载器或基板1a亦预留与晶片2a接合的凹入的脚位12a，然后将晶片2a翻覆后，使晶片2a上的I/O凸块21a与高分子薄膜或PI晶片承载器或基板1a的脚位12a内与凸设于基板1a下方的为金属垫的导电件13a接合，并在晶片2a与高分子薄膜或PI晶片承载器或基板1a的接合间隙填胶3a以增加其接合反分散应力。
如图10所示，本发明高分子薄膜或PI晶片承载器或基板1a的相对于黏贴晶片2a位置背保留金属片14a，使其可有效增加晶片2a的散热功效。
由于本发明的晶片承载器或基板1系采用高分子薄膜或PI层11来制作，故该高分子薄膜或PI晶片承载器或基板1可加工至极薄的近薄膜状，并制作与晶片导线21接合的凹入接合脚位12，亦有助于降低导线接合后的高度；若采用覆晶接合技术，除更能缩减厚度外，亦同时能缩小封装面积，制作超涉及超薄的封装组件。
本发明切割为单一封装颗粒底侧的为电极或金属垫的导电件13(13a)系为凸出状，如此可方便于封装颗粒与PCB板上的焊膏6接点对位焊接时可直接作业，具有较佳的焊接功能，并提高制程作业的时效。

Claims (7)

1、一种具薄膜基板的晶片封装组件，它包括刻设加工的基板、黏胶于基板上的晶片及与晶片电气连接的导电件；其特征在于所述的基板为薄膜基板，其上设有与晶片接合的凹入状输入/输出脚位；导电件为位于基板凹入状输入/输出脚位下方处呈凸出状并与晶片电气连接的金属垫。
2、根据权利要求1所述的具薄膜基板的晶片封装组件，其特征在于所述的基板为以高分子薄膜制作的薄膜基板，并以化学药物蚀刻或用激光加工的方式刻设加工；晶片系以阵列式黏胶于为高分子薄膜基板的基板上。
3、根据权利要求1所述的具薄膜基板的晶片封装组件，其特征在于所述的基板为以聚醯亚胺薄膜制作的薄膜基板，并以化学药物蚀刻/用激光加工的方式刻设加工；晶片系以阵列式黏胶于基板上。
4、根据权利要求2或3所述的具薄膜基板的晶片封装组件，其特征在于所述的晶片与为金属垫的导电件之间以引线键合方式形成的导线电气连接。
5、根据权利要求2或3所述的具薄膜基板的晶片封装组件，其特征在于所述的晶片与为金属垫的导电件之间以覆晶方式形成的输入/输出凸块电气连接。
6、根据权利要求4所述的具薄膜基板的晶片封装组件，其特征在于所述的基板相对于晶片位置的背面设有利于晶片散热的金属片。
7、根据权利要求5所述的具薄膜基板的晶片封装组件，其特征在于所述的基板相对于晶片位置的背面设有利于晶片散热的金属片。
CNB01104232XA 2001-02-26 2001-02-26 具薄膜基板的晶片封装组件 Expired - Fee Related CN1154179C (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB01104232XA CN1154179C (zh) 2001-02-26 2001-02-26 具薄膜基板的晶片封装组件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB01104232XA CN1154179C (zh) 2001-02-26 2001-02-26 具薄膜基板的晶片封装组件

Publications (2)

Publication Number Publication Date
CN1372314A CN1372314A (zh) 2002-10-02
CN1154179C true CN1154179C (zh) 2004-06-16

Family

ID=4653775

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB01104232XA Expired - Fee Related CN1154179C (zh) 2001-02-26 2001-02-26 具薄膜基板的晶片封装组件

Country Status (1)

Country Link
CN (1) CN1154179C (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114132022B (zh) * 2021-11-02 2022-08-16 河海大学 一种针对硬脆性高模镁合金的楔形衬板及其控边裂轧制方法和应用

Also Published As

Publication number Publication date
CN1372314A (zh) 2002-10-02

Similar Documents

Publication Publication Date Title
KR100470897B1 (ko) 듀얼 다이 패키지 제조 방법
CN102789994B (zh) 侧面可浸润半导体器件
CN101499450B (zh) 半导体装置及其制造方法
EP2306513A2 (en) IC chip package with directly connected leads
KR20000005915A (ko) 반도체장치와그제조방법
CN203367260U (zh) 一种功率陶瓷外壳和功率芯片封装结构
JP5125975B2 (ja) 樹脂ケース製造方法
CN1129968C (zh) 发光二极管的封装方法
CN1387252A (zh) 具散热结构的半导体封装件
KR20010110154A (ko) 리드 프레임, 반도체 장치 및 그 제조 방법, 회로 기판 및 전자기기
CN1149766A (zh) 树脂密封型半导体器件
CN103165794B (zh) 光学半导体装置用基台、其制造方法以及光学半导体装置
CN1254858C (zh) 具有集成电路的电子芯片组件及其制造方法
CN1221216A (zh) 引线框架及涂敷引线框架的方法
CN102403236B (zh) 芯片外露的半导体器件及其生产方法
US7768104B2 (en) Apparatus and method for series connection of two die or chips in single electronics package
CN1154179C (zh) 具薄膜基板的晶片封装组件
CN202034361U (zh) 一种半导体封装结构
CN108807352B (zh) 一种新型led灯丝制作方法
JP2000049382A (ja) 半導体発光装置及びその製造方法
CN100359655C (zh) 集成电路或分立元件平面凸点式封装工艺
CN102339762A (zh) 无载具的半导体封装件及其制造方法
CN205016516U (zh) 半导体装置和电子设备
CN2819476Y (zh) 新型集成电路或分立元件平面凸点式封装结构
CN216250730U (zh) 一种堆叠式芯片封装件

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee