TW201930646A - 具凸塊結構之半導體裝置及其製造方法 - Google Patents

具凸塊結構之半導體裝置及其製造方法 Download PDF

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Publication number
TW201930646A
TW201930646A TW107100404A TW107100404A TW201930646A TW 201930646 A TW201930646 A TW 201930646A TW 107100404 A TW107100404 A TW 107100404A TW 107100404 A TW107100404 A TW 107100404A TW 201930646 A TW201930646 A TW 201930646A
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Taiwan
Prior art keywords
bump
metal layer
semiconductor device
manufacturing
width
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TW107100404A
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English (en)
Inventor
李俊德
劉明昇
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頎邦科技股份有限公司
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Application filed by 頎邦科技股份有限公司 filed Critical 頎邦科技股份有限公司
Priority to TW107100404A priority Critical patent/TW201930646A/zh
Priority to CN201810292068.XA priority patent/CN110010576A/zh
Priority to US15/952,807 priority patent/US20190214357A1/en
Priority to SG10201803483RA priority patent/SG10201803483RA/en
Priority to JP2018089699A priority patent/JP2019121776A/ja
Publication of TW201930646A publication Critical patent/TW201930646A/zh

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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract

一種具凸塊結構之半導體裝置的製造方法，於形成該具凸塊結構之半導體裝置後另對該具凸塊結構之半導體裝置之該凸塊或該凸塊下金屬層進行一額外蝕刻，使該具凸塊結構之半導體裝置之性能及外觀能符合規範。

Description

具凸塊結構之半導體裝置及其製造方法
本發明是關於一種半導體裝置及其製造方法，特別是關於一種具凸塊結構之半導體裝置及其製作方法。
凸塊結構之製作為覆晶技術中的關鍵製程，其用以提供晶片與基板之間的電性連接，一般凸塊結構是藉由圖案化光阻層、電鍍及蝕刻製程形成於晶片上，使晶片能以反置的方式與基板進行連接，讓以覆晶技術製成之半導體裝置具有元件密度高、散熱能力佳及低成本等優點，並可大幅地縮小積體電路之尺寸，因此覆晶技術成為了目前積體電路重要的封裝製程之一，而如何提昇凸塊結構的製程良率則為覆晶技術的發展核心。
本發明的主要目的在於對凸塊或凸塊下金屬層進行額外之蝕刻，可進一步地清除正常蝕刻下未完全蝕刻的殘留金屬，以確保半導體裝置之外觀及性能可合乎規範。
本發明之一種具凸塊結構之半導體裝置的製造方法包含：提供一基板，該基板具有一導接墊及一保護層，該保護層之一開口顯露該導接墊；形成一凸塊下金屬層於該基板上，該凸塊下金屬層覆蓋該保護層及該開口顯露之該導接墊；形成一圖案化光阻層於該凸塊下金屬層上，該圖案化光阻層之一開孔顯露該凸塊下金屬層；於該圖案化光阻層之該開孔中形成一凸塊，該凸塊電性連接該凸塊下金屬層；剝離該圖案化光阻層以顯露該凸塊之一側壁及未被該凸塊罩蓋之該凸塊下金屬層；以該凸塊作為遮罩對該凸塊下金屬層進行一蝕刻，以顯露該保護層；以及對該凸塊或該凸塊下金屬層進行一額外蝕刻，以調整該凸塊之尺寸、清除殘留之金屬或清除該凸塊之髒汙。
本發明藉由對該凸塊或該凸塊下金屬層進行額外蝕刻，可有效的解決該具凸塊結構之半導體裝置可能之尺寸不符、金屬殘留及表面髒汙之問題，讓該具凸塊結構之半導體裝置的性能及外觀可合乎規範，以提高該具凸塊結構之半導體裝置的生產良率。
請參閱第1圖，其為本發明之一實施例，一種具凸塊結構之半導體裝置的製造方法10，其包含「提供基板11」、「形成凸塊下金屬層12」、「形成圖案化光阻層13」、「形成凸塊14」、「剝離圖案化光阻層15」、「對凸塊下金屬層進行蝕刻16」及「對凸塊或凸塊下金屬層進行額外蝕刻17」。
請參閱第1及2圖，於步驟11中提供一基板100，該基板100具有一本體110、一導接墊120及一保護層130，該導接墊120位於該本體110之一表面111上，以提供該本體110內部之元件(圖未繪出)與其他電子裝置或導線進行電性連接，該保護層130罩蓋該本體110之該表面111及部份之該導接墊120，該保護層130為一絕緣材料，用以提供該本體110之該表面111絕緣保護，該保護層130具有一開口131，該開口131顯露該導接墊120。在本實施例中，該本體110之材料可選自為矽、砷化鎵或其他半導體材料，該基板100具有複數個導接墊120，該些導接墊120之材料可選自為鋁、銅等金屬材料，該保護層130具有複數個開口131，且各該開口131顯露各該導接墊120。
請參閱第1及3圖，於步驟12中形成一凸塊下金屬層200於該基板100上，該凸塊下金屬層200覆蓋該保護層130及該開口131顯露之該導接墊120，在本實施例中，該凸塊下金屬層200具有一第一金屬層210及一第二金屬層220，該兩層金屬層是分別透過蒸鍍或濺鍍形成於該基板100上，其形成順序為先形成該第一金屬層210於該基板100上後，再形成該第二金屬層220於該第一金屬層210上，使得該第一金屬層210位於該基板100及該第二金屬層220之間，且該第一金屬層210接觸該保護層130及該導接墊120，該第二金屬層220則接觸該第一金屬層210。其中該第一金屬層210用以作為一黏結層(Adhesion layer)或阻障層(Barrier layer)，用以作為該導接墊120與其他金屬之間的連接介面或避免第二金屬層220的金屬離子遷移(Migration)，該第二金屬層220為一種子層(Seed layer)，用以定義後續凸塊的長成的圖形。
在本實施例中，該第一金屬層210之材料為鈦鎢合金，該第二金屬層220之材料為金，但本發明並不在此限。
請參閱第1及4圖，在步驟13中形成一圖案化光阻層300於該凸塊下金屬層200上，該圖案化光阻層300之一開孔310顯露該凸塊下金屬層200，其中形成該圖案化光阻層300的步驟包含：於該凸塊下金屬層200上塗佈一光阻層；以一遮罩對該光阻層進行曝光以定義該光阻層之形狀；以及對曝光之該光阻層進行顯影而形成該圖案化光阻層300，其中該圖案化光阻層300之材料可選自為正光阻(Positive photoresist)或負光阻(Negative photoresist)，皆可用以形成該圖案化光阻層300。
請參閱第1及5圖，在步驟14中於該圖案化光阻層300之該開孔310中形成一凸塊400，該凸塊400形成於該凸塊下金屬層200之該第二金屬層220上並電性連接該凸塊下金屬層200，其中該凸塊400能以蒸鍍、電鍍或印刷製程形成於該圖案化光阻層300之該開孔310中，在本實施例中，是以電鍍製程形成與該第二金屬層220之材料相同為金的該凸塊400於該圖案化光阻層300之該開孔310中。
請參閱第1及6圖，於步驟15中剝離該圖案化光阻層300以顯露該凸塊400之一側壁410及未被該凸塊400罩蓋之該凸塊下金屬層200，其中該圖案化光阻層300能以一剝離液以浸泡及沖洗的方式由該基板100上剝離。
請參閱第1、7及8圖，於步驟16中以該凸塊400作為遮罩對該凸塊下金屬層200進行一蝕刻，以除去未被該凸塊400罩蓋之該凸塊下金屬層200並顯露該保護層130而形成該具凸塊結構之半導體裝置D。在本實施例中，由於該凸塊下金屬層200具有一第一金屬層210及一第二金屬層220，因此，在第7及8圖中是分別以兩個蝕刻製程對該第一金屬層210及該第二金屬層220進行該蝕刻，以分別將該凸塊400未罩蓋之該第一金屬層210及該第二金屬層220去除。其中，請參閱第8圖，在完成兩次蝕刻後，該第一金屬層210具有一第一寬度W1M1 ，該第二金屬層220具有一第一寬度W1M2 ，且該第一金屬層210之該第一寬度W1M1 小於該第二金屬層220之該第一寬度W1M2 ，使得該第二金屬層220之邊緣與該保護層130之間產生一凹槽L。
請參閱第1圖，由於該具凸塊結構之半導體裝置D之外觀及性能不一定能符合規範而可能為不良品，因此，於步驟17中對該凸塊400或該凸塊下金屬層200進行一額外蝕刻，以對該凸塊400或該凸塊下金屬層200進行額外之蝕刻，以清除殘留之金屬或該凸塊400之髒汙或是調整該凸塊400之尺寸，使其成為良品。在本實施例中，該額外蝕刻是藉由觀察該具凸塊結構之半導體裝置D的外觀後，再選擇性地對該凸塊400或該凸塊下金屬層200進行蝕刻，較佳的，於步驟17前另包含對該具凸塊結構之半導體裝置D進行檢查之步驟，以判定該具凸塊結構之半導體裝置D是否有凸塊尺寸不符、金殘留、鈦鎢殘留或是表面髒汙的情形。
其中，若檢查結果為凸塊尺寸不符或表面髒汙，則須再次調整該凸塊400之尺寸或判定該凸塊400表面有化合物生成，而於步驟17額外對該凸塊400進行蝕刻，以調整該凸塊400之尺寸或將髒汙清除，請參閱第9圖，以蝕刻液對該凸塊400進行蝕刻時，由於該凸塊400之材料與該第二金屬層220之材料相同，蝕刻液也會對該第二金屬層220蝕刻，且在步驟16後該第二金屬層220與該保護層130之間形成有該凹槽L，因此，對該凸塊400進行額外蝕刻時，蝕刻液會在該凹槽L停留，使得讓該第二金屬層220的蝕刻速度相對於該凸塊400的蝕刻速度較快，而讓該第二金屬層220經額外蝕刻後之一第二寬度W2M2 小於該凸塊400之一寬度WB 及該第一金屬層210之該第一寬度W1M1 。
其中，若檢查結果為鈦鎢殘留，則代表該凸塊400未覆蓋之該第一金屬層210尚未完全移除，而於步驟17額外對該第一金屬層210進行蝕刻，以將殘留之該第一金屬層210清除，請參閱第8及10圖，由於在步驟16後該第二金屬層220與該保護層130之間形成有該凹槽L，因此，進行額外蝕刻時，蝕刻液會在該凹槽L停留，而對該凸塊400下之該第一金屬層210之側壁進行蝕刻，使得該第一金屬層210經過該額外蝕刻後具有一第二寬度W2M1 ，該第二寬度W2M1 小於額外蝕刻前之該第一寬度W1M1 。
其中，若檢查結果為金殘留，則代表該凸塊400未覆蓋之該第二金屬層220尚未完全移除，亦代表著位於殘留之該第二金屬層220下方之該第一金屬層210也未移除，因此於步驟17額外分別對該第二金屬層220及該第一金屬層210進行蝕刻，以將殘留之該第二金屬層220及該第一金屬層210清除，請參閱第8及11圖，對該第二金屬層220進行蝕刻時，雖然也會同時對該凸塊400蝕刻，但由於蝕刻液會在該凹槽L停留，使得讓該第二金屬層220的蝕刻速度相對於該凸塊400的蝕刻速度較快，而讓該第二金屬層220經額外蝕刻後之一第二寬度W2M2 小於該凸塊400之該寬度WB 。接著，對該第一金屬層210進行額外蝕刻，相同地，由於蝕刻液會在該凹槽L停留，而對該凸塊400下之該第一金屬層210之側壁進行蝕刻，使得該第一金屬層210經過該額外蝕刻後具有一第二寬度W2M1 ，該第一金屬層210之該第二寬度W2M1 小於該第二金屬層220經額外蝕刻後之該第二寬度W2M2 。
本發明藉由對該凸塊400或該凸塊下金屬層200進行額外蝕刻，可有效的解決該具凸塊結構之半導體裝置D可能之尺寸不符、金屬殘留及表面髒汙之問題，讓該具凸塊結構之半導體裝置D的性能及外觀合乎規範，以提高該具凸塊結構之半導體裝置D的生產良率。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
10‧‧‧具凸塊結構之半導體裝置的製造方法
11‧‧‧提供基板
12‧‧‧形成凸塊下金屬
13‧‧‧形成圖案化光阻層
14‧‧‧形成凸塊
15‧‧‧剝離圖案化光阻層
16‧‧‧對凸塊下金屬層進行蝕刻
17‧‧‧對凸塊或凸塊下金屬層進行額外蝕刻
100‧‧‧基板
110‧‧‧本體
120‧‧‧導接墊
130‧‧‧保護層
131‧‧‧開口
200‧‧‧凸塊下金屬層
210‧‧‧第一金屬層
220‧‧‧第二金屬層
300‧‧‧圖案化光阻層
310‧‧‧開孔
400‧‧‧凸塊
410‧‧‧側壁
D‧‧‧具凸塊結構之半導體裝置
W1M1‧‧‧第一金屬層之第一寬度
W2M1‧‧‧第一金屬層之第二寬度
W1M2‧‧‧第二金屬層之第一寬度
W2M2‧‧‧第二金屬層之第一寬度
WB‧‧‧凸塊之寬度
L‧‧‧凹槽
第1圖： 依據本發明之一實施例，一種具凸塊結構之半導體裝置的製造方法的流程圖。 第2至11圖： 依據本發明之一實施例，該具凸塊結構之半導體裝置之製作過程的剖視圖。

Claims (10)

  1. 一種具凸塊結構之半導體裝置的製造方法，其包含： 提供一基板，該基板具有一導接墊及一保護層，該保護層之一開口顯露該導接墊； 形成一凸塊下金屬層於該基板上，該凸塊下金屬層覆蓋該保護層及該開口顯露之該導接墊； 形成一圖案化光阻層於該凸塊下金屬層上，該圖案化光阻層之一開孔顯露該凸塊下金屬層； 於該圖案化光阻層之該開孔中形成一凸塊，該凸塊電性連接該凸塊下金屬層； 剝離該圖案化光阻層以顯露該凸塊之一側壁及未被該凸塊罩蓋之該凸塊下金屬層； 以該凸塊作為遮罩對該凸塊下金屬層進行一蝕刻，以顯露該保護層；以及 對該凸塊或該凸塊下金屬層進行一額外蝕刻，以調整該凸塊之尺寸、清除殘留之金屬或清除該凸塊之髒汙。
  2. 如申請專利範圍第1項所述之具凸塊結構之半導體裝置的製造方法，其中該凸塊下金屬層具有一第一金屬層及一第二金屬層，該第一金屬層位於該第二金屬層及該基板之間。
  3. 如申請專利範圍第2項所述之具凸塊結構之半導體裝置的製造方法，其中該額外蝕刻是對該凸塊金屬層之該第一金屬層、該第二金屬層或該第一金屬層及該第二金屬層進行額外蝕刻。
  4. 如申請專利範圍第3項所述之具凸塊結構之半導體裝置的製造方法，其中該第一金屬層之材料為鈦鎢合金。
  5. 如申請專利範圍第3項所述之具凸塊結構之半導體裝置的製造方法，其中該第二金屬層經過該額外蝕刻後具有一寬度，該寬度小於該凸塊之一寬度。
  6. 如申請專利範圍第5項所述之具凸塊結構之半導體裝置的製造方法，其中該第二金屬層之材料與該凸塊之材料相同。
  7. 如申請專利範圍第6項所述之具凸塊結構之半導體裝置的製造方法，其中該第二金屬層及該凸塊之材料為金。
  8. 如申請專利範圍第3項所述之具凸塊結構之半導體裝置的製造方法，其中該第二金屬層經過該額外蝕刻後具有一寬度，該第二金屬層之該寬度小於該第一金屬層經過該蝕刻後之該第一寬度，且該第二金屬層之該寬度大於該第一金屬層經過該額外蝕刻後之一第二寬度。
  9. 如申請專利範圍第8項所述之具凸塊結構之半導體裝置的製造方法，其中於額外蝕刻前另包含檢查該凸塊及該凸塊金屬層之步驟，以判定是否有該凸塊尺寸不符、該凸塊髒汙、該第一金屬層殘留或該第二金屬層殘留的問題，若判定為該凸塊尺寸不符或該凸塊髒汙，則對該凸塊進行額外蝕刻，若判定為該第一金屬層殘留，則對該第一金屬層進行額外蝕刻，若判定為該第二金屬層殘留，則對該第一金屬層及該第二金屬層進行額外蝕刻。
  10. 一種以申請專利範圍第1至9項任一項之方法製造之具凸塊結構之半導體裝置。
TW107100404A 2018-01-05 2018-01-05 具凸塊結構之半導體裝置及其製造方法 TW201930646A (zh)

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