TW201606453A - 光阻剝離方法 - Google Patents

光阻剝離方法 Download PDF

Info

Publication number
TW201606453A
TW201606453A TW103126825A TW103126825A TW201606453A TW 201606453 A TW201606453 A TW 201606453A TW 103126825 A TW103126825 A TW 103126825A TW 103126825 A TW103126825 A TW 103126825A TW 201606453 A TW201606453 A TW 201606453A
Authority
TW
Taiwan
Prior art keywords
layer
bump
patterned photoresist
photoresist layer
stripping method
Prior art date
Application number
TW103126825A
Other languages
English (en)
Other versions
TWI595332B (zh
Inventor
施政宏
楊國華
侯翔彬
Original Assignee
頎邦科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 頎邦科技股份有限公司 filed Critical 頎邦科技股份有限公司
Priority to TW103126825A priority Critical patent/TWI595332B/zh
Priority to CN201410440251.1A priority patent/CN105321807A/zh
Priority to JP2014183253A priority patent/JP2016039358A/ja
Priority to KR1020140124219A priority patent/KR20160016479A/ko
Priority to US14/530,896 priority patent/US9230823B1/en
Priority to SG10201407663TA priority patent/SG10201407663TA/en
Publication of TW201606453A publication Critical patent/TW201606453A/zh
Application granted granted Critical
Publication of TWI595332B publication Critical patent/TWI595332B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • H01L2224/02311Additive methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0231Manufacturing methods of the redistribution layers
    • H01L2224/02313Subtractive methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02331Multilayer structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/034Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346Plating
    • H01L2224/03464Electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/0347Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03914Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05008Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0502Disposition
    • H01L2224/05022Disposition the internal layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05541Structure
    • H01L2224/05548Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05575Plural external layers
    • H01L2224/0558Plural external layers being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11464Electroless plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1181Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13024Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Weting (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

一種光阻剝離方法包含:提供一半導體基板、一浸泡步驟及一剝離步驟,其中該半導體基板具有一基板、一銲墊、一保護層、一凸塊下金屬層、一圖案化光阻層及一凸塊,該圖案化光阻層覆蓋該凸塊下金屬層及該凸塊之一側面,且該圖案化光阻層及該凸塊之該側面之間形成有一第一接合界面,該圖案化光阻層及該凸塊下金屬層之間形成有一第二接合界面,於浸泡步驟中,由於該圖案化光阻接觸一化學液,可使得該第一接合界面的接合強度減弱,因此,於剝離步驟中以具有適當衝擊力之一流體沖刷該半導體基板,可使該圖案化光阻層由該基板上剝離。

Description

光阻剝離方法
本發明是關於一種光阻剝離方法,特別是關於一種以流體剝離光阻之光阻剝離方法。
習知凸塊製程包含:於基板上形成一光阻層;對該光阻層進行曝光/顯影,以圖案化該光阻層;於圖案化之該光阻層中鍍上凸塊;最後再將圖案化之該光阻層移除而完成凸塊製程。其中於移除光阻的製程中,一般是將覆蓋有該光阻層之該基板浸入光阻剝離液中,使得該光阻層產生膨潤、裂解而由該基板上剝離,但根據不同的產品需求考量,製程中所使用的光阻材料及光阻剝離液的種類皆不相同,而造成習知技術於光阻剝離的製程中常因將該基板浸入光阻剝離液的時間過長而導致凸塊的散落或是導致該基板之一保護層的損壞。反之,若該基板浸入光阻剝離液的浸泡時間過短,則易導致光阻層的殘留,而影響凸塊製程的良率。此外,於凸塊製程中由於凸塊需具有一定的厚度,因此,該光阻層的厚度亦需塗佈有相對之厚度,而導致於光阻剝離液浸泡的時間較長,且光阻剝離液的使用量亦較多,而造成環境上的負擔以及製作成本的增加。
本發明之一種光阻剝離方法藉由流體沖刷覆蓋有光阻之半導體基板,以使光阻層由半導體基板上剝離,可大幅減少浸泡化學液之時間,並減少化學液之用量,且由於浸泡化學液的時間較短,本發明之光阻剝離方法並不會影響半導體基板之結構,而可大幅提升生產之良率。
一種光阻剝離方法包含提供一半導體基板,該半導體基板具有一基板、一銲墊、一保護層、一凸塊下金屬層、一圖案化光阻層及一凸塊,該銲墊位於該基板之一表面,該保護層覆蓋該基板及該銲墊,且該保護層具有一開口,該開口顯露該銲墊,該凸塊下金屬層覆蓋該保護層,該凸塊設置於該凸塊下金屬層上,該凸塊具有一側面,該圖案化光阻層覆蓋該凸塊下金屬層及該凸塊之該側面,且該圖案化光阻層及該凸塊之該側面之間形成有一第一接合界面,該圖案化光阻層及該凸塊下金屬層之間形成有一第二接合界面,其中該第一接合界面具有一第一接合強度,該第二接合界面具有一第二接合強度,接著,將該半導體基板浸泡至一化學液中,使該化學液接觸該圖案化光阻層,且該化學液滲入該第一接合界面中,使該第一接合界面之該第一接合強度轉變為一第三接合強度,該第二接合界面之該第二接合強度轉變為一第四接合強度,其中該第三接合強度小於該第一接合強度,接著,以一流體沖刷該半導體基板,該流體具有一衝擊力,該衝擊力大於該第三接合強度及該第四接合強度,以使該圖案化光阻層由該基板上剝離,以顯露該凸塊之該側面及該凸塊下金屬層。
本發明藉由流體沖刷的方式剝離該圖案化光阻層,可大幅減短該半導體基板浸泡於該化學液中的浸泡時間,使得該化學液的使用量下降而減少製作成本,且由於浸泡時間短可避免該半導體基板之該凸塊或其他元件的損壞,以提昇製程之良率。
請參閱第1圖,為本發明之第一實施例,一種光阻剝離方法10的流程圖,請參閱第1及2圖,於「提供半導體基板11」中提供一半導體基板100,其中該半導體基板100具有一基板110、一銲墊120及一保護層130,該銲墊120位於該基板110之一表面111,該保護層130覆蓋該基板110及該銲墊120,且該保護層130具有一開口131,該開口131顯露該銲墊120,該銲墊120可選自於銅、鋁、銅合金或其他導電材料。
請參閱第1及3圖,於「形成凸塊下金屬層12」中是以蒸鍍、濺鍍、電鍍或無電鍍之製程於該保護層130上鍍上一凸塊下金屬層140,該凸塊下金屬層140覆蓋該保護層130,且該凸塊下金屬層140連接該銲墊120,其中該凸塊下金屬層140可為多層金屬層之結構,其包含黏著層(Adhesion layer)、擴散阻礙層(Diffusion barrier layer)、潤濕層(Wetting layer)及抗氧化層(Oxidation barrier layer),但本發明並不在此限。
請參閱第1及4圖,於「形成光阻層13」中於該凸塊下金屬層140上形成一光阻層150,該光阻層150以塗佈及烘烤等製程形成於該凸塊下金屬層140上,該光阻層150可選自於正光阻(positive photoresist)或負光阻(negative photoresist)。
請參閱第1、4及5圖,於「圖案化光阻層14」中以一光罩作為遮罩對該光阻層150進行曝光製程(expose process),使該光阻層150的感光區域產生化學變化,接著於顯影製程(developing process)中以一顯影液移除不需要之光阻,而形成一圖案化光阻層160,該圖案化光阻層160覆蓋該凸塊下金屬層140,且該圖案化光阻層160顯露部分之該凸塊下金屬層140,其中該圖案化光阻層160具有一高度H1,在本實施例中,該圖案化光阻層160之該高度H1介於150μm至200μm之間。
請參閱第1及6圖,於「形成凸塊15」中,是以蒸鍍、濺鍍、電鍍、無電鍍或印刷製程形成一凸塊170於該圖案化光阻層160中,該凸塊170設置於該凸塊下金屬層140上,該凸塊170用以使該銲墊120與另一基板(圖未繪出)進行電性連接,該凸塊170具有一側面171及一高度H2,其中該圖案化光阻層160覆蓋該凸塊170之該側面171,該凸塊170之該高度H2介於150μm至200μm之間,該凸塊170可自於金、銅/鎳、銅/鎳/金、錫/銀或其他導電金屬。
請再參閱第6圖,該圖案化光阻層160及該凸塊170之該側面171之間形成有一第一接合界面S1,該圖案化光阻層160及該凸塊下金屬層140之間形成有一第二接合界面S2,其中該第一接合界面S1具有一第一接合強度,該第二接合界面S2具有一第二接合強度,由於此時該第一接合強度及該第二接合強度皆強,因此無法輕易將該圖案化光阻層160由該半導體基板100上剝離。
請參閱第1及7圖,於「浸泡步驟16」中將該半導體基板100浸泡至一化學液中,該化學液接觸該圖案化光阻層160,使該圖案化光阻層160產生化學變化,且該化學液滲入該第一接合界面S1中,使該第一接合界面S1之該第一接合強度轉變為一第三接合強度,該第二接合界面S2之該第二接合強度轉變為一第四接合強度,較佳的,該第三接合強度小於該第一接合強度,且該第四接合強度小於該第二接合強度。由於本發明在「浸泡步驟16」中並非要以該化學液剝離該圖案化光阻層160,而是用以降低該圖案化光阻層160與該凸塊下金屬層140及該凸塊170之間的接合強度,因此,可大幅減短該半導體基板100於「浸泡步驟16」中浸泡該化學液的一浸泡時間並減少該化學液之用量,較佳的,該浸泡時間介於1分鐘至40分鐘之間。
請參閱第1及7圖,於「清洗步驟17」中以去離子水(DIW)或超純水(UPW)清洗該半導體基板100,主要是用以清除殘留於該基板110之一背面112的該化學液,由於後續製程中該半導體基板100會以機械手臂固定於該基板110之該背面112,若該化學液殘留於該基板110之該背面112,將可能造成該半導體基板100的損壞。
請參閱第1及8圖,於「剝離步驟18」中以一噴嘴(圖未繪出)噴出一流體沖刷該半導體基板100,較佳的,該流體為二流體(two-phase flow),且該流體可選自於去離子水(DIW)混合氮氣或二氧化碳,其中該噴嘴至該半導體基板100具有一間距,該間距介於0.2公分至1公分之間,且該流體的流量介於3LPM至5LPM之間,使該流體具有一衝擊力,該衝擊力大於該第三接合強度及該第四接合強度,以使該圖案化光阻層160由該基板110上剝離,以顯露該凸塊170之該側面171及該凸塊下金屬層140。由於在「浸泡步驟16」中已對該圖案化光阻層160進行初步處理,因此,以該流體沖刷該半導體基板100的一沖刷時間介於10秒至30秒之間即可將該圖案化光阻層160由該基板110上剝離。
請參閱第1圖,於「乾燥步驟19」中以IPA乾燥或旋乾的方式去除該半導體基板100上殘留之水分。
請參閱第1及9圖,於「凸塊下金屬層蝕刻20」中以該凸塊170作為遮罩對該凸塊下金屬層140蝕刻,而移除不需要之該凸塊下金屬層140,僅留下位於該凸塊170下之該凸塊下金屬層140。
請參閱第10至19圖,為本發明之第二實施例的製作流程,為一種1P2M製程,其與第一實施例的差異在於其另具有一保護層130A及一線路層180,該保護層130A是在形成該凸塊下金屬層140前形成於該保護層130上,以確保該凸塊下金屬層140與該基板110之間的絕緣,且該保護層130A亦顯露出該銲墊120,在本實施例中,該凸塊下金屬層140形成於該保護層130A上並電性連接該銲墊120。請參閱第13至15圖,該線路層180藉由一圖案化光阻層160A形成於該凸塊下金屬層140上以作為重分佈線路層(Redistribution Layer),其中在該線路層180形成於該凸塊下金屬層140後,亦可藉由「浸泡步驟16」及「剝離步驟18」將該圖案化光阻層160A剝離。相同地,請參閱第16至18圖,藉由該圖案化光阻層160於該線路層180及該凸塊下金屬層140上形成該凸塊170,並藉由「浸泡步驟16」及「剝離步驟17」剝離該圖案化光阻層160。在本實施例中,由於該圖案化光阻層160A及該圖案化光阻層160皆可藉由「浸泡步驟16」及「剝離步驟18」進行剝離,因此,可大幅減少該化學液的使用量且避免該基板上110之微電路的損壞。
請參閱第20至32圖,為本發明之第三實施例的製作流程,為一種2P2M製程,其與第一實施例的差異在於其另具有一保護層130A、一線路層180、一保護層130B及一凸塊下金屬層140A,其中該保護層130A及該線路層180與第二實施例相同,分別作為絕緣層及重分佈線路層。請參閱第27圖,在本實施例中,在形成該線路層180後,另形成該保護層130B於該線路層180上,以保護該線路層180,且該保護層130B顯露該線路層180。請參閱第28至31圖,在本實施例中,形成該凸塊下金屬層140A於該保護層130A上,以作為該凸塊170及該保護層130A之間的黏著層,接著,藉由該圖案化光阻層160將該凸塊170形成於該凸塊下金屬層140A上。請參閱第24及30圖,在本實施例中,在分別藉由該圖案化光阻層160A及該圖案化光阻層160形成該線路層180及該凸塊170後,該圖案化光阻層160A及該圖案化光阻層160皆可藉由「浸泡步驟16」及「剝離步驟17」進行剝離,以大幅減少該化學液的使用量且避免該基板110上之微電路的損壞。
此外,在3P3M、4P3M或多P多M的製程中,皆可藉由「浸泡步驟16」及「剝離步驟17」進行圖案化光阻層的剝離,由於在多P多M的製程需多道圖案化光阻層的剝離製程,因此,藉由本發明之該光阻剝離方法10可節省更多的化學液用量,可減少製作之成本及降低環境之污染。
本發明藉由流體沖刷的方式剝離該圖案化光阻層160,可大幅減短該半導體基板100浸泡於該化學液中的該浸泡時間,使得該化學液的使用量下降而減少製作成本,且由於該浸泡時間短可避免該半導體基板100之該凸塊170或其他元件的損壞,以提昇製程之良率。
本發明之保護範圍當視後附之申請專利範圍所界定者為準,任何熟知此項技藝者,在不脫離本發明之精神和範圍內所作之任何變化與修改,均屬於本發明之保護範圍。
10‧‧‧光阻剝離方法
11‧‧‧提供半導體基板
12‧‧‧形成凸塊下金屬層
13‧‧‧形成光阻層
14‧‧‧圖案化光阻層
15‧‧‧形成凸塊
16‧‧‧浸泡步驟
17‧‧‧清洗步驟
18‧‧‧剝離步驟
19‧‧‧乾燥步驟
20‧‧‧凸塊下金屬層蝕刻
100‧‧‧半導體基板
110‧‧‧基板
111‧‧‧表面
112‧‧‧背面
120‧‧‧銲墊
130‧‧‧保護層
130A‧‧‧保護層
130B‧‧‧保護層
131‧‧‧開口
140‧‧‧凸塊下金屬層
140A‧‧‧凸塊下金屬層
150‧‧‧光阻層
160‧‧‧圖案化光阻層
160A‧‧‧圖案化光阻層
170‧‧‧凸塊
171‧‧‧側面
180‧‧‧線路層
S1‧‧‧第一接合界面
S2‧‧‧第二接合界面
H1‧‧‧高度
H2‧‧‧高度
第1圖:依據本發明之第一實施例,一種光阻剝離方法之流程圖。 第2至9圖:依據本發明之第一實施例,一半導體基板之側面剖視圖。 第10至19圖:依據本發明之第二實施例,一半導體基板之側面剖視圖。 第20至32圖:依據本發明之第三實施例,一半導體基板之側面剖視圖。
10‧‧‧光阻剝離方法
11‧‧‧提供半導體基板
12‧‧‧形成凸塊下金屬層
13‧‧‧形成光阻層
14‧‧‧圖案化光阻層
15‧‧‧形成凸塊
16‧‧‧浸泡步驟
17‧‧‧清洗步驟
18‧‧‧剝離步驟
19‧‧‧乾燥步驟
20‧‧‧凸塊下金屬層蝕刻

Claims (12)

  1. 一種光阻剝離方法,其包含: 提供一半導體基板,該半導體基板具有一基板、一銲墊、一保護層、一凸塊下金屬層、一圖案化光阻層及一凸塊,該銲墊位於該基板之一表面,該保護層覆蓋該基板及該銲墊,且該保護層具有一開口,該開口顯露該銲墊,該凸塊下金屬層覆蓋該保護層,該凸塊設置於該凸塊下金屬層上,該凸塊具有一側面,該圖案化光阻層覆蓋該凸塊下金屬層及該凸塊之該側面,且該圖案化光阻層及該凸塊之該側面之間形成有一第一接合界面,該圖案化光阻層及該凸塊下金屬層之間形成有一第二接合界面,其中該第一接合界面具有一第一接合強度,該第二接合界面具有一第二接合強度; 一浸泡步驟,將該半導體基板浸泡至一化學液中,使該化學液接觸該圖案化光阻層,且該化學液滲入該第一接合界面中,使該第一接合界面之該第一接合強度轉變為一第三接合強度,該第二接合界面之該第二接合強度轉變為一第四接合強度,其中該第三接合強度小於該第一接合強度;以及 一剝離步驟,以一流體沖刷該半導體基板,該流體具有一衝擊力,該衝擊力大於該第三接合強度及該第四接合強度,以使該圖案化光阻層由該基板上剝離,以顯露該凸塊之該側面及該凸塊下金屬層。
  2. 如申請專利範圍第1項所述之光阻剝離方法,其中該第四接合強度小於該第二接合強度。
  3. 如申請專利範圍第1項所述之光阻剝離方法,其中該流體為二流體(two-phase flow)。
  4. 如申請專利範圍第3項所述之光阻剝離方法,其中該流體的流量介於3LPM至5LPM之間。
  5. 如申請專利範圍第4項所述之光阻剝離方法,其中於剝離步驟中,是以一噴嘴噴出該流體,且該噴嘴至該半導體基板具有一間距,該間距介於0.2公分至1公分之間。
  6. 如申請專利範圍第5項所述之光阻剝離方法,其中以該流體沖刷該半導體基板具有一沖刷時間,該沖刷時間介於10秒至30秒之間。
  7. 如申請專利範圍第1項所述之光阻剝離方法,其中以將該半導體基板浸泡至該化學液中具有一浸泡時間,該浸泡時間介於1分鐘至40分鐘之間。
  8. 如申請專利範圍第3項所述之光阻剝離方法,其中該流體可選自於去離子水(DIW)混合氮氣或二氧化碳。
  9. 如申請專利範圍第1項所述之光阻剝離方法,其中該凸塊具有一高度,該凸塊之該高度介於150μm至200μm之間。
  10. 如申請專利範圍第1或9項所述之光阻剝離方法,其中該圖案化光阻層具有一高度,該圖案化光阻層之該高度介於150μm至200μm之間。
  11. 如申請專利範圍第1項所述之光阻剝離方法,其中於剝離步驟前包含有一清洗步驟,以清除殘留於該基板之一背面的該化學液。
  12. 如申請專利範圍第1項所述之光阻剝離方法,其中於剝離步驟後包含一乾燥步驟,以去除水分。
TW103126825A 2014-08-05 2014-08-05 光阻剝離方法 TWI595332B (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
TW103126825A TWI595332B (zh) 2014-08-05 2014-08-05 光阻剝離方法
CN201410440251.1A CN105321807A (zh) 2014-08-05 2014-08-28 光刻胶剥离方法
JP2014183253A JP2016039358A (ja) 2014-08-05 2014-09-09 フォトレジスト剥離方法
KR1020140124219A KR20160016479A (ko) 2014-08-05 2014-09-18 포토레지스트 박리 방법
US14/530,896 US9230823B1 (en) 2014-08-05 2014-11-03 Method of photoresist strip
SG10201407663TA SG10201407663TA (en) 2014-08-05 2014-11-17 Method of photoresist strip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103126825A TWI595332B (zh) 2014-08-05 2014-08-05 光阻剝離方法

Publications (2)

Publication Number Publication Date
TW201606453A true TW201606453A (zh) 2016-02-16
TWI595332B TWI595332B (zh) 2017-08-11

Family

ID=54939286

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103126825A TWI595332B (zh) 2014-08-05 2014-08-05 光阻剝離方法

Country Status (6)

Country Link
US (1) US9230823B1 (zh)
JP (1) JP2016039358A (zh)
KR (1) KR20160016479A (zh)
CN (1) CN105321807A (zh)
SG (1) SG10201407663TA (zh)
TW (1) TWI595332B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108198751B (zh) * 2017-12-27 2020-08-04 深圳市华星光电技术有限公司 光阻层剥离方法
CN111834216B (zh) * 2019-04-15 2022-07-15 中国科学院物理研究所 一种制备纳米尺寸金属薄膜图形的方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02106040A (ja) * 1988-10-14 1990-04-18 Teru Kyushu Kk 有機被膜の除去方法
JP3940742B2 (ja) * 1996-01-12 2007-07-04 忠弘 大見 洗浄方法
CN1129036C (zh) * 1998-02-26 2003-11-26 弗莱斯金属公司 抗蚀层的剥离方法
JP2000012605A (ja) * 1998-06-18 2000-01-14 World Metal:Kk 半導体チップの電極部の形成方法
JP2000058494A (ja) * 1998-08-06 2000-02-25 Sony Corp 洗浄方法及び洗浄装置
JP3869566B2 (ja) * 1998-11-13 2007-01-17 三菱電機株式会社 フォトレジスト膜除去方法および装置
JP2001085456A (ja) * 1999-09-10 2001-03-30 Seiko Epson Corp バンプ形成方法
JP3516446B2 (ja) * 2002-04-26 2004-04-05 東京応化工業株式会社 ホトレジスト剥離方法
JP2006049713A (ja) * 2004-08-06 2006-02-16 Sekisui Chem Co Ltd レジスト除去方法及びレジスト除去装置
KR20070120609A (ko) * 2005-04-15 2007-12-24 어드밴스드 테크놀러지 머티리얼즈, 인코포레이티드 마이크로전자 소자로부터 이온 주입 포토레지스트층을세정하기 위한 배합물
KR101319217B1 (ko) * 2006-11-15 2013-10-16 동우 화인켐 주식회사 포토레지스트 박리액 조성물 및 이를 이용하는포토레지스트의 박리방법
KR20080088246A (ko) * 2007-03-29 2008-10-02 삼성전자주식회사 반도체 기판 세정 방법
US20080245390A1 (en) * 2007-04-03 2008-10-09 Lam Research Corporation Method for cleaning semiconductor wafer surfaces by applying periodic shear stress to the cleaning solution
TWI405052B (zh) * 2007-11-30 2013-08-11 Daxin Materials Corp 光阻清洗劑以及應用其之清洗光阻的方法
TWM352128U (en) * 2008-10-08 2009-03-01 Int Semiconductor Tech Ltd Semiconductor structure having silver bump
JP4413266B1 (ja) * 2008-12-15 2010-02-10 アクアサイエンス株式会社 対象物洗浄方法及び対象物洗浄システム
US8569897B2 (en) * 2009-09-14 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Protection layer for preventing UBM layer from chemical attack and oxidation
CN103119694A (zh) * 2009-12-11 2013-05-22 高级技术材料公司 掩蔽材料的去除
JP2011171691A (ja) * 2010-01-21 2011-09-01 Tohoku Univ マイクロ・ナノソリッド利用型半導体洗浄システム
US9018758B2 (en) * 2010-06-02 2015-04-28 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall spacer and metal top cap
JP2012174741A (ja) * 2011-02-17 2012-09-10 Aqua Science Kk 複連ノズル及び当該複連ノズルを備える基板処理装置
JP6347572B2 (ja) * 2012-07-12 2018-06-27 東邦化成株式会社 リフトオフ装置およびリフトオフ方法

Also Published As

Publication number Publication date
KR20160016479A (ko) 2016-02-15
JP2016039358A (ja) 2016-03-22
SG10201407663TA (en) 2016-03-30
US9230823B1 (en) 2016-01-05
CN105321807A (zh) 2016-02-10
TWI595332B (zh) 2017-08-11

Similar Documents

Publication Publication Date Title
JP5296590B2 (ja) 半導体パッケージの製造方法
JP4209178B2 (ja) 電子部品実装構造及びその製造方法
JP5599276B2 (ja) 半導体素子、半導体素子実装体及び半導体素子の製造方法
KR20060103799A (ko) 반도체 장치 및 그 제조 방법
TWI534296B (zh) 蝕刻底層凸塊金屬化層及產生的裝置
CN101916722A (zh) 防止晶圆边缘产生镀金属剥离的方法
JP2012114173A (ja) 半導体装置の製造方法及び半導体装置
TWI595332B (zh) 光阻剝離方法
CN102254842A (zh) 电镀工艺中的活化处理
JP2008288607A (ja) 電子部品実装構造の製造方法
JP2012074406A (ja) 半導体装置および半導体装置の製造方法
JP4797368B2 (ja) 半導体装置の製造方法
JP5633095B2 (ja) 半導体パッケージの製造方法および半導体パッケージ
JP2003301293A (ja) 半導体装置の製造方法
JP4119740B2 (ja) 半導体装置の製造方法
JP6385202B2 (ja) 半導体装置の製造方法
KR101341634B1 (ko) 비지에이 패키지에 사용되는 회로 기판
TW201930646A (zh) 具凸塊結構之半導體裝置及其製造方法
JP2006120803A (ja) 半導体装置及び半導体装置の製造方法
JP4161754B2 (ja) 半導体装置の製造方法
JP4126392B2 (ja) 半導体装置の製造方法
KR100599636B1 (ko) 무 도금선 패턴을 갖는 비오씨 반도체 패키지용인쇄회로기판의 제조방법
JP3362574B2 (ja) バリアメタルの形成方法
JP2005129665A (ja) 半導体装置およびその製造方法
WO2006046806A1 (en) Method of supplying flux to semiconductor device