TWM352128U - Semiconductor structure having silver bump - Google Patents

Semiconductor structure having silver bump Download PDF

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Publication number
TWM352128U
TWM352128U TW097218044U TW97218044U TWM352128U TW M352128 U TWM352128 U TW M352128U TW 097218044 U TW097218044 U TW 097218044U TW 97218044 U TW97218044 U TW 97218044U TW M352128 U TWM352128 U TW M352128U
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TW
Taiwan
Prior art keywords
silver
width
metal layer
bump
base metal
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TW097218044U
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Chinese (zh)
Inventor
Yung-Fa Huang
Chih-Wen Ho
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Int Semiconductor Tech Ltd
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Priority to TW097218044U priority Critical patent/TWM352128U/en
Publication of TWM352128U publication Critical patent/TWM352128U/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

M352128 八、新型說明: 【新型所屬之技術領域】 本創作係有關於一種半導體結構,特別係 銀具有銀凸塊之半導體結構。 ’、關於一種 【先前技術】 傳統之驅動ic係使用金凸塊做為電性連接 由於物價域,金價也隨之域,使得封裝廠所W介,但 金壓力變Λ,在成本轉價不易及製造成本提高之产又之資 產品競爭力相對降低,|致封裝薇不僅無法獲利:形下’ 虧損。 甚至可能 【新型内容】 本創作之主要目的係在於提供一種具有銀凸塊之“ 體結構,其係包含一半導體裝置、一第一基底金屬層Ί 第二基底金屬層以及至少一銀凸塊,該半導體裝 I 1糸具^有 至少一銲墊及一保護層,該保護層係具有至少— .上 Ί 以顯 % 路該銲墊,該第一基底金屬層係形成於該銲墊上,該第 基底金屬層係具有一第一側面及一第二側面,該第_ * ^ 一·'暴底 金屬層係形成於該第一基底金屬層上,該第二基底金屬層 係具有一第三側面及一第四側面,該銀凸塊係形成於兮第 二基底金屬層上,該銀凸塊係具有一第五側面及一第六侧 面,其中該第一側面、該第三側面及該第五側面係位於同 +面’ §玄第·一側面、該第四側面及該第/、側面係彳立於同 一平面。本創作係利用該銀凸塊取代傳統之金凸壤以作為 電性連接之媒介,進而降低生產成本及提高產品競爭力。 5 M352128 【實施方式】 請參閱第1圖,依據本創作之一具體實施例係揭示一 種具有銀凸塊之半導體結構10〇,其係主要包含一半導體 ' 裝置110、一第一基底金屬層120、一第二基底金屬層13〇 以及至少一銀凸塊丨40 ’該半導體裝置丨丨〇係具有至少一 銲墊1 11及一保護層1丨2,在本實施例中,該半導體裝置 • 11 0係可為矽晶片或矽晶圓,該保護層11 2係具有至少一 _開口 113以顯露該銲墊111,該第一基底金屬層丨2〇係形 成於該銲墊m上,該第一基底金屬層120係具有一第一 側面1 2 1及一第二側面丨22,在本實施例中,該第一基底 金屬層120之材質係為鈦鎢’該第二基底金屬層13〇係形 成於該第—基底金屬層120上,該第二基底金屬層13〇係 具有第二側面1 3 1及一第四側面1 3 2,在本實施例中, 該第二基底金屬層丨3 0之材質係為金,該銀凸塊丨4〇係形 成於該第二基底金屬層130上,該銀凸塊14〇係具有一第 •五側面141及一第六側面142,其中該第一側面m、該第 —側面1 3 1及該第五側面1 4 1係位於同一平面,該第二側 面122、該第四側面1S2及該第六側面μ〗係位於同一平 面。 此外’請參閱第2圖,在本實施例中,該銀凸塊1 4〇 係包含有一第一凸塊部i 43及一第二凸塊部1 44,該第一 凸塊部1 43係具有一第一寬度w 1,該第二凸塊部丨44係具 有一第二寬度W2且該第一寬度W1係大於該第二寬度 w 2 ’該保護層1 1 2之該開口 1 1 3係具有一第三寬度W 3, 6 ;M352128 該銀凸塊1 40之該第一寬度W 1係大於該第三寬方 該銀凸塊1 40之該第二寬度W2係不大於該第三, 另’該銲墊111係具有一第四寬度W4,該第四寬 大於該第一寬度W 1。本創作係利用該銀凸塊1 4 0 連接之媒介,取代傳統以金凸塊作為電性連接之 法’達到降低生產成本及提高產品競爭力之目的 ' 請參閱第3A至3L圖’其係為該具有銀凸塊 籲結構之製程之截面示意圖’首先,請參閱第3A 一半導體裝置110,該半導體裝置110係可選自 或石夕晶圓,該半導體裝置1 1 0係具有至少一銲墊 保護層1 1 2,該保護層1 1 2係具有至少一開口 1 ] 該銲墊1 1 1,接著,請參閱第3B圖,濺鍍形成一 層12〇’於該銲墊111及該保護層112上,在本實 該第—金屬層120,之材質係為鈦鎢,接著,請| 圖’濺鍍形成一第二金屬層130,於該第一金屬層 φ 在本貫施例中,該第二金屬層1 3 〇,之材質係為金 請參閱第3D圖,塗佈一光阻層200於該第二金 上’接著,請參閱第3E圖,設置一遮罩300於 2 00上’之後,請參閱第3f圖,曝光顯影該光阻 使该光阻層2 〇 〇形成有至少一槽孔2 1 〇 ’接著, 3G圖,以電漿清洗該光阻層200之該槽孔210, 留之該光阻層200,之後,請參閱第3H圖,電 140’於該槽孔210内,接著,請參閱第31圖,移 層2〇〇以形成至少一銀凸塊14〇於該第二金屬層 L W3,且 L 度 W3, 度W4係 作為電性 媒介之方 〇 之半導體 圖,提供 於矽晶片 1 1 1 及一 l3以顯露 第一金屬 施例中, ^閱第 3C 120,上, ,之後, 屬層130’ 該光阻層 層20 0以 請參閱第 以去除殘 鑛一銀層 除該光阻 130,上, 7 ,M352128 之後,請參閱第3 J圖,再次以電漿清洗該銀凸塊 第二金屬層 130’之表面以去除殘留之該光阻層 • 著,請參閱第3K圖,以該銀凸塊140為遮罩蝕: • 金屬層1 20 ’及該第二金屬層1 3 0 ’,以使該銀凸塊 形成有一第一基底金屬層120及一第二基底金屬 該第一基底金屬層120係具有一第一側面121及 ~ 面122,該第二基底金屬層130係具有一第三側, . 一第四侧面1 3 2,該銀凸塊1 40係具有一第五側 胃一第六侧面142,其中該第一側面1 21、該第三 及該第五側面141係位於同一平面,該第二側面 第四侧面1 3 2及該第六側面1 42係位於同一平面 請參閱第3L圖,韌化該銀凸塊1 40並形成一具有 半導體結構1 〇〇,最後,經過出貨檢驗之步驟後 出貨至客戶端。 本創作之保護範圍當視後附之申請專利範圍 φ 為準,任何熟知此項技藝者,在不脫離本創作之 圍内所作之任何變化與修改,均屬於本創作之保 【圖式簡單說明】 第 1 圖:依據本創作之一具體實施例,一 凸塊之半導體結構之截面不意圖 第 2 圖:依據本創作之一具體實施例,該 塊之半導體結構之局部放大圖。 第3 A至3 L圖:依據本創作之一具體實施例,該 塊之半導體結構之製程之截面示 1 4 0及該 2 00,接 刻該第一 140下方 層 130, 一第二側 面1 3 1及 面141及 侧面 1 3 1 122、該 。之後, 銀凸塊之 即可包裝 所界定者 精神和範 護範圍。 種具有銀 〇 具有銀凸 具有銀凸 意圖。 8 M352128 【主要元件符號說明】 100 具 有 銀 凸 塊 之 半導體 結構 110 半 導 體 裝 置 111 銲 墊 112 保 護 層 113 開 a 120 第 一 基 底 金 屬 層 1205 第 一 金 屬 層 121 第 一 侧 面 122 第 一 _ 側 面 130 第 二 基 底 金 屬 層 1 305 第 金 屬 層 13 1 第 二 側 面 132 第 四 侧 面 140 銀 凸 塊 140, 銀 層 141 第 五 侧 面 142 第 六 側 面 143 第 '* 凸 塊 部 144 第 — 凸 塊 部 200 光 阻 層 210 槽 孔 300 遮 罩 W1 第 一 寬 度 W2 第 -— 寬 度 W3 第 二 寬 度 W4 第 四 寬 度M352128 VIII. New Description: [New Technology Field] This creation is about a semiconductor structure, especially a semiconductor structure with silver bumps. 'About a kind of [previous technology] The traditional driving ic system uses gold bumps as electrical connections. Because of the price field, the price of gold also follows the domain, which makes the packaging factory to be introduced, but the gold pressure is changed, and the cost is not easy to change. And the production cost of the product and the competitiveness of the product is relatively reduced, so that the package Wei is not only profitable: the shape of the loss. It is even possible [new content] The main purpose of the present invention is to provide a "body structure" having silver bumps, comprising a semiconductor device, a first base metal layer, a second base metal layer, and at least one silver bump. The semiconductor device has at least one pad and a protective layer, and the protective layer has at least a top layer to expose the pad, and the first base metal layer is formed on the pad. The first base metal layer has a first side and a second side, and the first metal layer is formed on the first base metal layer, and the second base metal layer has a third The silver bump is formed on the second base metal layer, the silver bump has a fifth side and a sixth side, wherein the first side, the third side, and the side The fifth side is located on the same side of the same side, the fourth side, and the fourth side and the side of the side are on the same plane. The creation uses the silver bump to replace the traditional gold bullion as electricity. Media of sexual connection, which in turn reduces production costs and High-product competitiveness. 5 M352128 [Embodiment] Referring to FIG. 1 , a semiconductor structure having silver bumps is disclosed in a specific embodiment of the present invention, which mainly includes a semiconductor device 110 and a first a base metal layer 120, a second base metal layer 13A, and at least one silver bump 40'. The semiconductor device has at least one pad 1 11 and a protective layer 1丨2, in this embodiment. The semiconductor device 110 can be a germanium wafer or a germanium wafer. The protective layer 112 has at least one opening 113 to expose the solder pad 111. The first base metal layer 2 is formed on the solder. The first base metal layer 120 has a first side surface 1 1 1 and a second side surface 22, and in the embodiment, the first base metal layer 120 is made of titanium tungsten. A second base metal layer 13 is formed on the first base metal layer 120. The second base metal layer 13 has a second side surface 133 and a fourth side surface 133. In this embodiment, The material of the second base metal layer 丨30 is gold, and the silver bump 丨4〇 Formed on the second base metal layer 130, the silver bump 14 has a fifth side 141 and a sixth side 142, wherein the first side m, the first side 1-3 and the fifth The side surface 1 4 1 is located on the same plane, and the second side surface 122, the fourth side surface 1S2 and the sixth side surface μ are located on the same plane. Further, please refer to FIG. 2, in the embodiment, the silver bump The first bump portion 143 has a first width w 1 and the second bump portion 144 has a first width w 1 . a second width W2 and the first width W1 is greater than the second width w 2 '. The opening 1 1 3 of the protective layer 1 1 2 has a third width W 3, 6; M352128 the silver bump 1 40 The first width W 1 is greater than the third width. The second width W2 of the silver bumps 140 is not greater than the third. The solder pad 111 has a fourth width W4. The width is greater than the first width W 1 . This creation uses the medium of the silver bumps 140 to replace the traditional method of using gold bumps as an electrical connection to achieve the goal of reducing production costs and improving product competitiveness. Please refer to Figures 3A to 3L. A schematic cross-sectional view of the process having the structure of the silver bumps. First, please refer to the semiconductor device 110 of FIG. 3A. The semiconductor device 110 can be selected from a silicon wafer, and the semiconductor device 110 has at least one solder. Pad protection layer 1 1 2, the protective layer 1 1 2 has at least one opening 1 ] The pad 1 1 1 , then, referring to FIG. 3B , sputtering forms a layer 12 〇 ' on the pad 111 and the protection On the layer 112, the material of the first metal layer 120 is titanium tungsten, and then, the sputtering layer forms a second metal layer 130, and the first metal layer φ is in the present embodiment. The second metal layer 13 〇 is made of gold. Please refer to FIG. 3D, and apply a photoresist layer 200 on the second gold. Next, please refer to FIG. 3E, and set a mask 300 to 2 After 00', please refer to Figure 3f, exposing and developing the photoresist to form the photoresist layer 2 at least Slot 2 1 〇 ' Next, in the 3G diagram, the trench 210 of the photoresist layer 200 is cleaned by plasma, leaving the photoresist layer 200. Thereafter, please refer to FIG. 3H, and the electric 140' is in the slot 210. Next, referring to FIG. 31, the layer 2 is patterned to form at least one silver bump 14 on the second metal layer L W3, and the L degree W3, the degree W4 is a semiconductor of the electrical medium. The picture is provided on the germanium wafers 1 1 1 and a 13 to expose the first metal embodiment, and the third layer 120, upper, and then, the layer 130' of the photoresist layer 20 0 is referred to to remove the residual After removing the photoresist 130, the upper layer, and the M352128, refer to the third J diagram, and again clean the surface of the silver bump second metal layer 130' to remove the residual photoresist layer. Referring to FIG. 3K, the silver bumps 140 are masked: • a metal layer 1 20 ′ and the second metal layer 1 30 0 ′ such that the silver bumps are formed with a first base metal layer 120 . And a second base metal, the first base metal layer 120 has a first side surface 121 and a surface 122, and the second base metal layer 130 has a third a fourth side surface 132, the silver bump 140 has a fifth side stomach and a sixth side surface 142, wherein the first side surface 121, the third side surface, and the fifth side surface 141 are located in the same Plane, the second side fourth side surface 133 and the sixth side surface 142 are located on the same plane. Referring to FIG. 3L, the silver bump 144 is toughened and formed with a semiconductor structure 1 〇〇, and finally, Shipment to the client after the shipping inspection step. The scope of protection of this creation is subject to the scope of patent application φ attached to it, and any changes and modifications made by those who are familiar with the art without departing from the scope of this creation are the guarantee of this creation. 1 is a cross-sectional view of a semiconductor structure of a bump according to a specific embodiment of the present invention. FIG. 2 is a partial enlarged view of a semiconductor structure of the block according to an embodiment of the present invention. 3A to 3L: According to a specific embodiment of the present invention, a cross section of the process of the semiconductor structure of the block shows 140 and 200, and the first 140 lower layer 130 and a second side 1 are engraved 3 1 and surface 141 and side 1 3 1 122, this. After that, the silver bumps can be packaged to define the spirit and scope of the protection. The species has a silver 〇 with a silver convex with a silver convex intent. 8 M352128 [Description of main components] 100 semiconductor structure with silver bumps 110 Semiconductor device 111 Solder pad 112 Protective layer 113 Open a 120 First base metal layer 1205 First metal layer 121 First side 122 First _ Side 130 Two base metal layers 1 305 second metal layer 13 1 second side 132 fourth side 140 silver bump 140, silver layer 141 fifth side 142 sixth side 143 first 'bump portion 144 first - bump portion 200 photoresist Layer 210 Slot 300 Mask W1 First Width W2 First - Width W3 Second Width W4 Fourth Width

Claims (1)

M352128 九、申請專利範圍· 1、 一種具有銀凸塊之半導體結構,其係包含: • 一半導體裝置,其係具有至少一銲墊及一保護層,該 保護層係具有至少一開口以顯露該銲墊; 一第一基底金屬層,其係形成於該銲墊上,該第一基 底金屬層係具有一第一侧面及一第二側面; ' 一第二基底金屬層,其係形成於該第一基底金屬層 . 上,該第二基底金屬層係具有一第三側面及一第四側 ® 面;以及 至少一銀凸塊,其係形成於該第二基底金屬層上,該 銀凸塊係具有一第五側面及一第六側面,其中該第一 侧面、該第三侧面及該第五側面係位於同一平面,該 第二側面、該第四侧面及該第六側面係位於同一平面。 2、 如申請專利範-圍第1項所述之具有銀凸塊之半導體結 構,其中該銀凸塊係包含有一第一凸塊部及一第二凸 I 塊部,該第一凸塊部係具有一第一寬度,該第二凸塊 部係具有一第二寬度且該第一寬度係大於該第二寬 度。 3、 如申請專利範圍第2項所述之具有銀凸塊之半導體結 構,其中該保護層之該開口係具有一第三寬度,該銀 凸塊之該第一寬度係大於該第三寬度。 4、 如申請專利範圍第2項所述之具有銀凸塊之半導體結 構,其中該保護層之該開口係具有一第三寬度,該銀 凸塊之該第二寬度係不大於該第三寬度。 10 M352128 5、 如申請專利範圍第2項所述之具有銀凸塊之半導體結 構,其中該銲墊係具有一第四寬度,該第四寬度係大 於該第一寬度。 6、 如申請專利範圍第1項所述之具有銀凸塊之半導體結 構,其中該第一基底金屬層之材質係為鈦鎢,該第二 基底金屬層之材質係為金。 7、 如申請專利範圍第1項所述之具有銀凸塊之.半導體結 構,其中該半導體裝置係為矽晶片或矽晶圓。M352128 IX. Patent Application Range 1. A semiconductor structure having silver bumps, comprising: • a semiconductor device having at least one pad and a protective layer, the protective layer having at least one opening to expose the a first base metal layer having a first side and a second side; and a second base metal layer formed on the first base metal layer a second base metal layer having a third side surface and a fourth side surface; and at least one silver bump formed on the second base metal layer, the silver bump The first side surface, the third side surface and the fifth side surface are located on the same plane, and the second side surface, the fourth side surface and the sixth side surface are located on the same plane. . 2. The semiconductor structure having a silver bump according to the first aspect of the invention, wherein the silver bump comprises a first bump portion and a second bump portion, the first bump portion The first bump has a second width and the first width is greater than the second width. 3. The semiconductor structure having silver bumps according to claim 2, wherein the opening of the protective layer has a third width, and the first width of the silver bump is greater than the third width. 4. The semiconductor structure having silver bumps according to claim 2, wherein the opening of the protective layer has a third width, and the second width of the silver bump is not greater than the third width . The semiconductor structure having silver bumps as described in claim 2, wherein the pad has a fourth width, the fourth width being greater than the first width. 6. The semiconductor structure having silver bumps according to claim 1, wherein the material of the first base metal layer is titanium tungsten, and the material of the second base metal layer is gold. 7. The semiconductor structure having silver bumps as described in claim 1, wherein the semiconductor device is a germanium wafer or a germanium wafer.
TW097218044U 2008-10-08 2008-10-08 Semiconductor structure having silver bump TWM352128U (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
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TWI423410B (en) * 2010-12-31 2014-01-11 Au Optronics Corp Metal conductive structure and manufacturing method
TWI473222B (en) * 2009-10-13 2015-02-11 Chipbond Technology Corp Chip structure having imitation gold bumps
US9230823B1 (en) 2014-08-05 2016-01-05 Chipbond Technology Corporation Method of photoresist strip
TWD195587S (en) 2017-09-27 2019-01-21 日商濱松赫德尼古斯股份有限公司 Part for semiconductor device
TWD195624S (en) 2017-09-27 2019-01-21 日商濱松赫德尼古斯股份有限公司 Part for semiconductor device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI473222B (en) * 2009-10-13 2015-02-11 Chipbond Technology Corp Chip structure having imitation gold bumps
TWI423410B (en) * 2010-12-31 2014-01-11 Au Optronics Corp Metal conductive structure and manufacturing method
US9230823B1 (en) 2014-08-05 2016-01-05 Chipbond Technology Corporation Method of photoresist strip
CN105321807A (en) * 2014-08-05 2016-02-10 颀邦科技股份有限公司 Photoresist Stripping Method
TWI595332B (en) * 2014-08-05 2017-08-11 頎邦科技股份有限公司 Method for photoresist stripping
TWD195587S (en) 2017-09-27 2019-01-21 日商濱松赫德尼古斯股份有限公司 Part for semiconductor device
TWD195624S (en) 2017-09-27 2019-01-21 日商濱松赫德尼古斯股份有限公司 Part for semiconductor device
TWD195586S (en) 2017-09-27 2019-01-21 日商濱松赫德尼古斯股份有限公司 Part for semiconductor device
USD864882S1 (en) 2017-09-27 2019-10-29 Hamamatsu Photonics K.K. Part for semiconductor device
USD864883S1 (en) 2017-09-27 2019-10-29 Hamamatsu Photonics K.K. Part for semiconductor device
USD865690S1 (en) 2017-09-27 2019-11-05 Hamamatsu Photonics K.K. Part for semiconductor device

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