TWI303089B - Flip-chip bonding method - Google Patents

Flip-chip bonding method Download PDF

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Publication number
TWI303089B
TWI303089B TW95124540A TW95124540A TWI303089B TW I303089 B TWI303089 B TW I303089B TW 95124540 A TW95124540 A TW 95124540A TW 95124540 A TW95124540 A TW 95124540A TW I303089 B TWI303089 B TW I303089B
Authority
TW
Taiwan
Prior art keywords
oxide layer
flip chip
layer
substrate
chip bonding
Prior art date
Application number
TW95124540A
Other languages
Chinese (zh)
Other versions
TW200805519A (en
Inventor
Zhi Hui Yang
Chen Chia Li
Yuan Hung Lo
Chin Tsun Feng
Jr Fu Chen
Original Assignee
Int Semiconductor Tech Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Int Semiconductor Tech Ltd filed Critical Int Semiconductor Tech Ltd
Priority to TW95124540A priority Critical patent/TWI303089B/en
Publication of TW200805519A publication Critical patent/TW200805519A/en
Application granted granted Critical
Publication of TWI303089B publication Critical patent/TWI303089B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Wire Bonding (AREA)

Description

• 1303089 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種覆晶接合方法，特別係有關於一 種可提咼晶片與基板接合強度之覆晶接合方法。 【先前技術】 隨著電子產品走向輕薄短小、1/〇數增加及功能提升 之發展趨勢之同時，也開啟覆晶封裝技術的概念，覆晶封 鲁裝技術具有電性佳、尺寸小、散熱佳及高密度等優點，正 符合未來高效能和攜帶式產品之所需。 • 如第1圖所示，其係為一覆晶封裝構造100，該覆晶 . 封裝構造1〇〇係包含有一基板U0、一晶片120及一封膠 體130。該基板110係具有複數個連接墊U1，該些連接 墊111上係形成有一錫層i 12，該晶片120係具有一主動 面121以及形成於該主動面121上之複數個金凸塊122， 將該晶片120覆晶接合於該基板11〇上，使該晶片12〇之 籲㈣金凸塊122接合於該基板110之該錫層n2 ’以達到 電性連接之功能，再以該封膠體130包覆該些金凸塊122 與該錫層112，然而該錫層112上係會形成有—表面氧化 層113，其係為該錫層丨12與空氣接觸所形成之氧化物， 該表面氧化層113係存在於該些金凸塊122與該錫層ιΐ2 之間，使得該些金凸塊122與該錫層112之接合不完全或 導致無法電性連接，使得該覆晶封裝結構1〇〇電性短路。 【發明内容】 本發明之主要目的係在於提供一種覆晶接合方法，一 1303089 基板之複數個連接墊上係形成有—錫層，該錫層係具有一 表面氧化層’藉由一氧化層去除膠覆蓋於該錫層之該表面 氧化層’以去除該表面氧化層，使得_晶片之複數個金凸 塊直接接合於該基板之該錫層，進而提高該些金凸塊與該 錫層間之接合強度。 本發明之次-目的係在於提供—種覆晶接合方法，其BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip chip bonding method, and more particularly to a flip chip bonding method capable of improving bonding strength between a wafer and a substrate. [Prior Art] With the development trend of electronic products going to be thin and light, 1/〇 increase and function enhancement, the concept of flip chip packaging technology is also opened. The flip chip sealing technology has good electrical properties, small size and heat dissipation. The advantages of good and high density are in line with the needs of future high performance and portable products. • As shown in Fig. 1, it is a flip chip package structure 100, which is a flip chip. The package structure 1 includes a substrate U0, a wafer 120, and a paste 130. The substrate 110 has a plurality of connection pads U1. The connection pads 111 are formed with a tin layer i12. The wafer 120 has an active surface 121 and a plurality of gold bumps 122 formed on the active surface 121. The wafer 120 is flip-chip bonded onto the substrate 11 , so that the silicon bumps 122 of the wafer 12 are bonded to the tin layer n2 ′ of the substrate 110 to achieve the function of electrical connection, and the encapsulant is further The gold bumps 122 are coated with the tin layer 112, but the tin layer 112 is formed with a surface oxide layer 113, which is an oxide formed by the tin layer 12 in contact with air. The oxide layer 113 is present between the gold bumps 122 and the tin layer ι 2, such that the gold bumps 122 are not completely bonded to the tin layer 112 or cause electrical connection, such that the flip chip package structure 1 〇〇 Electrical short circuit. SUMMARY OF THE INVENTION The main object of the present invention is to provide a flip chip bonding method in which a plurality of connection pads of a 1303089 substrate are formed with a tin layer having a surface oxide layer to remove glue by an oxide layer. Covering the surface oxide layer of the tin layer to remove the surface oxide layer, so that a plurality of gold bumps of the _ wafer are directly bonded to the tin layer of the substrate, thereby improving bonding between the gold bumps and the tin layer strength. The second objective of the present invention is to provide a flip chip bonding method, which

中該晶片與該基板係制超音波鍵結法接合，其係具有降 低成本與改進製程技術之功效。 依據本發明，-種覆晶接合方法：首先，提供一基板 該基板係具有複數個連接墊’該些連接墊上係形成有一録 層’且該錫層係具有-表面氧化層；接著，覆蓋一氧化層 去除膠於該錫層之該表面氧化層±，其中該氧化層去除锻 係用以去除該氧化層；最後，覆晶接合―晶片於該基板: 亥晶片之複數個金凸塊係直接接合於該錫層。 【實施方式】 请參閱第2A i 2D圖，其係為本發明之—具體實施 例，其係揭示一種覆晶接合方法，首先，請先參閱第2A 圖，提供一基板210，該基板21〇之一上表面211係具有 複數個連接墊212 ,在本實施例中，該基板21〇係可為一 PUpolyimide)基板，該些連接墊212上係形成有一錫層 213，該些連接墊212之材質係為銅，該錫層213係具有 一表面氧化層214，該表面氧化層214係為該錫層213與 空氣接觸後所生成。接著，請參閱第2B圖，覆蓋_氧化 層去除膠220於該錫層213之該表面氧化層214上，該氧 1303089 在不脫離本發明之精神和 ，均屬於本發明之保護範 :為準，任何熟知此項技藝者， 觀圍内所作之任何變化與修改 圍0 【圖式簡單說明】 第 1 圖·習知覆晶接合封裝構造之截面示意圖。 2A至2D圖·依據本發明之一具體實施例，一種利用氧 化層去除膠以提高晶片與基板間之覆晶 # 接合方法之截面示意圖。 圖·依據本發明之一具體實施例，氧化層去除 膠覆蓋於基板之上視圖。 【主要元件符號說明】 1 〇〇覆晶封裝構造 110基板 113表面氧化層 122金凸塊 210基板 213錫層. 111連接墊 12 0晶片 130封膠體 211上表面 214表面氧化層 231主動面 112錫層 121主動面 2 3 0晶片 A 氧化層去除膠覆蓋區 212連接墊 220氧化層去除膠 232金凸塊 B 覆晶區 8The wafer is bonded to the substrate by ultrasonic bonding, which has the effect of reducing cost and improving process technology. According to the present invention, a flip chip bonding method: first, providing a substrate having a plurality of connection pads, wherein the connection pads are formed with a recording layer and the tin layer has a surface oxide layer; The oxide layer removes the surface oxide layer of the tin layer, wherein the oxide layer removes the forging layer to remove the oxide layer; finally, the flip chip bonds the wafer to the substrate: the plurality of gold bumps of the wafer are directly Bonded to the tin layer. [Embodiment] Please refer to FIG. 2A i 2D, which is a specific embodiment of the present invention, which discloses a flip chip bonding method. First, please refer to FIG. 2A to provide a substrate 210. The upper surface 211 has a plurality of connection pads 212. In this embodiment, the substrate 21 can be a PU polyimide substrate, and the connection pads 212 are formed with a tin layer 213. The connection pads 212 are formed. The material is copper, and the tin layer 213 has a surface oxide layer 214 which is formed after the tin layer 213 is in contact with air. Next, referring to FIG. 2B, the cover oxide layer is removed from the surface oxide layer 214 of the tin layer 213. The oxygen 1303089 belongs to the protection of the present invention without departing from the spirit of the present invention. Anyone who is familiar with the art, any changes and modifications made in the viewing area 0 [Simplified description of the drawing] Fig. 1 is a schematic cross-sectional view of a conventional flip chip bonding package structure. 2A to 2D. According to an embodiment of the present invention, a cross-sectional view of a method of removing a paste by using an oxide layer to improve a flip chip bonding between a wafer and a substrate. BRIEF DESCRIPTION OF THE DRAWINGS In accordance with one embodiment of the present invention, an oxide layer is removed from a substrate overlying a view. [Main component symbol description] 1 〇〇 flip chip package structure 110 substrate 113 surface oxide layer 122 gold bump 210 substrate 213 tin layer. 111 connection pad 12 0 wafer 130 encapsulant 211 upper surface 214 surface oxide layer 231 active surface 112 tin Layer 121 active surface 2 3 0 wafer A oxide layer removal adhesive coverage area 212 connection pad 220 oxide layer removal glue 232 gold bump B flip chip area 8

Claims (1)

1303089 案號 95124540 *TTi»auar,'r^*^'_丨樵m t ·..-l··^ .-: /、λ;:-:'· 年.月 曰 :|-(^正.換>” ------------------------- 、申請專利範圍： 、一種覆晶接合方法，包含·· ^fit ,Ljg 、土攸，该基板係具有複數個連接墊，該些連接 墊上係形成有_錫層，該錫層係具有一表面氧化層； 1蓋氧化層去除膠於該錫層之該表面氧化層上，其 S ^亥氧化層去除膠係、用以去除該氧化層；以及 =曰曰接合―晶片於該基板，該晶片係具有-主動面及 複數個金凸塊，該些金凸塊係直接接合該基板之該錫 層。 2 如申睛專利範圍第1項所述之覆晶接合方法，直中該 晶片與該基板之接合係利用超音波鍵結法。 4 士申明專利耗圍第！項所述之覆晶接合方法，其中該 氧化層去除膠係以點塗或印刷方式覆蓋於該錫層。 申請專利範圍第1項所述之覆晶接合方法，其中該 氧化層去除膠覆蓋於該表面氧化層之區域係大於該 曰曰片之覆晶區域。 如申請專利範圍第上項所述之覆晶接合方法，盆中該 氧化層去除膠係為非導電膠（N〇n_c〇nductive ΜΑ NCP) 〇 ^申請專利範圍第1項所述之覆晶接合方法，其中該 乳化層去除膠係包含有松香、#機③、有機酸、無機 酸等活化劑。 61303089 Case No. 95124540 *TTi»auar, 'r^*^'_丨樵mt ·..-l··^ .-: /, λ;:-:'· Year. Month:|-(^正. Change >" -------------------------, the scope of application for patents: a method of flip chip bonding, including ·· ^fit , Ljg , soil The substrate has a plurality of connection pads, the connection pads are formed with a tin layer, the tin layer has a surface oxide layer, and the cover oxide layer removes the glue on the surface oxide layer of the tin layer. a coating layer for removing the oxide layer, and a bonding layer for the wafer, the wafer having an active surface and a plurality of gold bumps directly bonded to the substrate The tin layer of the substrate. 2 The method of flip chip bonding according to the first aspect of the patent application, the bonding of the wafer to the substrate is by ultrasonic bonding. The flip chip bonding method, wherein the oxide layer removing glue is applied to the tin layer by spot coating or printing. The flip chip bonding method according to claim 1, wherein the oxide layer removes the glue covering The region of the surface oxide layer is larger than the flip chip region of the enamel sheet. The flip chip bonding method according to the above claim, wherein the oxide layer removes the glue system as a non-conductive glue (N〇n_c〇nductive ΜΑ The flip chip bonding method according to claim 1, wherein the emulsion layer removing adhesive comprises an activator such as rosin, #3, organic acid, or inorganic acid.
TW95124540A 2006-07-05 2006-07-05 Flip-chip bonding method TWI303089B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW95124540A TWI303089B (en) 2006-07-05 2006-07-05 Flip-chip bonding method

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Application Number Priority Date Filing Date Title
TW95124540A TWI303089B (en) 2006-07-05 2006-07-05 Flip-chip bonding method

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TW200805519A TW200805519A (en) 2008-01-16
TWI303089B true TWI303089B (en) 2008-11-11

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