JP5296590B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
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- JP5296590B2 JP5296590B2 JP2009081922A JP2009081922A JP5296590B2 JP 5296590 B2 JP5296590 B2 JP 5296590B2 JP 2009081922 A JP2009081922 A JP 2009081922A JP 2009081922 A JP2009081922 A JP 2009081922A JP 5296590 B2 JP5296590 B2 JP 5296590B2
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- 239000004065 semiconductor Substances 0.000 title claims description 78
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 229910000679 solder Inorganic materials 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 25
- 239000011347 resin Substances 0.000 claims description 21
- 229920005989 resin Polymers 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000007788 roughening Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 70
- 239000010949 copper Substances 0.000 description 13
- 230000005012 migration Effects 0.000 description 12
- 238000013508 migration Methods 0.000 description 12
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000000243 solution Substances 0.000 description 6
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 238000007639 printing Methods 0.000 description 3
- 239000007921 spray Substances 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 229910001431 copper ion Inorganic materials 0.000 description 2
- BDAGIHXWWSANSR-UHFFFAOYSA-N methanoic acid Natural products OC=O BDAGIHXWWSANSR-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- OSWFIVFLDKOXQC-UHFFFAOYSA-N 4-(3-methoxyphenyl)aniline Chemical compound COC1=CC=CC(C=2C=CC(N)=CC=2)=C1 OSWFIVFLDKOXQC-UHFFFAOYSA-N 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 235000019253 formic acid Nutrition 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- QAOWNCQODCNURD-UHFFFAOYSA-M hydrogensulfate Chemical compound OS([O-])(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-M 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000003999 initiator Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- UKLNMMHNWFDKNT-UHFFFAOYSA-M sodium chlorite Chemical compound [Na+].[O-]Cl=O UKLNMMHNWFDKNT-UHFFFAOYSA-M 0.000 description 1
- 229960002218 sodium chlorite Drugs 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0175—Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/099—Coating over pads, e.g. solder resist partly over pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0577—Double layer of resist having the same pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本実施形態における半導体パッケージの製造方法について、図1〜図6を参照して説明する。図7に示すように、最終形態として半導体パッケージ20は、例えば、コアとなるプリント基板(基板1S)と、その基板1Sの両面に形成されたビルドアップ樹脂層1と、そのビルドアップ樹脂層1に形成された配線2とを有して構成される。
本実施形態における半導体パッケージの製造方法について、図10〜図12を参照して説明する。なお、前記実施形態1と重複する説明は省略する場合がある。
本実施形態における半導体パッケージの製造方法について、図13〜図15を参照して説明する。なお、前記実施形態1、2と重複する説明は省略する場合がある。
1S 基板
2 配線
2a 電極パッド
4 レジスト膜
5 無機絶縁膜
5a 開口部(第1開口部)
6 ソルダレジスト層
6a 開口部(第2開口部)
7、7a、7b 電極バンプ
8 UBM膜
9 レジスト膜
9a 開口部
20 半導体パッケージ
21 スルーホール
22 電極ピン
30 半導体チップ
31 電極バンプ
32 アンダーフィル樹脂
101 ビルドアップ樹脂層
102 配線
102a 電極パッド
103 ソルダレジスト層
104 電極バンプ
Claims (8)
- 以下の工程を含む半導体パッケージの製造方法:
(a)電極パッドを有する配線が形成された基板を準備する工程;
(b)前記電極パッド上にレジスト膜を設ける工程;
(c)前記(b)工程後に、前記配線および前記レジスト膜を覆うように前記基板上に無機絶縁膜を形成した後、前記レジスト膜を除去することによって、前記レジスト膜上の前記無機絶縁膜を除去し、前記無機絶縁膜から前記電極パッドを露出する工程;
(d)前記(c)工程後に、前記無機絶縁膜上に、前記電極パッドを露出するソルダレジスト層を形成する工程。 - 更に以下の工程を含む請求項1記載の半導体パッケージの製造方法:
(e)前記(a)工程後、前記(b)工程前に、前記配線に粗化処理を施す工程。 - 請求項1または2記載の半導体パッケージの製造方法において、
前記(b)工程では、前記電極パッド上の一部に前記レジスト膜を設け、
前記(c)工程では、前記電極パッドを露出する第1開口部を前記無機絶縁膜に形成し、
前記(d)工程では、前記電極パッドを露出し、前記第1開口部より小さい開口の第2開口部を前記ソルダレジスト層に形成する。 - 請求項1または2記載の半導体パッケージの製造方法において、
前記(b)工程では、前記電極パッド上の一部に前記レジスト膜を設け、
前記(c)工程では、前記電極パッドを露出する第1開口部を前記無機絶縁膜に形成し、
前記(d)工程では、前記電極パッドを露出し、前記第1開口部より大きい開口の第2開口部を前記ソルダレジスト層に形成する。 - 請求項1〜4のいずれか一項に記載の半導体パッケージの製造方法において、
前記(c)工程では、前記無機絶縁膜として、酸化シリコン膜または窒化シリコン膜を形成する。 - 請求項1〜5のいずれか一項に記載の半導体パッケージの製造方法において、
前記(d)工程では、樹脂からなる前記ソルダレジスト層を形成する。 - 更に以下の工程を含む請求項1〜6のいずれか一項に記載の半導体パッケージの製造方法:
(f)前記(d)工程後に、前記電極パッドと電気的に接続される外部電極を形成する工程。 - 請求項7記載の半導体パッケージの製造方法において、
前記(f)工程では、前記外部電極として、半田バンプを形成する。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009081922A JP5296590B2 (ja) | 2009-03-30 | 2009-03-30 | 半導体パッケージの製造方法 |
US12/749,117 US8288875B2 (en) | 2009-03-30 | 2010-03-29 | Method of manufacturing a semiconductor package and semiconductor package having an electrode pad with a small pitch |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009081922A JP5296590B2 (ja) | 2009-03-30 | 2009-03-30 | 半導体パッケージの製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013022824A Division JP5633095B2 (ja) | 2013-02-08 | 2013-02-08 | 半導体パッケージの製造方法および半導体パッケージ |
Publications (3)
Publication Number | Publication Date |
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JP2010238702A JP2010238702A (ja) | 2010-10-21 |
JP2010238702A5 JP2010238702A5 (ja) | 2012-03-15 |
JP5296590B2 true JP5296590B2 (ja) | 2013-09-25 |
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Application Number | Title | Priority Date | Filing Date |
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JP2009081922A Active JP5296590B2 (ja) | 2009-03-30 | 2009-03-30 | 半導体パッケージの製造方法 |
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US (1) | US8288875B2 (ja) |
JP (1) | JP5296590B2 (ja) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
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KR101767108B1 (ko) * | 2010-12-15 | 2017-08-11 | 삼성전자주식회사 | 하이브리드 기판을 구비하는 반도체 패키지 및 그 제조방법 |
US20140318831A1 (en) * | 2011-12-12 | 2014-10-30 | Mitsubishi Materials Corporation | Power module substrate, power module substrate with heat sink, power module, paste for forming flux component intrusion-preventing layer and method for bonding bonded body |
US9224674B2 (en) * | 2011-12-15 | 2015-12-29 | Intel Corporation | Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages |
US8653662B2 (en) * | 2012-05-02 | 2014-02-18 | International Business Machines Corporation | Structure for monitoring stress induced failures in interlevel dielectric layers of solder bump integrated circuits |
KR101921258B1 (ko) * | 2012-05-09 | 2018-11-22 | 삼성전자주식회사 | 배선 기판 및 이를 포함하는 반도체 패키지 |
US9646928B2 (en) * | 2014-03-13 | 2017-05-09 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement and formation thereof |
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