JP5599276B2 - 半導体素子、半導体素子実装体及び半導体素子の製造方法 - Google Patents
半導体素子、半導体素子実装体及び半導体素子の製造方法 Download PDFInfo
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- JP5599276B2 JP5599276B2 JP2010213688A JP2010213688A JP5599276B2 JP 5599276 B2 JP5599276 B2 JP 5599276B2 JP 2010213688 A JP2010213688 A JP 2010213688A JP 2010213688 A JP2010213688 A JP 2010213688A JP 5599276 B2 JP5599276 B2 JP 5599276B2
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- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 238000007796 conventional method Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
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- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
- KERTUBUCQCSNJU-UHFFFAOYSA-L nickel(2+);disulfamate Chemical compound [Ni+2].NS([O-])(=O)=O.NS([O-])(=O)=O KERTUBUCQCSNJU-UHFFFAOYSA-L 0.000 description 1
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Description
図1(a)は実施形態に係る半導体素子(チップ)を配線基板にフリップチップ実装したときの状態を断面図の形態で示したものであり、図1(b)は比較例としての実装状態を断面図の形態で示したものである。
上述した第1の実施形態では、Cuポスト15の形成に際し(図3(c)参照)、導体層15Aの上面の周囲部分を選択エッチングするのに用いるレジスト層32Aを構成する耐エッチング材料として有機材料(感光性ドライフィルム等)を使用した場合を例にとって説明したが、エッチングレジストの材料がこれに限定されないことはもちろんである。この第2の実施形態では、耐エッチング材料として金属材料を使用している。
上述した第1、第2の実施形態では、Cuポスト15の先端部分をテーパ状に形成するために(図3(c)、図4(d)参照)、導体層15Aの上面の周囲部分のみが露出するようにパターニングされたエッチングレジスト(レジスト層32A、金属層34)を使用した場合を例にとって説明したが、Cuポスト15の先端部分をテーパ状に形成するための手段がこれに限定されないことはもちろんである。この第3の実施形態では、Cuポスト15の先端部分をテーパ状に形成するために、導体層15Aの周囲のレジスト層31の厚さを減じて導体層15Aの上面近傍の側面部分を露出させ、この露出した部分に選択エッチングを施している。
以下、第4の実施形態に係るプロセス(半導体素子の製造方法)について、その製造工程の一部を示す図6を参照しながら説明する。
図7は、Cuポスト15に表面処理を施す場合の一実施形態に係る工程を断面図の形態で示したものである。この実施形態で行う表面処理は、第1の実施形態(図3)に適用することができる。
11(11A)…半導体基板(シリコンウエハ)、
12,22…パッド、
13,23…保護膜(パッシベーション膜、ソルダレジスト層)、
14…シード層(バリヤメタル層)、
15…Cuポスト(柱状の接続端子)、
15a…(Cuポストの)先端、
15b…(Cuポストの)テーパ状に形成された側面、
17,18…めっき層(金属層)、
20…配線基板、
25…はんだ、
31,31A,32A…レジスト層(マスク)、
33…リフトオフ用のレジスト層、
34,35A,36…金属層(マスク)、
50…半導体素子実装体。
Claims (10)
- 柱状の接続端子を備えた半導体素子であって、
前記接続端子の先端側の側面において、前記接続端子の横断面積が前記先端側になるにつれて徐々に減小する形状であり、かつ、前記接続端子の先端側の側面の全体が内側にへこむ曲面になって形成されており、
前記接続端子の先端側の側面に金属めっき層が形成されており、前記接続端子の基部側の側面は前記金属めっき層から露出していることを特徴とする半導体素子。 - 前記接続端子の形状は、前記先端の近傍部分を除いて円柱状であることを特徴とする請求項1に記載の半導体素子。
- 前記接続端子は、銅めっきから形成されることを特徴とする請求項1又は2に記載の半導体素子。
- さらに前記接続端子の先端の表面に、金属めっき層が形成されていることを特徴とする請求項1又は2に記載の半導体素子。
- 請求項1から4のいずれか一項に記載の半導体素子が、前記接続端子を介して配線基板上に実装されていることを特徴とする半導体素子実装体。
- 柱状の接続端子を有する半導体素子の製造方法であって、
半導体基板上に開口部を有する第1のマスクを形成する工程と、
めっきにより前記開口部内を充填して前記半導体基板のパッド上に柱状の導体層を形成する工程と、
前記導体層上に、該導体層の上面の周囲部分及び上面近傍の側面部分の少なくとも一方を露出させた第2のマスクを形成する工程と、
前記導体層の前記第2のマスクからの露出部分をウェットエッチングより選択的に除去して、前記導体層の先端側の側面を、前記導体層の横断面積が先端側になるにつれて徐々に減小する形状で、かつ、前記導体層の先端側の側面の全体が内側にへこむ曲面に形成する工程と、
前記導体層の先端側の側面に金属めっき層を形成する工程と、
前記第1のマスク及び前記第2のマスクを除去する工程とを含むことを特徴とする半導体素子の製造方法。 - 前記第2のマスクを形成する工程は、
前記第1のマスク上及び前記導体層上に、該導体層の上面において当該導体層の横断面形状よりも小さい形状の開口部を有するリフトオフ用のレジスト層を形成する工程と、
前記導体層上及び前記リフトオフ用のレジスト層上に、マスク用の金属層を形成する工程と、
前記リフトオフ用のレジスト層をその表面に形成された金属層と共に除去する工程とを含むことを特徴とする請求項6に記載の半導体素子の製造方法。 - 前記第2のマスクを形成する工程は、
前記導体層上にマスク用の金属層を形成する工程と、
前記金属層から露出している前記第1のマスクの上層部分を除去する工程とを含むことを特徴とする請求項6に記載の半導体素子の製造方法。 - 前記開口部内を充填して前記柱状の導体層を形成後、当該導体層の表面を研削する工程を含むことを特徴とする請求項6に記載の半導体素子の製造方法。
- 前記第1のマスクはレジスト層であり、前記第2のマスクは金属層であり、
前記金属めっき層を形成する工程と、前記第1のマスク及び前記第2のマスクを除去する工程とに代えて、
前記第2のマスクを選択的に除去する工程と、
前記接続端子の側面及び先端面に金属めっき層を形成する工程と、
前記第1のマスクを除去する工程とを有することを特徴とする請求項7に記載の半導体素子の製造方法。
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US10833033B2 (en) * | 2011-07-27 | 2020-11-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bump structure having a side recess and semiconductor structure including the same |
US9013037B2 (en) * | 2011-09-14 | 2015-04-21 | Stmicroelectronics Pte Ltd. | Semiconductor package with improved pillar bump process and structure |
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US9324557B2 (en) * | 2014-03-14 | 2016-04-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method for fabricating equal height metal pillars of different diameters |
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