JP2012074406A - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
JP2012074406A
JP2012074406A JP2010212184A JP2010212184A JP2012074406A JP 2012074406 A JP2012074406 A JP 2012074406A JP 2010212184 A JP2010212184 A JP 2010212184A JP 2010212184 A JP2010212184 A JP 2010212184A JP 2012074406 A JP2012074406 A JP 2012074406A
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Japan
Prior art keywords
metal film
resist
film
rewiring
forming
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JP2010212184A
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Inventor
Tatsuo Uda
達夫 右田
Hirokazu Ezawa
弘和 江澤
Soichi Yamashita
創一 山下
Kimiro Nagamine
公朗 永嶺
Masahiro Miyata
雅弘 宮田
Tatsuo Shiotsuki
竜夫 塩月
Kiyoshi Muranishi
清 村西
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Toshiba Corp
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Toshiba Corp
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Priority to JP2010212184A priority Critical patent/JP2012074406A/ja
Priority to TW100128421A priority patent/TWI453806B/zh
Priority to CN201110256133.1A priority patent/CN102386160B/zh
Priority to US13/224,787 priority patent/US8704367B2/en
Publication of JP2012074406A publication Critical patent/JP2012074406A/ja
Pending legal-status Critical Current

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Abstract

【課題】再配線のパターン形成後のレジストパターンの剥離性を確保しつつ、再配線のパターン形成前のレジストパターンとその下地との密着性を向上させる。
【解決手段】半導体チップ上に形成されたメタル膜５の表層には、レジスト膜６との密着性を上げる表面改質層１６が形成され、表面改質層１６を介してメタル膜５上に再配線７ａ〜７ｃが形成される。
【選択図】 図９

Description

本発明の実施形態は半導体装置および半導体装置の製造方法に関する。
半導体デバイスの高集積化と高機能化を達成するために、動作速度の向上やメモリの大容量化が要求されている。それに合わせて半導体基板上の再配線形成プロセスにおいても、１０ｕｍピッチ以下の微細な再配線が要求されている。
再配線のピッチが微細化されると、再配線をパターン形成するためのレジストパターンとその下地との密着性が低下し、レジスト現像時などにレジスト剥がれを引き起こすことがあった。
特開２００７−１０３７１６号公報
本発明の一つの実施形態の目的は、再配線のパターン形成後のレジストパターンの剥離性を確保しつつ、再配線のパターン形成前のレジストパターンとその下地との密着性を向上させることが可能な半導体装置および半導体装置の製造方法を提供することである。
実施形態の半導体装置によれば、半導体基板と、メタル膜と、表面改質層と、再配線とが設けられている。半導体基板は、配線およびパッド電極が形成されている。メタル膜は、前記半導体基板上に形成されている。表面改質層は、前記メタル膜の表層に形成され、レジストパターンとの密着性を上げる。再配線は、前記表面改質層を介して前記メタル膜上に形成されている。
図１（ａ）〜（ｅ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図２（ａ）〜（ｄ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図３（ａ）〜（ｃ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図４（ａ）〜（ｂ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図５（ａ）〜（ｂ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図６（ａ）〜（ｂ）は、第１実施形態に係る半導体装置の製造方法を示す断面図である。 図７は、第１実施形態に係る吸光度の異なるレジストＡ、Ｂの表面と下面との露光量の関係を示す図である。 図８（ａ）〜（ｅ）は、第３実施形態に係る半導体装置の製造方法を示す断面図である。 図９（ａ）〜（ｄ）は、第３実施形態に係る半導体装置の製造方法を示す断面図である。 図１０（ａ）〜（ｃ）は、第３実施形態に係る半導体装置の製造方法を示す断面図である。 図１１（ａ）〜（ｂ）は、第３実施形態に係る半導体装置の製造方法を示す断面図である。 図１２（ａ）〜（ｂ）は、第３実施形態に係る半導体装置の製造方法を示す断面図である。 図１３（ａ）〜（ｂ）は、第３実施形態に係る半導体装置の製造方法を示す断面図である。
以下、実施形態に係る半導体装置および半導体装置の製造方法について図面を参照しながら説明する。なお、これらの実施形態により本発明が限定されるものではない。
（第１実施形態）
図１〜図６は、第１実施形態に係る半導体装置の製造方法を示す断面図である。
図１（ａ）において、基材層１上には、パッド電極２ａおよび配線２ｂが形成されるとともに、パッド電極２ａおよび配線２ｂが覆われるようにして保護膜３が形成されている。また、保護膜３には、パッド電極２ａを露出させる開口部３ａおよび配線２ｂの一部を露出させる開口部３ｂが形成されている。
なお、基材層１としては、例えば、ロジック回路またはＤＲＡＭなどの集積回路が形成された半導体基板を用いることができる。また、パッド電極２ａおよび配線２ｂの材料は、例えば、ＡｌまたはＡｌを主成分とした金属を用いることができる。また、保護膜３の材料は、例えば、シリコン酸化膜またはシリコン酸窒化膜またはシリコン窒化膜などの絶縁体を用いることができる。
次に、図１（ｂ）に示すように、感光性樹脂などを保護膜３上に塗布することにより、保護膜３上に緩衝層４を形成する。なお、緩衝層４の材料としては、例えば、ポリイミド系樹脂を用いることができる。ウェハストレスを低減させるために、ポリイミド系樹脂よりも硬化温度の低いアクリル系樹脂またはフェノール系樹脂を用いるようにしてもよい。
次に、図１（ｃ）に示すように、フォトリソグラフィー技術を用いることにより、パッド電極２ａおよび配線２ｂの一部をそれぞれ露出させる開口部４ａ、４ｂを緩衝層４に形成する。
次に、図１（ｄ）に示すように、スパッタ、メッキ、ＣＶＤ、ＡＬＤまたは蒸着などの方法を用いることにより、パッド電極２ａ、配線２ｂ、保護膜３および緩衝層４上にメタル膜５を形成する。なお、メタル膜５としては、例えば、Ｔｉと、その上のＣｕとの積層構造を用いることができる。なお、Ｔｉの代わりに、ＴｉＮ、ＴｉＷ、Ｗ、Ｔａ、Ｃｒ、Ｃｏ等の材料を使用することもできる。Ｃｕの代わりに、Ａｌ、Ｐｄ、Ａｕ、Ａｇ等の材料を使用することもできる。
次に、図１（ｅ）に示すように、スピンコートなどの方法を用いることにより、メタル膜５上にレジスト膜６を形成する。なお、レジスト膜６は、メタル膜５との界面（以下、下地界面と称す）まで届く光に対して吸光度が８０％以下に設定されている。尚、本発明の吸光度は、ｉ線波長（３６５ｎｍ）の露光装置を用いて測定した値とする。また、レジスト膜６の膜厚は１〜５０μｍの範囲内に設定することができる。
次に、図２（ａ）に示すように、レジスト膜６の露光および現像を行うことにより、開口部６ａ〜６ｃをレジスト膜６に形成する。なお、開口部６ａは、パッド電極２ａ上に配置し、開口部６ｂは、緩衝層４上に配置し、開口部６ｃは、配線２ｂ上に配置することができる。なお、開口部６ｂが形成されたレジスト膜６の幅は２０μｍ以下とすることができる。
次に、図２（ｂ）に示すように、電解メッキにて第１の導体を開口部６ａ〜６ｃに埋め込むことにより、メタル膜５を介してパッド電極２ａ、緩衝層４および配線２ｂ上に再配線７ａ〜７ｃをそれぞれ形成する。さらに、電解メッキにて第２の導体を開口部６ａ〜６ｃに埋め込むことにより、再配線７ａ〜７ｃ上に表面層８ａ〜８ｃをそれぞれ形成する。なお、再配線７ａは、パッド電極２ａとの接続に使用することができる。再配線７ｃは、配線２ｂとの接続に使用することができる。再配線７ｂ、緩衝層４上での再配線７ａ、７ｃの引き回しなどに使用することができる。
なお、表面層８ａ〜８ｃは再配線７ａ〜７ｃよりもエッチング耐性の高い材料を用いることができる。例えば、再配線７ａ〜７ｃの材料は、ＣｕまたはＣｕを主成分とする金属、表面層８ａ〜８ｃの材料は、Ｎｉ、Ｍｎ、Ｔａ、Ｚｎ、Ｃｒ、Ｃｏ、ＳｎおよびＰｂのうちの少なくともいずれか１つから選択することができる。また、再配線７ｂの幅は２０μｍ以下かつ再配線７ｂのハーフピッチは４０μｍ以下であることが望ましい。
次に、図２（ｃ）に示すように、アッシングなどの方法により、メタル膜５上のレジスト膜６を除去する。
ここで、レジスト膜６の吸光度を３６５ｎｍの波長の光に対して８０％以下に設定することにより、レジスト膜６の露光時において、レジスト膜６の表面での架橋度の増大を抑制しつつ、レジスト膜６の下地界面での架橋度を増大させることができる。このため、レジスト膜６の表面の過硬化を抑制しつつ、レジスト膜６の下地界面との密着性を上げることができ、開口部６ｂが形成されたレジスト膜６の幅が細い場合においても、現像時にレジスト膜６が剥がれるのを抑制することが可能となるとともに、それ以外の領域に幅の広いレジスト膜６が存在する場合においても、再配線７ａ〜７ｃの形成後にレジスト膜６を除去することができる。
なお、レジスト膜６の残し幅は、２０μｍ以下になると剥がれに対して顕著に厳しくなるので、２０μｍ以下であることが好ましい。ハーフピッチでは、４０μｍ以下であることが好ましい。
次に、図２（ｄ）に示すように、再配線７ａ〜７ｃをマスクとしてメタル膜５をエッチングすることにより、再配線７ａ〜７ｃの周囲のメタル膜５を除去する。
次に、図３（ａ）に示すように、感光性樹脂などを配線２ｂ、緩衝層４および表面層８ａ〜８ｃ上に塗布することにより、配線２ｂ、緩衝層４および表面層８ａ〜８ｃ上に緩衝層９を形成する。なお、緩衝層９の材料としては、例えば、ポリイミド系樹脂を用いることができる。ウェハストレスを低減させるために、ポリイミド系樹脂よりも硬化温度の低いアクリル系樹脂またはフェノール系樹脂を用いるようにしてもよい。
次に、図３（ｂ）に示すように、フォトリソグラフィー技術を用いることにより、パッド電極２ａ上の表面層８ａおよび配線２ｂの一部をそれぞれ露出させる開口部９ａ、９ｂを緩衝層９に形成する。
次に、図３（ｃ）に示すように、スパッタ、メッキ、ＣＶＤ、ＡＬＤまたは蒸着などの方法を用いることにより、配線２ｂ、保護膜３、緩衝層４、９および表面層８ａ上にメタル膜１０を形成する。なお、メタル膜１０としては、例えば、Ｔｉと、その上のＣｕとの積層構造を用いることができる。
次に、図４（ａ）に示すように、スピンコートなどの方法を用いることにより、メタル膜１０上にレジスト膜１１を形成する。
次に、図４（ｂ）に示すように、レジスト膜１１の露光および現像を行うことにより、パッド電極２ａ上の表面層８ａを露出させる開口部１１ａをレジスト膜１１に形成する。
次に、図５（ａ）に示すように、電解メッキにてバリア層１２およびハンダ層１３、１４を開口部１１ａに順次埋め込むことにより、メタル膜１０を介して表面層８ａ上に突出電極を形成する。なお、例えば、バリア層１２の材料はＮｉ、ハンダ層１３の材料はＣｕ、ハンダ層１４の材料はＳｎを用いることができる。
次に、図５（ｂ）に示すように、アッシングなどの方法により、メタル膜１０上のレジスト膜１１を除去する。
次に、図６（ａ）に示すように、バリア層１２およびハンダ層１３、１４からなる突出電極をマスクとして、メタル膜１０をエッチングすることにより、バリア層１２およびハンダ層１３、１４からなる突出電極の周囲のメタル膜１０を除去する。
次に、図６（ｂ）に示すように、ハンダ層１３、１４をリフローすることにより、ハンダ層１３、１４を合金化し、バリア層１２上に合金ハンダ層１５を形成する。
以上の工程は基材層１がウェハの状態で行うことができる。そして、以上の工程の後、このウェハを個片化することより、半導体チップを切り出すことができる。
なお、上述した実施形態では、突出電極としてハンダボールを用いる方法について説明したが、ニッケルバンプ、金バンプまたは銅バンプなどを用いるようにしてもよい。また、上述した実施形態では、メタル膜５、１０として、ＴｉとＣｕとの積層構造を用いる方法について説明したが、ＴｉまたはＣｕを単体で用いるようにしてもよいし、Ｃｒ、Ｐｔ、Ｗなどを単体として用いるようにしてもよし、これらの金属の積層構造を用いるようにしてもよい。
また、突出電極の接合方法としては、半田接合や合金接合などの金属接合を用いるようにしてもよいし、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＮＣＦ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接合、ＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合、ＮＣＰ（Ｎｏｎｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接合などを用いるようにしてもよい。
図７は、第１実施形態に係る吸光度の異なるレジストＡ、Ｂの表面と下面との露光量の関係を示す図である。なお、３６５ｎｍの波長の光に対して、レジストＡの吸光度は８１％、レジストＢの吸光度は４２％に設定した。また、レジストＡ、Ｂの膜厚は１０μｍに設定した。また、レジストＡ、Ｂの下地はＣｕ膜を用いた。
図７において、レジストＡではレジストＢに対して、表面での露光量が同じでも、下地との界面での露光量が低下する。このため、レジストＡでは、下地との密着性を上げるために、下地との界面での露光量を増大させると、表面で過露光となり、表面の過硬化が発生する。
一方、レジストＢでは、表面での露光量を増大させることなく、下地との界面での露光量を増大させることができ、表面での過露光を防止しつつ、下地との密着性を上げることができる。
次に、ライン＆スペースが３／３μｍ〜１５／１５μｍのパーフピッチパターンを形成し、第１実施形態に係る吸光度の異なるレジストＡ、Ｂの表面露光量と剥がれの発生するレジスト残し幅との関係を調べた。
この結果、例えば、５μｍの幅のレジストパターンを剥がれなしで形成するには、レジストＡでは、表面で６００ｍＪ／ｃｍ２以上の露光量が必要になり、表面の過硬化が発生するため、レジストパターンの剥離性が低下することが分かった。
一方、レジストＢでは、５μｍの幅のレジストパターンを剥がれなしで形成するには、表面で４００ｍＪ／ｃｍ２程度の露光量でよく、表面の過硬化を防止することができるため、ジストパターンの剥離性が低下するのを防止することができた。
さらに、第１実施形態に係る吸光度の異なるレジストＡ、Ｂの下面露光量と剥がれの発生するレジスト残し幅との関係を調べたところ、例えば、５μｍの幅のレジストパターンを剥がれなしで形成するには、レジストＡでは、下地との界面で１２０ｍＪ／ｃｍ２程度の露光量が必要であった。そして、下地との界面で１２０ｍＪ／ｃｍ２の露光量を得るには、図７を参照すると、表面では６００ｍＪ／ｃｍ２程度の露光量が必要となり、表面の過硬化が発生するため、レジストパターンの剥離性が低下した。すなわち、レジストＡでは吸光度が３６５ｎｍの波長の光に対して８０％を越えるため、本発明の効果が得られないことが分かった。
一方、レジストＢでは、５μｍの幅のレジストパターンを剥がれなしで形成するには、下地との界面で２００ｍＪ／ｃｍ２程度の露光量が必要であった。そして、下地との界面で２００ｍＪ／ｃｍ２程度の露光量を得るには、図７を参照すると、表面では４００ｍＪ／ｃｍ２程度の露光量でよく、表面の過硬化を防止することができるため、ジストパターンの剥離性が低下するのを防止することができた。すなわち、吸光度が３６５ｎｍの波長の光に対して４２％のレジストＢでは、本発明の効果が得られることが分かった。従って、本発明のレジスト膜６の吸光度は３６５ｎｍの波長の光に対して８０％以下とし、好ましくは６０％以下、更に好ましくは５０％以下である。
また、レジストＡにおいて、露光量が４００ｍＪ／ｃｍ２ではライン＆スペースが１０μｍ以上で剥離がなかった。また、レジストＡにおいて、露光量が６００ｍＪ／ｃｍ２ではライン＆スペースが６μｍ以上で剥離がなかった。
一方、レジストＢにおいて、露光量が４００ｍＪ／ｃｍ２ではライン＆スペースが５μｍ以上で剥離がなかった。また、レジストＢにおいて、露光量が６００ｍＪ／ｃｍ２ではライン＆スペースが３μｍ以上で剥離がなかった。
（第２実施形態）
上述した第１実施形態では、レジストパターンの剥がれを防止するために、レジスト膜６の吸光度を３６５ｎｍの波長の光に対して８０％以下に設定する方法について説明したが、レジスト膜６の現像時の溶解性を１μｍ／ｍｉｎ以下に低下させるようにしてもよい。なお、レジスト膜６の現像時の溶解性を低下させる方法としては、レジスト材料のアルカリ可溶性基を低下させることができる。
ここで、レジスト膜６の現像時の溶解性を低下させることにより、レジスト膜６と下地との界面に現像液が浸透するのを抑制することができ、レジストパターンの剥がれを低減することができる。
この第２実施形態に係る溶解性の異なるレジストＣ、Ｄの現像時間とレジスト残膜厚との関係を調べた。条件は次のとおりである。レジストＣ、Ｄとしてネガ型レジストを用い、レジストＤは、レジストＣに対してアルカリ可溶性基を約３０％だけ低下させたものを用い、レジストＣ、Ｄの膜厚は１０μｍに設定し、下地にＳｉ基板を用いた。
この結果、レジストＤの現像レートは２μｍ／ｍｉｎだったのに対し、レジストＣの現像レートは０．６７μｍ／ｍｉｎだった。このレジストＣを用いた場合、レジストＤを用いた場合に比べて、レジストパターンの剥がれを低減できた。
（第３実施形態）
図８〜図１３は、第３実施形態に係る半導体装置の製造方法を示す断面図である。
この第３実施形態では、図８（ｅ）の工程で、メタル膜５上にレジスト膜６を形成する前に、メタル膜５上にレジスト膜６との密着性を上げる表面改質層１６が形成される。
なお、メタル膜５の表面がＣｕである場合、表面改質層１６はＣｕ酸化膜を用いることができる。ここで、Ｃｕ酸化膜としては、ＣｕＯが好ましく、さらに好ましくはＣｕ２Ｏがよい。表面改質層１６はメタル膜５上に存在すればよく、表面改質層１６の膜厚は数ｎｍ程度でもよい。
表面改質層１６としてＣｕ酸化膜を用いると、Ｃｕの表面をＯで終端させることができ、レジスト膜６との密着性を上げることができる。
なお、Ｃｕ膜上にＣｕ酸化膜を形成する方法としては、酸化性雰囲気中で熱処理を行う方法を挙げることができる。なお、この熱処理の温度は室温以上であればよい。ただし、Ｃｕ酸化膜の形成時間を短くするために、熱処理の温度は数百℃以上に設定することが好ましい。
図８〜図１３において、図８（ｅ）の工程でメタル膜５上に表面改質層１６を形成する方法以外は、図１〜図６と同様のプロセスを行うことができる。
第３実施形態に係る下地の表面状態の異なる場合における、剥がれの発生するレジスト残し幅を表面露光量300ｍＪ／ｃｍ2において調べたところ、Ｃｕ膜状に直接レジストパターンを形成した場合は、剥がれ耐性レジスト残し幅が６μm程度であったのに対し、Ｃｕ膜上に熱処理にて表面改質層としてＣｕ酸化膜を形成してからレジストパターンを形成した場合は３μm程度となり、表面改質層を設けることにより、レジスト剥がれを抑制できることが分かった。
尚、このレジストパターンとしては、ライン＆スペースが３／３μｍ〜１５／１５μｍのパーフピッチパターンを用いた。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
１ 基材層、２ａ パッド電極、２ｂ 配線、３ 保護膜、３ａ、３ｂ、４ａ、４ｂ、６ａ〜６ｃ、９ａ、９ｂ、１１ａ 開口部、４、９、２１ 緩衝層、６、１１ レジスト膜、５、１０、２２ メタル膜、７ａ〜７ｃ、２３ 再配線、８ａ〜８ｃ、２４ 表面層、１２ バリア層、１３、１４ ハンダ層、１５ 合金ハンダ層、１６ 表面改質層

Claims (5)

  1. 配線およびパッド電極が形成された半導体基板と、
    前記半導体基板上に形成されたメタル膜と、
    前記メタル膜の表層に形成された表面改質層と、
    前記表面改質層を介して前記メタル膜上に形成された再配線とを備えることを特徴とする半導体装置。
  2. 前記メタル膜の下層はＴｉ、ＴｉＮ、ＴｉＷ、Ｗ、Ｔａ、Ｃｒ、ＣｏＴｉのうちのいずれかから選択され、前記メタル膜の上層はＣｕ、Ａｌ、Ｐｄ、Ａｕ、Ａｇのうちのいずれかから選択される積層構造、前記表面改質層はＣｕ酸化膜であることを特徴とする請求項１に記載の半導体装置。
  3. 配線およびパッド電極が形成された半導体基板上にメタル膜を形成する工程と、
    前記メタル膜との界面まで届く３６５ｎｍの波長の光に対して吸光度が８０％以下のレジストパターンを前記メタル膜上に形成する工程と、
    前記レジストパターン間に埋め込まれた再配線を前記メタル膜上に形成する工程と、
    前記再配線の形成後に前記レジストパターンを前記メタル膜上から除去する工程とを備えることを特徴とする半導体装置の製造方法。
  4. 配線およびパッド電極が形成された半導体基板上にメタル膜を形成する工程と、
    現像時の溶解性が１μｍ／ｍｉｎ以下のレジストパターンを前記メタル膜上に形成する工程と、
    前記レジストパターン間に埋め込まれた再配線を前記メタル膜上に形成する工程と、
    前記再配線の形成後に前記レジストパターンを前記メタル膜上から除去する工程とを備えることを特徴とする半導体装置の製造方法。
  5. 配線およびパッド電極が形成された半導体基板上にメタル膜を形成する工程と、
    前記メタル膜の表層に表面改質層を形成する工程と、
    前記レジストパターンを前記メタル膜上に形成する工程と、
    前記レジストパターン間に埋め込まれた再配線を前記メタル膜上に形成する工程と、
    前記再配線の形成後に前記レジストパターンを前記メタル膜上から除去する工程とを備えることを特徴とする半導体装置の製造方法。
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