JPS577141A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS577141A
JPS577141A JP8123580A JP8123580A JPS577141A JP S577141 A JPS577141 A JP S577141A JP 8123580 A JP8123580 A JP 8123580A JP 8123580 A JP8123580 A JP 8123580A JP S577141 A JPS577141 A JP S577141A
Authority
JP
Japan
Prior art keywords
wiring
layer
film
substrate
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8123580A
Other languages
Japanese (ja)
Inventor
Yoshimi Shiotani
Ryoji Abe
Mikio Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8123580A priority Critical patent/JPS577141A/en
Publication of JPS577141A publication Critical patent/JPS577141A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To elevate the yield and reliability with a less step in the multilayer interconnection by connecting wires arranged on a substrate to wires on the upper layers through a window provided in a layer insulation after it is burried flat with a plasma CVD film. CONSTITUTION:After a window is provided on an SiO2 2 on a substrate 1 with function regions formed thereon, for example, an Al layer is deposited entirely over the substrate in such a manner as to be connected thereto. With a resist pattern 11, the Al layer is etched to form a wiring 4 on the first layer. Then, a PSG film 10 is formed so thickly by plasma CVD that the wiring 4 can be burried flat. Projections 12 possible developed on the film 10 is removed by lifting off the PSG film 10 on the resist and a PSG film 5 is accumulated entirely thereon and subsequently, a window 6 to be connected to the wiring 4 is etched to form an Al wiring 7 on the upper layers. This can almost eliminate steps possibly produced with the formation of the wiring on the first layer, thereby hampering the development of disconnection, short-circuiting, or the like in the wiring 4 on the upper layers.
JP8123580A 1980-06-16 1980-06-16 Semiconductor device Pending JPS577141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8123580A JPS577141A (en) 1980-06-16 1980-06-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8123580A JPS577141A (en) 1980-06-16 1980-06-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS577141A true JPS577141A (en) 1982-01-14

Family

ID=13740774

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8123580A Pending JPS577141A (en) 1980-06-16 1980-06-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS577141A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130069225A1 (en) * 2011-09-21 2013-03-21 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Protection and Support Structure for Conductive Interconnect Structure
US9082832B2 (en) 2011-09-21 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130069225A1 (en) * 2011-09-21 2013-03-21 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Protection and Support Structure for Conductive Interconnect Structure
US9082832B2 (en) 2011-09-21 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US9484259B2 (en) 2011-09-21 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure

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