CN1988133A - 半导体装置及其制造方法、摄像机组件 - Google Patents

半导体装置及其制造方法、摄像机组件 Download PDF

Info

Publication number
CN1988133A
CN1988133A CNA2006101712225A CN200610171222A CN1988133A CN 1988133 A CN1988133 A CN 1988133A CN A2006101712225 A CNA2006101712225 A CN A2006101712225A CN 200610171222 A CN200610171222 A CN 200610171222A CN 1988133 A CN1988133 A CN 1988133A
Authority
CN
China
Prior art keywords
supporting mass
semiconductor
peristome
electronic device
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2006101712225A
Other languages
English (en)
Other versions
CN100536111C (zh
Inventor
野间崇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Publication of CN1988133A publication Critical patent/CN1988133A/zh
Application granted granted Critical
Publication of CN100536111C publication Critical patent/CN100536111C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14618Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3164Partial encapsulation or coating the coating being a foil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14683Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687Wafer level processing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/57Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0615Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/114Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146Plating
    • H01L2224/11462Electroplating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • H01L2224/1148Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/11848Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849Reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1415Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/14154Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81136Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81141Guiding structures both on and outside the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01057Lanthanum [La]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01072Hafnium [Hf]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Dicing (AREA)
  • Lens Barrels (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Studio Devices (AREA)

Abstract

一种封装型半导体装置及其制造方法,其谋求不使制造工序复杂化而提高可靠性及成品率。在形成平头电极(4)的半导体基板(2)的表面形成树脂层(6)及支承体(7)。蚀刻除去树脂层(6)及支承体(7)而露出平头电极(4)。如图3(c)所示,该蚀刻同时除去隔着切割线DL相向的两个导电端子形成区域(9)和其间连续区域上的支承体(7),而形成开口部(10)。之后,在开口部(10)露出的平头电极(4)上,形成金属层(11),进而形成导电端子(12)。最后,通过沿切割线DL切割而将半导体基板(2)分割为各个半导体芯片。

Description

半导体装置及其制造方法、摄像机组件
技术领域
本发明涉及一种半导体装置,特别涉及封装型半导体装置及其制造方法。另外,还涉及具有封装型半导体装置的摄像机组件。
背景技术
近年来,CSP(Chip Size Package)作为一种新的封装(パッケ一ジ)技术而被关注。CSP指的是具有与半导体芯片的外形尺寸大致相同的外形尺寸的小型封装件。
以往,作为CSP的一种,众所周知的有BGA(Ball Grid Array)型半导体装置。该BGA型半导体装置是排列于封装件的一主面上的多个由焊锡等金属部件构成的球形导电端子与搭载于封装件的其它面上的半导体芯片电连接而成的一种半导体装置。
将该BGA型半导体装置组装入电子器件中时,通过将各导电端子安装在印刷基板上的配线图案上,而与搭载于半导体芯片和印刷基板上的外部电路电连接。
这样的BGA型半导体装置与具有突出于侧部的导线销的SOP(SmallOutline Package)或QFP(Quad Flat Package)等其它CSP型的半导体装置相比,具有能够设置多个导电端子,而且可以小型化的优点,因此,作为例如搭载于便携式电话机上的数码相机的图像传感器芯片等广泛应用。
图15表示现有的BGA型半导体装置的概略结构,图15(a)为该BGA型半导体装置的表面侧的立体图。图15(b)为该BGA型半导体装置的背面侧的立体图。
该BGA型半导体装置101中,半导体基板104经由环氧树脂等树脂层105a、105b而密封在第一及第二玻璃基板102、103之间。在第二玻璃基板103的一主面上,即,BGA型半导体装置101的背面上,导电端子106在栅格上配置多个。该导电端子106经由第二配线109而与半导体基板104连结。在多个第二配线109上连结有分别从半导体基板104的内部引出的铝配线,各导电端子106与半导体基板104成为电连接。
参照图16进一步详细说明该BGA型半导体装置101的剖面结构。图16表示沿切割线DL被分割为各个芯片的BGA型半导体装置101的剖面图。
在半导体基板104的表面上形成的绝缘膜108上设有第一配线107。该半导体基板104的表面经树脂层105a与第一玻璃基板102粘接。该半导体基板104的背面经环氧树脂等树脂层105b与第二玻璃基板103粘接。
第一配线107的一端与第二配线109连接。该第二配线109自第一配线107的一端在第二玻璃基板103的表面上延伸。在第二玻璃基板103上延伸的第二配线109上形成球形导电端子106。在第二配线109的表面上形成由抗焊剂(ソルダ一レジスト)等构成的保护膜110。
上述技术记载于以下的专利文献1中。
专利文献1  (日本)专利公表2002-512436号公报
但是上述以往的半导体装置101中,具有其制造工序变得复杂的问题。
在上述半导体装置101中,由于其结构复杂而无法实现充分的可靠性。例如,由于半导体装置101的第一配线107与第二配线109的接触面积非常小,因此第二配线109在该接触部分有断线的可能。而且,也有第二配线109的阶梯覆盖(step coverage)差的问题。
从解决这种问题的观点看,半导体装置可以如以下说明的那样而构成。图1(a)为该半导体装置200自上方看的平面图,图1(b)为图1(a)的沿X-X线的剖面图。
该半导体装置200中,在其表面形成有电子器件201及平头电极202的半导体基板203上、经由树脂层205粘合由玻璃构成的支承体204。另外,206是由BPSG、氧化硅膜等构成的绝缘膜,207是由氮化硅膜等构成、且覆盖在平头电极202的一部分上的钝化膜。
支承体204的规定区域从其表面直到背面开口(贯通),分别在该各开口部208上形成由焊锡等构成的多个导电端子209。导电端子209经由镍或金等构成的金属层210而与平头电极202电连接。
根据所述结构,由于在设于支承体204上的多个开口部208内分别直接形成导电端子209,因此不需要现有例中所示的那样的配线,具有能够使制造工序简单化的优点。另外,由于半导体基板203的表面通过支承体204而被保护,因而,能够防止表面的电子器件201或周围元件的劣化,而提高半导体装置的可靠性及成品率。
但是,由于该半导体装置202的各个开口部208非常微小(例如为一边为100μm左右的大致正方形),因而也有在支承体204的目标位置上难以精度良好地形成目标大小的开口部208的问题。
发明内容
本发明的目的在于使制造工序简单化、提高半导体装置的可靠性和成品率。另外,其目的在于谋求作为摄像装置的半导体装置所搭载的摄像机组件的小型化、及提高可靠性和成品率。
本发明的主要特征如下。即,本发明的半导体装置的制造方法,其特征在于,具有支承体贴合工序,其在具有平头电极、且通过切割线而被划分的半导体基板的表面上贴合支承体;开口部形成工序,其通过对所述支承体中隔着所述切割线相对的外部连接用电极形成区域和其间的连续区域进行有选择地除去,而使所述半导体基板的一部分露出,形成开口部;半导体芯片分割工序,其通过沿所述切割线切割,将所述半导体基板分割为各个半导体芯片。
本发明的半导体装置的制造方法,其特征在于,其在所述半导体基板的表面上形成电子器件,在形成所述开口部的工序之前,具有薄化工序,将与所述支承体中的与所述电子器件的形成区域不重叠的区域的厚度通过蚀刻而薄化。
本发明的半导体装置,其具有:半导体基板,其具有电子器件及与所述电子器件电连接的外部连接用电极;支承体,其在所述电子器件的上方,与所述半导体基板贴合;其特征在于,在所述支承体的外周上,在从外侧向内侧的方向上设有开口部,在所述开口部上形成所述外部连接用电极。
本发明的半导体装置,其特征在于,与所述支承体中的所述电子器件的形成区域重叠的区域的厚度形成为比与所述电子器件的形成区域不重叠的区域的一部分的厚度更厚。
本发明的摄像机组件,其具有:摄像装置;具有外部电极、安装有所述摄像装置的电路板;将光导入所述摄像装置的感光区域的透镜;其特征在于,所述摄像装置具有:半导体基板,其具有感光元件及与所述感光元件电连接的外部连接用电极;支承体,其在所述电子器件的上方,与所述半导体基板贴合;开口部,其贯通所述支承体,经由所述开口部,所述电路板的外部电极与所述外部连接用电极电连接。
本发明的摄像机组件,其特征在于,所述开口部配置于所述支承体的外周,从外侧朝向内侧的方向开口。
本发明的摄像机组件,其特征在于,与所述支承体中的所述感光元件的形成区域重叠的区域的厚度形成为比与所述感光元件的形成区域不重叠的区域的一部分的厚度更厚。
根据本发明,由于半导体基板的表面经支承体而被保护,因此,能够防止表面的电子器件或其周围元件的劣化,提高半导体装置的可靠性及成品率。
由于对于支承体容易形成开口部,因此能够抑制制造成本,提高半导体装置的可靠性及成品率。
根据本发明的摄像机组件,能够谋求摄像机组件小型化,提高可靠性。
附图说明
图1(a)~(b)是说明本发明所涉及的半导体装置及其制造方法的平面图及剖面图;
图2是说明本发明第一实施方式的半导体装置及其制造方法的平面图;
图3(a)~(c)是说明本发明第一实施方式的半导体装置及其制造方法的剖面图;
图4(a)~(c)是说明本发明第一实施方式的半导体装置及其制造方法的剖面图;
图5是说明本发明第一实施方式的半导体装置及其制造方法的剖面图;
图6(a)~(b)是说明本发明第一实施方式的半导体装置的安装状态的平面图及剖面图;
图7(a)~(b)是说明本发明第一实施方式的半导体装置的安装状态的平面图及剖面图;
图8(a)~(b)是说明本发明第一实施方式的半导体装置的安装状态的平面图及剖面图;
图9是说明本发明第一实施方式的半导体装置的安装状态的剖面图;
图10(a)~(b)是说明本发明第一实施方式的半导体装置的安装状态的平面图及剖面图;
图11(a)~(c)是说明本发明第二实施方式的半导体装置及其制造方法的剖面图;
图12(a)~(c)是说明本发明第二实施方式的半导体装置及其制造方法的剖面图;
图13是说明本发明第二实施方式的半导体装置及其制造方法的剖面图;
图14(a)~(b)是说明本发明第二实施方式的半导体装置的安装状态的平面图及剖面图;
图15(a)~(b)是说明以往的半导体装置的立体图;
图16是说明以往的半导体装置的剖面图。
附图标记说明
1    电子器件         1A~1E 电路板           2     半导体基板
3    第一绝缘膜       4      平头电极         5     钝化膜
6    树脂层           7      支承体           8     光致抗蚀剂层
9    导电端子形成区域 10     开口部           11    金属层
12   导电端子         15     半导体芯片       16     感光区域
20   外部电极         20m    Cu层             20n    Cu层
21   连接线           21p    导电性膏体       22     填充材料
30   镜筒部           31     滤波器           32     透镜
40   DSP芯片          50     光致抗蚀剂层     55     光致抗蚀剂层
60   半导体芯片       H      电路板1B的高     H1     凹部
H2   凹部             H3     电路板1E的高     101    半导体装置
102  第一玻璃基板     103    第二玻璃基板     104    半导体基板
105a、105b 树脂层     106    导电端子         107    第一配线
108  绝缘层           109    第二配线         110    保护膜
200  半导体装置       201    电子器件         202    平头电极
203  半导体芯片       204    支承体           205    树脂层
206  绝缘层           207    钝化膜           208    开口部
209  导电端子         210    金属层           DL     切割线
具体实施方式
下面,参照附图对本发明的半导体装置及其制造方法的第一实施方式进行说明。图2为本发明的半导体装置的从上方看的概略平面图。图3~5为图2的沿Y-Y线的剖面图,表示其制造工序的顺序。
首先,本发明的第一实施方式所涉及的半导体装置的特征之一,如图2所示,沿支承体7的外周,从外侧朝向内侧的方向上设置多个开口部10,在该开口部10内,形成与其它电路板电连接的导电端子12及金属层11。以下,具体说明其制造方法。
如图3(a)所示,首先准备在其表面上形成电子器件1的由硅(Si)等构成的半导体基板2。接着,在半导体基板2的表面上形成例如膜厚为2μm的第一绝缘膜3(例如通过热氧化法或CVD法等形成的氧化硅膜或BPSG膜)。
接着,通过溅射法、镀敷法或其它成膜方法形成铝(Al)或铜(Cu)等金属层,之后,将未图示的光致抗蚀剂层作为掩模对该金属进行蚀刻,在第一绝缘膜3上形成平头电极4,膜厚为例如1μm。平头电极4与电子器件1或其周围元件电连接。
接着,在半导体基板2的表面上形成覆盖平头电极4的一部分的钝化膜5(例如:通过CVD法而形成的氮化硅膜)。
接着,包括平头电极4的半导体基板2的表面上,经由环氧树脂等的树脂层6粘合支承体7。支承体7由例如玻璃、石英、塑料等构成,在支承半导体基板2的同时,具有保护其表面的作用。电子器件1为CCD等感光元件的情况下。支承体7由透明或半透明的材料构成,为具有可透过光的性质。另外,根据需要,其后进行半导体基板2背面的背研磨,使半导体基板2的厚度变薄。
接着,如图3(b)所示,在支承体7的表面上有选择地形成光致抗蚀剂层8。在此,光致抗蚀剂层8在隔着切割线DL相邻的两导电端子形成区域9及其之间相应的位置开口而形成。
接着,如图3(c)所示,将光致抗蚀剂层8作为掩模进行支承体7的有选择的蚀刻。通过该蚀刻,隔着切割线DL相向的两导电端子形成区域9及其之间的连续区域作为一个单位被除去,形成贯通支承体7的开口部10。另外,从上方看该开口部10的情况下,开口部10如图2所示,沿支承体7的外周均等地形成。
该选择性蚀刻,可以通过例如干蚀刻或将氢氟酸(HF)作为蚀刻溶液的深度蚀刻进行。与蚀刻区域的一单位作为每一导电端子形成区域的半导体装置200(参照图1(a))相比,支承体的蚀刻区域的一单位跨越两个导电端子形成区域,面积扩大为两倍以上,因此,开口部能够在所希望的位置精度良好地、且容易地形成。
接着,如图4(a)所示,通过在开口部10的底部将露出的树脂层6有选择地蚀刻,露出平头电极4的上面一部分。另外,也可以通过一次蚀刻而进行支承体7的蚀刻和树脂层6的蚀刻。
接着,如图4(b)所示,在开口部10的底部露出的平头电极4上,形成由镍(Ni)和金(Au)构成的金属层11。
接着,如图4(c)所示,在金属层11的规定区域上,通过将金属层11作为电镀电极使用的电解电镀法,固定焊锡球,形成导电端子12。另外,通过对焊锡进行丝网印刷(スクリ一ン印刷),且经热处理使该焊锡回流,从而能够形成同样的导电端子12。导电端子12的形成方法不局限于这些,还可以使用调和器(デイスペンサ)涂敷焊锡等所谓的调和法(涂敷法)等来形成。导电端子12其材料可以使用金,但对其材料并不特别限定。另外,也有如以下说明的不形成导电端子12的情况。这种情况下,金属层11或平头电极4为被露出的状态。
最后,如图5所示,沿切割线DL将半导体基板2分割成各个半导体芯片15。这样,完成本实施方式所涉及的半导体装置。完成的半导体装置安装在外部电极构图形成的电路板上。安装时,导电端子12作为外部连接用电极与电路板上的外部电极电连接。另外,在不形成导电端子12的情况下,金属层11或平头电极4作为外部连接用电极与电路板上的外部电极以连接线等电连接。
在第一实施方式中,不需要以往那样的复杂配线,具有能够使制造工序简单化的优点。另外,由于半导体基板2的背面被支承体7所保护,因此,能够防止形成在表面的电子器件1及其周围元件的劣化,且能够提高半导体装置的可靠性。另外,如上所述,由于向支承体7的开口部10的形成变得容易,因此,能够将制造成本压低,其结果使半导体装置的可靠性及成品率提高。
接着,参照附图说明本实施方式的半导体装置安装在电路板(组件基板)上的情况。另外,在以下说明中,对于电子器件1为CCD型图像传感器或CMOS型图像传感器等感光元件,半导体芯片15作为摄像机组件的摄像装置而使用的情况进行说明。图6(a)是从上方看到的安装有本实施方式的半导体装置的摄像机组件的平面图,图6(b)是图6(a)沿Z-Z线的剖面图。
如图6(a)所示,在例如印刷基板那样的电路板1A上搭载半导体芯片15。半导体基板15其背面侧(不形成支承体7的一侧)与电路板1A相对而形成。电路板1A上,构图形成外部电极20。
进而,半导体芯片15的平头电极4与外部电极20经由例如焊线21电连接。另外,也可以使用形成导电图案而成的柔性板或胶带来代替焊线21。另外,虽未图示,也可以在平头电极4上形成金属层11,该金属层11与外部电极20经由焊线21等电连接。
进一步,如图6(b)所示,在电路板1A的表面上,以覆盖半导体芯片15的方式设置有镜筒部30。镜筒部30之中,在对应于半导体芯片15的感光区域16的位置上,设有截断特定波长的滤波器31及汇集外部光线的透镜32。在此,与以往的半导体装置101(参照图15)不同,半导体芯片15的背面不形成导电端子而被平坦化,因此,能够尽量消除安装半导体芯片15时的倾斜或偏离。进而,能够回避由该摄像机组件引起的摄像时对像的不利影响。
另外,在电路板1A的背面,也可以配置处理来自感光元件的图像信号的DSP(Digital Signal Processor)芯片40。这样,通过使半导体芯片15与DSP芯片40在电路板1A的表面与背面重叠构成,能够将电路板1A的面积控制为较小。
另外,在本实施方式的半导体装置向电路板上的安装可以如图7所示进行。图7(a)为从上方看到的本实施方式的半导体装置作为摄像机组件的摄像装置而安装的状态的平面图,图7(b)为图7(a)的沿O-O线的剖面图。另外,图6中对已有图示的相同结构使用相同符号,省略其说明。
如图7(a),例如,使印刷基板那样的电路板1B的背面和半导体芯片15的表面相对,而搭载半导体芯片15。在此,导电端子12与在电路板1B的背面构图形成的外部电极20直接连接。
另外,电路板1B上与感光区域16重叠的区域开口,并设有感光窗1W。因此,即使半导体芯片15搭载在电路板1B的背面,也能够感光。
另外,在本结构中,由于电路板1B的背面搭载半导体芯片15,因此电路板1B的厚度也成为焦距的一部分。为此,与在如图6所示的电路板的上方配置半导体芯片15的结构相比,至少有可能使镜筒部30的高度降低电路板1B的厚度H,而实现摄像机组件的小型化。
但是,在摄像机组件中,若摄像装置的感光面上附着上细小的尘埃或尘土,则感光量会减少,而出现图像模糊等品质劣化。为此,如图7(b)的虚线所示,可以将滤波器31在电路板1B上使用专用的卡具固定。这样,滤波器就不仅发挥滤波器原有的作用(截断特定波长的光),而且通过作为密封半导体芯片15的表面的盖来使用,而有效防止尘埃或尘土附着在感光面(支承体7的表面)上,能够提高摄像机组件的可靠性。
也可以如图8所示进行本实施方式的半导体装置在电路板上的安装。图8(a)为从上方看到的安装有本实施方式的半导体装置的摄像机组件的平面图,图8(b)为图8(a)沿P-P线的剖面图。另外,对于在图6或图7中已图示的相同结构要件使用相同符号,省略其说明。
如图8(b)所示,在例如像印刷基板那样的电路板1C上形成凹部H1,以埋入到该凹部H1内的方式搭载半导体芯片15。凹部H1的形成通过例如由激光照射的蚀刻或通过钻的切削而进行。
另外,在凹部1的底部形成作为放热层例如由传热性高的铜构成的Cu层20m,与半导体芯片15的背面相连。通过这样构成,能够使半导体芯片15工作时产生的热从半导体芯片15的底部传到Cu层20m而向外部散去。
因此,能够有效防止由热引起的电子器件1的性能劣化。因而,如果电子器件1是容易由热而引起电子特性劣化的CCD等感光元件,则能够防止其性能劣化,提高工作品质。
另外,如图8(b)所示,Cu层20m的表面和半导体芯片15的背面相连,但并不必须为直接相连,也可以在二者之间形成氧化硅膜、氮化硅膜或树脂膜等的绝缘膜。
另外,搭载半导体芯片15时,凹部H1的侧壁与半导体芯片15之间存在空间的情况下,通过填充填充材料22(例如环氧树脂等有机材料)而填埋该空间。
进而,平头电极4与电路板1C的外部电极20经由焊线21而连接。另外,虽未图示,也可以在平头电极4上形成金属层11,该金属层11与外部电极20经由焊线21等电连接。进而,代替焊线21,如图9所示,也可以使用由例如含有银(Ag)粒子的导电性膏体21p构成的配线。导电性膏体21p从平头电极4上的开口部在外部电极20上延伸而形成。
另外,可以如图10所示进行本实施方式的半导体装置向电路板上的安装。图10(a)为从上方看到的安装有本实施方式的半导体装置的摄像机组件的平面图,图10(b)为图10(a)沿Q-Q线的剖面图。另外,对已图示的相同结构要件使用相同符号,省略其说明。
如图10(b)所示,在印刷基板那样的电路板1D的背面一侧形成凹部H2,在该凹部H2内以埋入的方式载置半导体芯片15。凹部H2的形成,通过例如由激光照射的蚀刻或通过钻的切削而进行。
电路板1D的内部,作为外部电极用的配线层形成例如Cu层20n,与作为外部连接用电极的导电端子12电连接。另外,电路板1D上,在与感光区域16重叠的区域设有感光窗1W。因此,即使半导体芯片15搭载于电路板1D的背面,也能够感光。
另外,在本结构中,由于电路板1D的背面载置有半导体芯片15,因此,电路板1D的厚度的一部分成为焦距的一部分。因此,与如图8所示的在电路板的上方配置半导体芯片15的结构相比,有可能使镜筒部30的高度降低,而实现摄像机组件的小型化。
另外,载置半导体芯片15时,凹部H2的侧壁与半导体芯片15之间存在空间的情况下,通过填充填充材料22而填埋该空间。
接着,参照附图对本发明的第二实施方式的半导体装置及其制造方法进行说明。以下,说明其制造方法。图11~13表示制造工序的顺序。对已说明的相同结构要件使用相同符号,省略其说明。
如图11(a)所示,首先准备在其表面上形成有电子器件1的由硅(Si)等构成的半导体基板2。进而,在半导体基板2的表面上形成第一绝缘膜3。
接着,通过溅射法、电镀法或其它成膜方法形成铝(Al)或铜(Cu)等金属层,其后,将未图示的光致抗蚀剂层作为掩模对该金属层进行蚀刻,在第一绝缘膜3上形成平头电极4。
接着,在半导体基板2的表面上,形成覆盖在平头电极4的一部分上的钝化膜5。接着,在包含平头电极4的半导体基板2的表面上经由环氧树脂等树脂层6,粘合支承体7。另外,根据需要,其后进行半导体基板2的背面的背研磨,使半导体基板2的厚度变薄。
接着,如图11(b)所示,支承体7的表面上有选择地形成光致抗蚀剂层50。在此,光致抗蚀剂层50至少在与电子器件1的形成区域重叠的区域,更优选地,仅在与电子器件1的形成区域重叠的区域形成。进而,将光致抗蚀剂层50作为掩模进行支承体7的有选择的蚀刻。通过该蚀刻,对支承体7中的规定区域(与电子器件的形成区域不重叠的区域的一部分)进行蚀刻,将其厚度减薄规定量。例如将约100μm的厚度减薄为约30μm。
接着,如图11(c)所示,在支承体7的表面上有选择地形成光致抗蚀剂层55。进而,将光致抗蚀剂层55作为掩模进行支承体7的有选择的蚀刻。通过该蚀刻,在隔着切割线DL相向的两导电端子形成区域9及其之间的连续区域上的支承体7被同时除去,形成贯通支承体7的开口部10。进而,支承体7形成为凸状,支承体7中与电子器件1的形成区域重叠的区域的厚度,比其它的区域厚。
接着,如图12(a)所示,通过对开口部10的底部露出的树脂层6进行有选择的蚀刻,露出平头电极4的上面一部分。接着,如图12(b)所示,在开口部10的底部露出的平头电极4上,形成由镍(Ni)及金(Au)等构成的金属层11。
接着,如图12(c)所示在金属层11的规定区域上形成导电端子12。另外,虽未图示,与第一实施方式相同,也有不形成导电端子12的情况。最后,如图13所示,沿切割线DL将半导体基板2分割为各个半导体芯片60。这样,完成第二实施方式的半导体装置。
在第二实施方式中,不需要以往那样的复杂配线,具有能够使制造工序简单化的优点。另外,半导体基板2的表面通过支承体7而被保护,因此,能够防止在表面形成的电子器件1或其周围元件的劣化,提高半导体装置的可靠性。另外,与第一实施方式相同,容易形成朝向支承体7的开口部10,因此,能够抑制制造成本,提高半导体装置的可靠性及成品率。
接着,参照附图说明第二实施方式的半导体装置向电路板上安装的情况。另外,在以下的说明中,以电子器件1为CCD型图像传感器或CMOS型图像传感器等感光元件进行说明。图14(a)为从上方看到的安装有第二实施方式的半导体装置的摄像机组件的平面图,图14(b)为图14(a)的沿R-R线的剖面图。
如图14(a)所示,例如像印刷基板那样的电路板1E的背面与半导体芯片60的表面相对而载置半导体芯片60。在此,导电端子12与在电路板1E的背面构图形成的外部电极20直接连接。
另外,在电路板1E上与感光区域16重叠的区域开口,设置感光窗1W。因此,即使半导体芯片60载置于电路板1E的背面,也能够感光。在此,本实施方式中,将支承体7中厚的部分(凸状部分)使用未图示的粘结剂而嵌合在电路板1E的感光窗1W上。因此,支承体7的表面中仅厚的部分的区域在感光窗1W处露出。
这样,根据半导体芯片的支承体7中的规定区域的表面的加厚加工的结构,在所述第一实施方式的半导体装置所得的效果之外,还使安装到摄像机组件上之后支承体7中感光区域16的表面清洁变得容易。另外,通过支承体7的表面和电路板1E的表面的高度位置大致相同的这样的结构,更进一步提高清洁工作的操作性。另外,可以防止安装半导体芯片时使用的粘结剂卷入感光区域16的支承体7的表面。因此,具有能够提高摄像机组件的维护性及可靠性的优点。具体地作为清洁方法的一例,取下镜筒部30后,使用棉花棍等规定的清扫用具清洁支承体7的表面。
另外,本结构中,由于电路板1E的背面上载置半导体芯片60,电路板1E的厚度也成为焦距的一部分。因此,与如图6所示的电路板的上方配置半导体芯片15的结构相比,至少有可能使镜筒部30的高度降低电路板1E的高度H3,而实现摄像机组件的小型化。另外,通过如图14(b)的虚线所示配置滤波器31,将其作为密封半导体芯片60表面的盖来使用,而有效防止尘埃或尘土附着在感光面(支承体7的表面)上,能够提高摄像机组件的可靠性,这一点与第一实施方式是相同的。更进一步,该半导体芯片60能够以各种各样的形式安装在电路板上,这与第一实施方式也是相同的。

Claims (12)

1.一种半导体装置的制造方法,其特征在于,具有
支承体贴合工序,其在具有平头电极、且通过切割线而被划分的半导体基板的表面上贴合支承体;
开口部形成工序,其通过对所述支承体中隔着所述切割线相向的外部连接用电极形成区域和其间的连续区域进行有选择的除去,而使所述半导体基板的一部分露出,形成开口部;
半导体芯片分割工序,其通过沿所述切割线切割,将所述半导体基板分割为各个半导体芯片。
2.如权利要求1所述的半导体装置的制造方法,其特征在于,具有金属层形成工序,其在所述开口部形成工序之后,在所述开口部内形成与所述平头电极电连接的金属层;
导电端子形成工序,其在所述金属层上形成导电端子。
3.如权利要求1或2中所述的半导体装置的制造方法,其特征在于,其在所述半导体基板的表面上形成电子器件,
在所述开口部形成工序之前,具有薄化工序,将与所述支承体中与所述电子器件的形成区域不重叠的区域的厚度进行蚀刻而薄化。
4.如权利要求1至3中任一项所述的半导体装置的制造方法,其特征在于,所述电子器件为感光元件。
5.一种半导体装置,其具有
半导体基板,其具有电子器件及与所述电子器件电连接的外部连接用电极;
支承体,其在所述电子器件的上方,与所述半导体基板贴合;
其特征在于,
在所述支承体的外周上,在从外侧向内侧的方向上设有开口部,在所述开口部上形成所述外部连接用电极。
6.如权利要求5所述的半导体装置,其特征在于,与所述支承体中与所述电子器件的形成区域重叠的区域的厚度形成为比与所述电子器件的形成区域不重叠的区域的一部分的厚度更厚。
7.如权利要求5或6所述的半导体装置,其特征在于所述电子器件为感光元件。
8.一种摄像机组件,其具有
摄像装置;
具有外部电极、安装有所述摄像装置的电路板;
将光导入所述摄像装置的感光区域的透镜;
其特征在于,所述摄像装置具有:
半导体基板,其具有感光元件及与所述感光元件电连接的外部连接用电极;
支承体,其在所述电子器件的上方,与所述半导体基板贴合;
开口部,其贯通所述支承体,
经由所述开口部,所述电路板的外部电极与所述外部连接用电极电连接。
9.如权利要求8所述的摄像机组件,其特征在于,所述开口部配置于所述支承体的外周,从外侧朝向内侧的方向开口。
10.如权利要求9所述的摄像机组件,其特征在于,所述支承体中与所述感光元件的形成区域重叠的区域的厚度形成为比与所述感光元件的形成区域不重叠的区域的一部分的厚度更厚。
11.如权利要求10所述的摄像机组件,其特征在于,仅露出所述支承体的表面中形成得较厚的区域。
12.如权利要求8至11中任一项所述的摄像机组件,其特征在于,用于去掉规定的波长区域的光的滤波器配置于所述摄像装置与所述透镜之间,
所述滤波器兼作密封所述摄像装置的盖。
CNB2006101712225A 2005-12-21 2006-12-21 半导体装置及其制造方法、摄像机组件 Expired - Fee Related CN100536111C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005368631A JP5427337B2 (ja) 2005-12-21 2005-12-21 半導体装置及びその製造方法、カメラモジュール
JP368631/05 2005-12-21

Publications (2)

Publication Number Publication Date
CN1988133A true CN1988133A (zh) 2007-06-27
CN100536111C CN100536111C (zh) 2009-09-02

Family

ID=38057845

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101712225A Expired - Fee Related CN100536111C (zh) 2005-12-21 2006-12-21 半导体装置及其制造方法、摄像机组件

Country Status (7)

Country Link
US (1) US7576402B2 (zh)
EP (1) EP1801849A3 (zh)
JP (1) JP5427337B2 (zh)
KR (1) KR100840501B1 (zh)
CN (1) CN100536111C (zh)
SG (1) SG133571A1 (zh)
TW (1) TWI329931B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102420147A (zh) * 2010-09-27 2012-04-18 新科金朋有限公司 形成保护结构用于绝缘层局部平坦化的方法和半导体器件
CN107039365A (zh) * 2015-11-23 2017-08-11 精材科技股份有限公司 晶片封装体及其制造方法
US10403675B2 (en) 2015-01-13 2019-09-03 Sony Semiconductor Solutions Corporation Semiconductor device and method for manufacturing semiconductor device, solid-state image pickup element, image pickup device, and electronic apparatus
US10580811B2 (en) 2015-11-24 2020-03-03 Sony Corporation Image pickup element package having a supporting resin frame with a thermally conductive portion including electronic components, and associated image pickup apparatus
CN111708452A (zh) * 2016-05-19 2020-09-25 三星显示有限公司 电子装置

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008092417A (ja) * 2006-10-04 2008-04-17 Matsushita Electric Ind Co Ltd 半導体撮像素子およびその製造方法並びに半導体撮像装置および半導体撮像モジュール
JP5295783B2 (ja) 2007-02-02 2013-09-18 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
WO2008123020A1 (ja) * 2007-03-09 2008-10-16 Sanyo Electric Co., Ltd. 半導体装置及びその製造方法
US20080265356A1 (en) * 2007-04-27 2008-10-30 Jin-Chyuan Biar Chip size image sensing chip package
CN101562175B (zh) * 2008-04-18 2011-11-09 鸿富锦精密工业(深圳)有限公司 影像感测器封装结构及其应用的成像装置
KR20100039686A (ko) 2008-10-08 2010-04-16 주식회사 하이닉스반도체 이미지 센서 모듈 및 이의 제조 방법
JP2010161163A (ja) * 2009-01-07 2010-07-22 Disco Abrasive Syst Ltd 撮像基板の加工方法
US8193555B2 (en) 2009-02-11 2012-06-05 Megica Corporation Image and light sensor chip packages
CN102572229A (zh) * 2010-12-29 2012-07-11 鸿富锦精密工业(深圳)有限公司 摄像模组
KR101131782B1 (ko) 2011-07-19 2012-03-30 디지털옵틱스 코포레이션 이스트 집적 모듈용 기판
JP5903796B2 (ja) * 2011-08-12 2016-04-13 ソニー株式会社 撮像装置およびカメラモジュール
US8513757B1 (en) * 2012-06-08 2013-08-20 Apple Inc. Cover for image sensor assembly with light absorbing layer and alignment features
TWI512961B (zh) 2013-08-16 2015-12-11 Azurewave Technologies Inc 用於降低整體厚度的影像感測模組及其製作方法

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63271969A (ja) * 1987-04-29 1988-11-09 Olympus Optical Co Ltd 固体撮像素子
JPH05347394A (ja) * 1992-06-15 1993-12-27 Sony Corp 固体撮像装置及びこの固体撮像装置と取付枠との結合構造
IL123207A0 (en) 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
US6503780B1 (en) * 2000-07-05 2003-01-07 Amkor Technology, Inc. Wafer scale image sensor package fabrication method
US6342406B1 (en) * 2000-11-15 2002-01-29 Amkor Technology, Inc. Flip chip on glass image sensor package fabrication method
JP3778817B2 (ja) * 2001-07-11 2006-05-24 富士フイルムマイクロデバイス株式会社 固体撮像装置およびその製造方法
JP2003078120A (ja) * 2001-08-31 2003-03-14 Seiko Precision Inc 固体撮像装置
JP3675402B2 (ja) * 2001-12-27 2005-07-27 セイコーエプソン株式会社 光デバイス及びその製造方法、光モジュール、回路基板並びに電子機器
JP2003309271A (ja) * 2002-04-18 2003-10-31 Matsushita Electric Ind Co Ltd 集積回路素子の実装構造および実装方法
JP4241160B2 (ja) * 2002-04-22 2009-03-18 富士フイルム株式会社 固体撮像装置の製造方法
JP2004096033A (ja) * 2002-09-04 2004-03-25 Iwate Toshiba Electronics Co Ltd 半導体装置及びその製造方法
KR20040033193A (ko) * 2002-10-11 2004-04-21 (주)그래픽테크노재팬 이미지 센서용 반도체 칩 패키지 및 제조 방법
JP4450168B2 (ja) * 2002-11-27 2010-04-14 セイコーエプソン株式会社 半導体装置の製造方法および半導体装置用カバー
JP2004200966A (ja) * 2002-12-18 2004-07-15 Sanyo Electric Co Ltd カメラモジュール
KR100541650B1 (ko) 2003-08-12 2006-01-10 삼성전자주식회사 고체 촬상용 반도체 장치 및 그 제조방법
DE10344770A1 (de) * 2003-09-26 2005-05-04 Siemens Ag Optisches Modul und optisches System
JP3839019B2 (ja) * 2003-12-24 2006-11-01 三菱電機株式会社 撮像装置
JP2005311107A (ja) * 2004-04-22 2005-11-04 Shinko Electric Ind Co Ltd 光学半導体装置
JP2006032886A (ja) * 2004-06-15 2006-02-02 Fuji Photo Film Co Ltd 固体撮像装置及びその製造方法及びカメラモジュール
US7115961B2 (en) * 2004-08-24 2006-10-03 Micron Technology, Inc. Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices
KR100785488B1 (ko) 2005-04-06 2007-12-13 한국과학기술원 이미지 센서 모듈 및 이의 제조 방법
JP4686400B2 (ja) * 2005-07-21 2011-05-25 パナソニック株式会社 光学デバイス、光学デバイス装置、カメラモジュールおよび光学デバイスの製造方法
KR20050119101A (ko) * 2005-12-07 2005-12-20 삼성전자주식회사 고체 촬상용 반도체 장치의 제조방법

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102420147A (zh) * 2010-09-27 2012-04-18 新科金朋有限公司 形成保护结构用于绝缘层局部平坦化的方法和半导体器件
CN102420147B (zh) * 2010-09-27 2016-05-18 新科金朋有限公司 形成保护结构用于绝缘层局部平坦化的方法和半导体器件
US10163815B2 (en) 2010-09-27 2018-12-25 STATS ChipPAC Pte. Ltd. Semiconductor device with dummy metal protective structure around semiconductor die for localized planarization of insulating layer
US10403675B2 (en) 2015-01-13 2019-09-03 Sony Semiconductor Solutions Corporation Semiconductor device and method for manufacturing semiconductor device, solid-state image pickup element, image pickup device, and electronic apparatus
CN107039365A (zh) * 2015-11-23 2017-08-11 精材科技股份有限公司 晶片封装体及其制造方法
US10580811B2 (en) 2015-11-24 2020-03-03 Sony Corporation Image pickup element package having a supporting resin frame with a thermally conductive portion including electronic components, and associated image pickup apparatus
CN111708452A (zh) * 2016-05-19 2020-09-25 三星显示有限公司 电子装置
CN111708452B (zh) * 2016-05-19 2023-04-28 三星显示有限公司 电子装置

Also Published As

Publication number Publication date
TW200729371A (en) 2007-08-01
US7576402B2 (en) 2009-08-18
JP2007173483A (ja) 2007-07-05
EP1801849A3 (en) 2008-07-02
EP1801849A2 (en) 2007-06-27
CN100536111C (zh) 2009-09-02
TWI329931B (en) 2010-09-01
US20070166955A1 (en) 2007-07-19
KR20070067634A (ko) 2007-06-28
SG133571A1 (en) 2007-07-30
KR100840501B1 (ko) 2008-06-23
JP5427337B2 (ja) 2014-02-26

Similar Documents

Publication Publication Date Title
CN100536111C (zh) 半导体装置及其制造方法、摄像机组件
EP1398832B1 (en) Camera module for compact electronic equipments
US7524753B2 (en) Semiconductor device having through electrode and method of manufacturing the same
EP1237202B1 (en) Semiconductor device and method for making the same
US6803651B1 (en) Optoelectronic semiconductor package device
US8766408B2 (en) Semiconductor device and manufacturing method thereof
KR100616670B1 (ko) 웨이퍼 레벨의 이미지 센서 모듈 및 그 제조방법
US7397134B2 (en) Semiconductor device mounted on and electrically connected to circuit board
US7084474B2 (en) Photosensitive semiconductor package and method for fabricating the same
CN101170090A (zh) 半导体装置及其制造方法
CN100501986C (zh) 半导体装置及其制造方法
KR100494474B1 (ko) 카메라 모듈 및 그 제조방법
JP3614840B2 (ja) 半導体装置
CN109729241B (zh) 摄像模组及其扩展布线封装感光组件和其制作方法
KR20050120142A (ko) 에폭시를 이용한 카메라 모듈 및 그 제조방법
US6936495B1 (en) Method of making an optoelectronic semiconductor package device
JP2005065285A (ja) 固体撮像用半導体装置及びその製造方法
EP4411803A1 (en) Imaging device, electronic apparatus, and method for manufacturing imaging device
JP4283801B2 (ja) カメラモジュール及びその製造方法
KR20010058581A (ko) 반도체패키지 및 그 제조방법
CN116490967A (zh) 成像装置、电子设备和成像装置的制造方法
KR19990006190A (ko) 칩 크기 패키지 및 그의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090902

Termination date: 20201221

CF01 Termination of patent right due to non-payment of annual fee