CN107039365A - 晶片封装体及其制造方法 - Google Patents

晶片封装体及其制造方法 Download PDF

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Publication number
CN107039365A
CN107039365A CN201611053813.2A CN201611053813A CN107039365A CN 107039365 A CN107039365 A CN 107039365A CN 201611053813 A CN201611053813 A CN 201611053813A CN 107039365 A CN107039365 A CN 107039365A
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hard conating
encapsulation body
wafer encapsulation
body according
conductive
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刘建宏
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XinTec Inc
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XinTec Inc
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Abstract

本发明提供一种晶片封装体及其制造方法。该方法包括：提供一装置基底，装置基底包括一感测装置及露出于装置基底的一表面的多个导电垫；于每一导电垫上对应形成一导电结构，接着于装置基底的表面上覆盖一硬涂层，硬涂层完全覆盖位于每一导电垫上的导电结构；以及对硬涂层进行薄化，以露出位于每一导电垫上的导电结构，其中硬涂层及位于每一导电垫上的导电结构具有实质上平坦且彼此切齐的表面。本发明不仅能够维持或改善晶片封装体的装置效能及可靠度，还能够简化制程及降低制造成本，且有助于后续对晶片封装体进行打线制程及模塑制程。

Description

晶片封装体及其制造方法
技术领域
本发明有关于一种晶片封装技术，特别为有关于一种晶片封装体及其制造方法。
背景技术
随着电子或光电产品诸如数字相机、具有影像拍摄功能的手机、条码扫瞄器(barcode reader)以及监视器需求的增加，半导体技术发展的相当快速，且半导体晶片的尺寸有微缩化(miniaturization)的趋势，而其功能也变得更为复杂。
大多数的半导体晶片通常为了效能上的需求而置放于一密封的封装体，其有助于操作上的稳定性。因此，晶片封装制程是制造电子产品过程中的重要步骤。晶片封装体除了将晶片保护于其中，使其免受外界环境污染外，还提供晶片内部电子元件与外界的电性连接通路。然而，由于电子或光电产品的功能复杂化，因此增加封装体的制造困难度及/或可靠度。
图1是绘示出一晶片封装体10的剖面示意图。晶片封装体10的制作包括将一晶片100(例如，一感测晶片)装设于一封装基底200上。接着，进行打线制程，以将接线102电性连接于晶片100导电垫100a与封装基底200的导电垫200a之间。之后，进行模塑制程以形成封装层104，其密封封装基底200、接线102及部分的晶片100而露出晶片100的感测区。最后，利用喷涂制程在封装层104的表面及晶片100的感测区上形成一硬涂层106，以保护晶片100的感测区。
然而，由于封装层104与晶片100之间形成高度落差(step height)，且硬涂层106的材料在固化以前具有流动性，因而造成硬涂层106的厚度不均而影响晶片封装体10的装置效能及可靠度。
因此，有必要寻求一种新颖的晶片封装体及其制造方法，其能够解决或改善上述的问题。
发明内容
本发明的实施例提供一种晶片封装体的制造方法，包括：提供一装置基底，其包括一感测装置及露出于装置基底的一表面的多个导电垫；于每一导电垫上对应形成一导电结构；于装置基底的表面上覆盖一硬涂层，且硬涂层完全覆盖位于每一导电垫上的导电结构；以及对硬涂层进行薄化，以露出位于每一导电垫上的导电结构，且使硬涂层及位于每一导电垫上的导电结构具有实质上平坦且彼此切齐的表面。
本发明的另一实施例提供一种晶片封装体，包括：一装置基底，包括一感测装置及露出于装置基底的一表面的多个导电垫；一硬涂层，覆盖装置基底的表面，且具有分别露出导电垫的多个开口；以及多个导电结构，对应设置于开口内，且电性连接至导电垫，其中硬涂层及导电结构具有实质上平坦且彼此切齐的表面。
本发明不仅能够维持或改善晶片封装体的装置效能及可靠度，还能够简化制程及降低制造成本，且有助于后续对晶片封装体进行打线制程及模塑制程。
附图说明
图1是绘示出一晶片封装体的剖面示意图。
图2A至2C是绘示出本发明一实施例的晶片封装体的不同中间制造阶段的剖面示意图。
图3A至3D是绘示出本发明另一实施例的晶片封装体的不同中间制造阶段的剖面示意图。
其中，附图中符号的简单说明如下：
10、20、30：晶片封装体；100：晶片；100a、200a、304、400a：导电垫；102、310：接线；104、312：封装层；106、308：硬涂层；200：封装基底；300：本体；301：感测装置；302：金属化层；303：装置基底；306：光阻图案层；306a：开口；307：导电结构；400：封装基底。
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明一实施例的晶片封装体可用以封装微机电系统晶片。然其应用不限于此，例如在本发明的晶片封装体的实施例中，其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路(digital or analog circuits)等集成电路的电子元件(electronic components)，例如是有关于光电元件(optoelectronic devices)、微机电系统(Micro Electro Mechanical System,MEMS)、生物辨识元件(biometric device)、微流体系统(micro fluidic systems)、或利用热、光线、电容及压力等物理量变化来测量的物理感测器(Physical Sensor)。特别是可选择使用晶圆级封装(wafer scale package,WSP)制程对影像感测元件、发光二极管(light-emittingdiodes,LEDs)、太阳能电池(solar cells)、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、指纹辨识元件(fingerprint-recognitiondevice)、微制动器(micro actuators)、表面声波元件(surface acoustic wavedevices)、压力感测器(process sensors)或喷墨头(ink printer heads)等半导体晶片进行封装。
其中上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后，再予以切割成独立的封装体，然而，在一特定实施例中，例如将已分离的半导体晶片重新分布在一承载晶圆上，再进行封装制程，亦可称之为晶圆级封装制程。另外，上述晶圆级封装制程亦适用于通过堆迭(stack)方式安排具有集成电路的多片晶圆，以形成多层集成电路(multi-layerintegrated circuit devices)或系统级封装(System in Package,SIP)的晶片封装体。
请参照图2C，其绘示出根据本发明一实施例的晶片封装体20的剖面示意图。在本实施例中，晶片封装体20包括一装置基底303。在本实施例中，装置基底303可包括一本体300以及形成于本体300上的一金属化层302。在一实施例中，本体300可包括硅本体或其他半导体本体。再者，金属化层302可包括一介电材料层及位于介电材料层内的内连接结构(未绘示)。
在本实施例中，装置基底303的本体300内具有一感测装置301，其邻近于金属化层302的下表面。在一实施例中，感测装置301用以感测生物特征，且可包括一指纹辨识元件。在其他实施例中，感测装置301用以感测环境特征，且可包括一电容感测元件或其他适合的感测元件。
再者，装置基底303的金属化层302内具有一个或一个以上的导电垫304。通常位于金属化层302内的导电垫304可为一顶部金属层且露出于装置基底300的一表面(例如，金属化层302的上表面)。在一实施例中，感测装置301内的感测元件可通过金属化层302内的内连接结构而与导电垫304电性连接。
在一实施例中，导电垫304可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以单层导电层作为范例说明(如图2C所示)，且仅绘示出位于装置基底303内的两个导电垫304作为范例说明。
在本实施例中，晶片封装体20还包括一硬涂层308设置于装置基底303的表面上，且位于感测装置301正上方。硬涂层308作为感测装置301的保护层并露出装置基底303的导电垫304。在一实施例中，硬涂层308可包括一高硬度材料，且其硬度(即，摩氏(mohs)硬度)值不小于6。再者，硬涂层308可包括一高介电常数材料，且其介电常数为5以上。举例来说，硬涂层308可包括二甲基乙酰胺(dimethylacetamide,DMAC)、钛酸锶、二氧化钛或其他适合的高介电常数绝缘保护材料。
请参照图2A至2C，其绘示出根据本发明一实施例的晶片封装体20的不同中间制造阶段的剖面示意图。如图2A所示，提供一装置基底303，其包括一本体300以及形成于本体300上的金属化层302。在一实施例中，本体300可包括硅本体或其他半导体本体。再者，金属化层302可包括一介电材料层及位于介电材料层内的内连接结构(未绘示)。在一实施例中，装置基底303为一晶片。在另一实施例中，装置基底303为一晶圆，以利于进行晶圆级封装制程。在本实施例中，装置基底303包括多个晶片区。为简化图式及说明，此处仅绘示出单一晶片区中的装置基底303。
在本实施例中，晶片区中的装置基底303内具有一感测装置301及一个或一个以上的导电垫304。通常感测装置301位于本体300内且邻近于金属化层302的下表面。再者，导电垫304通常位于金属化层302内且可为一顶部金属层而邻近于金属化层302的上表面。在一实施例中，感测装置301内的感测元件(例如，一指纹辨识元件)可通过装置基底303内的内连线结构而与导电垫304电性连接。在一实施例中，导电垫304可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以单层导电层作为范例说明，且仅绘示出装置基底303内的两个导电垫304作为范例说明。
接着，在装置基底303的表面上覆盖一光阻材料层(未绘示)。之后，通过光学微影制程来图案化光阻材料层，以形成光阻图案层306。在本实施例中，光阻图案层306具有一开口306a露出装置基底303的表面且对应于装置基底303的感测装置301。在本实施例中，光阻图案层306用于后续进行硬涂层(其不易被蚀刻)图案化。
请参照图2B，在光阻图案层306上形成一硬涂层308并完全填满光阻图案层306的开口306a。光阻图案层306上方的硬涂层308的厚度约在5至30微米(μm)范围。在一实施例中，硬涂层308可包括一高硬度材料，且其硬度值(即，摩氏硬度)不小于6。再者，硬涂层308可包括一高介电常数材料，且其介电常数为5以上。举例来说，硬涂层308可包括二甲基乙酰胺(dimethylacetamide,DMAC)、钛酸锶、二氧化钛或其他适合的高介电常数绝缘保护材料。
请参照图2C，如先前所述，由于硬涂层308不易被蚀刻，因此利用光阻图案层306作为牺牲材料进行一掀离(lift-off)制程，以将位于光阻图案层306上方的硬涂层308的部分移除。举例来说，利用氧等离子体在硬涂层308内形成穿孔(未绘示)而露出位于硬涂层308下方的光阻图案层306。接着，利用湿式蚀刻经由上述孔洞去除光阻图案层306，使光阻图案层306上方的硬涂层308的部分也同时被移除，而留下位于感测装置301上方的硬涂层308的部分。余留的硬涂层308用以作为位于下方的感测装置301的保护层。
相较于图1所示的晶片封装体10，晶片封装体20的保护层(即，硬涂层308)是在进行打线制程及模塑制程之前利用掀离制程制作而成，因此形成的硬涂层308的厚度具有较佳的均匀性，进而维持或改善晶片封装体20的装置效能及可靠度。
请参照图3D，其绘示出根据本发明另一实施例的晶片封装体30的剖面示意图，其中相同于前述图2C的实施例的部件使用相同的标号并省略其说明。在本实施例中，晶片封装体30包括一装置基底303。如先前图2C的实施例所述，装置基底303可包括一本体300以及形成于本体300上的一金属化层302。装置基底303的本体300内具有一感测装置301，其邻近于金属化层302的下表面，且可包括一指纹辨识元件。装置基底303的金属化层302内具有一个或一个以上的导电垫304，其露出于装置基底300的一表面，且可通过金属化层302内的内连接结构(未绘示)而与感测装置301内的感测元件电性连接。
在一实施例中，导电垫304可为单层导电层或具有多层的导电层结构。为简化图式，此处仅以位于装置基底303内的两个单层导电垫304作为范例说明(如图3D所示)。
在本实施例中，晶片封装体30还包括一硬涂层308覆盖装置基底303的表面。不同于图2C的实施例，硬涂层308内具有多个开口对应于导电垫304且露出导电垫304。如先前图2C的实施例所述，硬涂层308可包括一高硬度材料，且其硬度值不小于6。再者，硬涂层308可包括一高介电常数材料，且其介电常数为5以上。举例来说，硬涂层308可包括二甲基乙酰胺(dimethylacetamide,DMAC)、钛酸锶、二氧化钛或其他适合的高介电常数绝缘保护材料。
在本实施例中，晶片封装体30还包括多个导电结构307，对应设置于硬涂层308的开口内而与导电垫304形成电性连接。再者，硬涂层308及导电结构307具有实质上平坦且彼此切齐的表面。举例来说，硬涂层308的上表面与导电结构307的上表面为共平面，而硬涂层308的下表面与导电结构307的下表面也可为共平面。在一实施例中，导电结构307包括金属凸块或金属柱体。再者，导电结构307可包括金、银、锡、铜或其合金。
在本实施例中，晶片封装体30还包括一封装基底400，具有导电垫400a位于其上。装置基底303装设于封装基底400上。在本实施例中，晶片封装体30还包括一封装层312及埋设于封装层312内的多个接线310。封装层312设置于封装基底400上，以密封硬涂层308及装置基底303。封装层312包括一开口，使对应于感测装置301的硬涂层308的部分露出于封装层312。在本实施例中，封装层312可包括环氧树脂、无机材料(例如，氧化硅、氮化硅、氮氧化硅、金属氧化物或前述的组合)、有机高分子材料(例如，聚酰亚胺树脂、苯环丁烯(butylcyclobutene,BCB)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物、或丙烯酸酯(acrylates))、或其他适合的绝缘材料。
请参照图3A至3D，其绘示出根据本发明另一实施例的晶片封装体30的不同中间制造阶段的剖面示意图，其中相同于前述图2A至2C的实施例的部件使用相同的标号并省略其说明。如图3A所示，提供一装置基底303，其包括一本体300以及形成于本体300上的金属化层302。在一实施例中，装置基底303为一晶片。在另一实施例中，装置基底303为一晶圆，以利于进行晶圆级封装制程。在本实施例中，装置基底303包括多个晶片区。为简化图式及说明，此处仅绘示出单一晶片区中的装置基底303。
在本实施例中，晶片区中的装置基底303的本体300内具有一感测装置301，其邻近于金属化层302的下表面，且可包括一指纹辨识元件。装置基底303的金属化层302内具有一个或一个以上的导电垫304，其露出于装置基底300的一表面，且可通过金属化层302内的内连接结构(未绘示)而与感测装置301内的感测元件电性连接。为简化图式，此处仅绘示出装置基底303内的两个单层导电垫304作为范例说明。
接着，于每一导电垫304上对应形成一导电结构307，以作为导电垫304的延伸部或导电通道。在一实施例中，导电结构307可包括金属凸块或金属柱体。再者，导电结构307可包括金、银、锡、铜或其合金。在一实施例中，可通过植球(ball bumping)制程形成导电结构307。在其他实施例中，也可利用电镀制程、溅镀制程或其他适合的沉积制程形成导电结构307。
请参照图3B，于装置基底300的表面上覆盖一硬涂层308，且完全覆盖位于每一导电垫304上的导电结构307。亦即，导电结构307完全埋入硬涂层308内而未露出于硬涂层308的表面。在一实施例中，可通过印刷、涂布制程形成硬涂层308。如先前所述，硬涂层308可包括一高硬度材料，且其硬度值不小于6。再者，硬涂层308可包括一高介电常数材料，且其介电常数为5以上。举例来说，硬涂层308可包括二甲基乙酰胺(dimethylacetamide,DMAC)、钛酸锶、二氧化钛或其他适合的高介电常数绝缘保护材料。
请参照图3C，对硬涂层308进行薄化或平坦化制程，以露出位于每一导电垫304上的导电结构307。举例来说，薄化制程可包括化学机械研磨(chemical mechanicalpolishing,CMP)制程、机械研磨(mechanical grinding)制程或其他适合的平坦化制程。在进行薄化制程之后，硬涂层308及导电结构307具有实质上平坦且彼此切齐的表面。举例来说，硬涂层308的上表面与导电结构307的上表面为共平面。
请参照图3D，提供一封装基底400，其具有导电垫400a。图3C的结构装设于封装基底400上。接着，进行打线接合制程，使多个接线310电性连接于硬涂层308内的导电结构307与封装基底400的导电垫400a之间。之后，进行一模塑制程，以在封装基底400上形成一封装层312，其密封硬涂层308、装置基底303及接线310。封装层312包括一开口，使对应于感测装置301的硬涂层308的部分露出于封装层312。
根据图3A至3D的实施例，由于晶片封装体30的保护层(即，硬涂层308)是在进行打线制程及模塑制程之前利用平坦化制程制作而成，因此相较于图1所示的晶片封装体10，硬涂层308的厚度具有较佳的均匀性，进而维持或改善晶片封装体20的装置效能及可靠度。再者，如以上所述，由于硬涂层308利用平坦化制程制作而成，因此无需使用任何光学微影制程及掀离制程。相较于图2A至图2C所示的晶片封装体20的制作，可进一步简化制程及降低制造成本。再者，由于硬涂层308与导电结构307为实质上共平面，因此有助于后续对晶片封装体30进行打线制程及模塑制程。
以上所述仅为本发明较佳实施例，然其并非用以限定本发明的范围，任何熟悉本项技术的人员，在不脱离本发明的精神和范围内，可在此基础上做进一步的改进和变化，因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (19)

1.一种晶片封装体，其特征在于，包括：
装置基底，其包括感测装置及露出于该装置基底的表面的多个导电垫；
硬涂层，覆盖该装置基底的该表面，且具有分别露出该多个导电垫的多个开口；以及
多个导电结构，对应设置于该多个开口内，且电性连接至该多个导电垫，其中该硬涂层及该多个导电结构具有平坦且彼此切齐的表面。
2.根据权利要求1所述的晶片封装体，其特征在于，该感测装置包括指纹辨识元件。
3.根据权利要求1所述的晶片封装体，其特征在于，该硬涂层包括高硬度材料，且该硬涂层的硬度值不小于6。
4.根据权利要求1所述的晶片封装体，其特征在于，该硬涂层包括高介电常数材料，且该硬涂层的介电常数为5以上。
5.根据权利要求1所述的晶片封装体，其特征在于，该硬涂层包括二甲基乙酰胺。
6.根据权利要求1所述的晶片封装体，其特征在于，该多个导电结构包括金属凸块或金属柱体。
7.根据权利要求6所述的晶片封装体，其特征在于，该多个导电结构包括金、银、锡、铜或其合金。
8.根据权利要求1所述的晶片封装体，其特征在于，还包括：
封装基底，装设于该装置基底下方；
封装层，设置于该封装基底上，以密封该硬涂层及该装置基底，其中该硬涂层中对应于该感测装置的部分露出于该封装层；以及
多个接线，埋设于该封装层内，且电性连接于该多个导电结构与该封装基底之间。
9.一种晶片封装体的制造方法，其特征在于，包括：
提供装置基底，其包括感测装置及露出于该装置基底的表面的多个导电垫；
于每一该多个导电垫上对应形成导电结构；
于该装置基底的该表面上覆盖一硬涂层，且该硬涂层完全覆盖位于每一该多个导电垫上的该导电结构；以及
对该硬涂层进行薄化，以露出位于每一该多个导电垫上的该导电结构，且使该硬涂层及位于每一该多个导电垫上的该导电结构具有平坦且彼此切齐的表面。
10.根据权利要求9所述的晶片封装体的制造方法，其特征在于，该感测装置包括指纹辨识元件。
11.根据权利要求9所述的晶片封装体的制造方法，其特征在于，该硬涂层包括高硬度材料，且该硬涂层的硬度值不小于6。
12.根据权利要求9所述的晶片封装体的制造方法，其特征在于，该硬涂层包括高介电常数材料，且该硬涂层的介电常数为5以上。
13.根据权利要求9所述的晶片封装体的制造方法，其特征在于，该硬涂层包括二甲基乙酰胺。
14.根据权利要求9所述的晶片封装体的制造方法，其特征在于，该多个导电结构包括金属凸块或金属柱体。
15.根据权利要求14所述的晶片封装体的制造方法，其特征在于，该多个导电结构包括金、银、锡、铜或其合金。
16.根据权利要求9所述的晶片封装体的制造方法，其特征在于，利用植球制程形成该多个导电结构。
17.根据权利要求9所述的晶片封装体的制造方法，其特征在于，利用电镀制程形成该多个导电结构。
18.根据权利要求9所述的晶片封装体的制造方法，其特征在于，对该硬涂层进行薄化的步骤包括实施化学机械研磨。
19.根据权利要求9所述的晶片封装体的制造方法，其特征在于，还包括：
将该装置基底装设于封装基底上方；
形成多个接线，使该多个接线电性连接于该多个导电结构与该封装基底之间；以及
形成封装层于该封装基底上，以密封该硬涂层、该装置基底及该多个接线，其中该硬涂层中对应于该感测装置的部分露出于该封装层。
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