TW201301414A - 為了絕緣層的局部平坦化而在半導體晶粒附近形成保護結構之半導體元件及方法 - Google Patents

為了絕緣層的局部平坦化而在半導體晶粒附近形成保護結構之半導體元件及方法 Download PDF

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TW201301414A
TW201301414A TW100132555A TW100132555A TW201301414A TW 201301414 A TW201301414 A TW 201301414A TW 100132555 A TW100132555 A TW 100132555A TW 100132555 A TW100132555 A TW 100132555A TW 201301414 A TW201301414 A TW 201301414A
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semiconductor
semiconductor die
protective pattern
insulating layer
conductive layer
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TW100132555A
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TWI523128B (zh
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Yao-Jian Lin
Xia Feng
Kang Chen
Jian-Min Fang
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Stats Chippac Ltd
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Abstract

一半導體晶圓係包含複數個藉由一切割道分開的半導體晶粒。一接觸墊係形成在該半導體晶粒的一作用表面之上。一保護圖案係形成在該半導體晶粒的該作用表面之上且在該半導體晶粒的該接觸墊及切割道之間。該保護圖案係包含一分段的金屬層或是複數個平行的分段的金屬層。一絕緣層係形成在該作用表面、接觸墊以及保護圖案之上。該絕緣層的一部分係被移除以露出該接觸墊。該保護圖案係減低在該半導體晶粒的該接觸墊及切割道之間的絕緣層的侵蝕。該保護圖案在該半導體晶粒的角落處可以是有角度的或是依循該接觸墊的一輪廓。該保護圖案可形成在該半導體晶粒的角落處。

Description

為了絕緣層的局部平坦化而在半導體晶粒附近形成保護結構之半導體元件及方法
本發明係大致有關於半導體元件，並且更具體而言係有關於一種為了一絕緣層的局部平坦化而在一半導體晶粒附近形成一保護結構之半導體元件及方法。
半導體元件係常見於現代的電子產品中。半導體元件係在電氣構件的數目及密度上變化。離散的半導體元件一般包含一類型的電氣構件，例如，發光二極體(LED)、小信號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(MOSFET)。集積的半導體元件通常包含數百到數百萬個電氣構件。集積的半導體元件的例子係包含微控制器、微處理器、電荷耦合元件(CCD)、太陽能電池、以及數位微鏡元件(DMD)。
半導體元件係執行廣範圍的功能，例如，信號處理、高速的計算、傳送及接收電磁信號、控制電子元件、轉換太陽光成為電力、以及產生用於電視顯示器的視覺投影。半導體元件係見於娛樂、通訊、電力轉換、網路、電腦以及消費者產品的領域中。半導體元件亦見於軍事的應用、航空、汽車、工業用的控制器、以及辦公室設備。
半導體元件係利用半導體材料的電氣特性。半導體材料的原子結構係容許其導電度能夠藉由一電場或基極電流的施加或是透過摻雜的製程加以操縱。摻雜係將雜質帶入半導體材料中，以操縱及控制半導體元件的導電度。
一半導體元件係包含主動及被動的電性結構。包含雙載子及場效電晶體的主動結構係控制電流的流動。藉由改變摻雜的程度以及一電場或基極電流的施加，該電晶體不是提升、就是限制電流的流動。包含電阻器、電容器及電感器的被動結構係在電壓及電流之間產生執行各種電氣功能所必要的一種關係。該被動及主動結構係電連接以形成電路，此係使得該半導體元件能夠執行高速的計算及其它有用的功能。
半導體元件一般是利用兩個複雜的製程，亦即，前端製造及後端製造來加以製造，每個製造潛在涉及數百道步驟。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。每個晶粒通常是相同的並且包含藉由電連接主動及被動構件所形成的電路。後端製造係牽涉到從完成的晶圓單粒化(singulating)個別的晶粒並且封裝該晶粒以提供結構的支撐以及環境的隔離。
半導體製造的一目標是產出較小的半導體元件。較小的元件通常消耗較低的功率，具有較高的效能，並且可以更有效率地加以生產。此外，較小的半導體元件具有一較小的覆蓋區，此係較小的終端產品所期望的。較小的晶粒尺寸可藉由在產生具有較小且較高密度的主動及被動構件之晶粒的前端製程中的改良來達成。後端製程可以藉由在電氣互連及封裝材料上的改良來產生具有較小覆蓋區的半導體元件封裝。
圖1係展示一習知的半導體晶圓10的一部分，其中複數個半導體晶粒12是藉由切割道14分開的。接觸墊16係形成在半導體晶粒12的作用表面之上。一保護層18係形成在該作用表面及接觸墊16之上。保護層18的一部分係被移除以露出用於電氣互連的接觸墊16。然而，在顯影製程期間，保護層18可能會被侵蝕且變成非所要地薄，特別是在半導體晶粒12及半導體晶圓10的邊緣及角落處。圖2係展示保護層18在晶圓10或半導體晶粒12的角落或邊緣20的侵蝕。該薄的保護層18可能會造成缺陷並且降低半導體晶粒12在其最後的封裝配置的可靠度。
對於在一半導體晶粒的一作用表面之上的保護層之減低的侵蝕存在著需求。於是，在一實施例中，本發明係一種製造一半導體元件之方法，其係包括以下步驟：提供一具有複數個藉由一切割道分開的半導體晶粒的半導體晶圓，在該半導體晶粒的一作用表面之上形成一接觸墊，在該半導體晶粒的該作用表面之上且在該半導體晶粒的該接觸墊及切割道之間形成一保護圖案，在該作用表面、接觸墊以及保護圖案之上形成一絕緣層，以及移除該絕緣層的一部分以露出該接觸墊。該保護圖案係減低在該半導體晶粒的該接觸墊及切割道之間的該絕緣層的侵蝕。
在另一實施例中，本發明係一種製造一半導體元件之方法，其係包括以下步驟：提供一半導體晶圓，在該半導體晶圓的一表面之上形成一導電層，在該半導體晶圓的表面之上且在該導電層以及該半導體晶圓的一邊緣之間形成一保護圖案，在該半導體晶圓的表面、導電層以及保護圖案之上形成一絕緣層，以及移除該絕緣層的一部分以露出該導電層的一部分。該保護圖案係維持在該導電層以及該半導體晶圓的邊緣之間的絕緣層。
在另一實施例中，本發明係一種製造一半導體元件之方法，其係包括以下步驟：提供一半導體晶粒，在該半導體晶粒的一表面之上形成一導電層，在該半導體晶粒的表面之上相鄰該導電層形成一保護圖案，以及在該半導體晶粒的表面、導電層以及保護圖案之上形成一絕緣層。該保護圖案係維持相鄰該導電層的絕緣層。
在另一實施例中，本發明係一種半導體元件，其係包括一半導體晶粒以及形成在該半導體晶粒的一表面之上的導電層。一保護圖案係形成在該半導體晶圓的表面之上且相鄰該導電層。一絕緣層係形成在該半導體晶粒的表面、導電層以及保護圖案之上。該保護圖案係維持相鄰該導電層的絕緣層。
本發明係在以下參考該些圖式的說明中，以一或多個實施例來加以描述，其中相同的元件符號係代表相同或類似的元件。儘管本發明係以用於達成本發明之目的之最佳模式來加以描述，但熟習此項技術者將會體認到的是，其係欲涵蓋可內含在藉由所附的申請專利範圍及其由以下的揭露內容及圖式所支持的等同項所界定的本發明的精神與範疇內的替換物、修改以及等同物。
半導體元件一般是利用兩個複雜的製程：前端製造及後端製造來加以製造。前端製造係牽涉到複數個晶粒在一半導體晶圓的表面上的形成。在該晶圓上的每個晶粒係包含電連接以形成功能電路的主動及被動電氣構件。例如是電晶體及二極體的主動電氣構件係具有控制電流的流動之能力。例如是電容器、電感器、電阻器及變壓器的被動電氣構件係產生執行電路功能所必要的電壓及電流之間的一種關係。
被動及主動構件係藉由一系列的製程步驟而形成在半導體晶圓的表面之上，該些製程步驟包含摻雜、沉積、微影、蝕刻及平坦化。摻雜係藉由例如是離子植入或熱擴散的技術以將雜質帶入半導體材料中。該摻雜製程係修改主動元件中的半導體材料的導電度，其係轉換該半導體材料成為絕緣體、導體、或是響應於一電場或基極電流來動態地改變該半導體材料的導電度。電晶體係包含具有不同類型及程度的摻雜的區域，該些區域係以使得該電晶體在電場或基極電流的施加時提升或限制電流的流動所必要的來加以配置。
主動及被動構件係藉由具有不同電氣特性的材料層來加以形成。該些層可藉由各種沉積技術來形成，該技術部分是由被沉積的材料類型來決定的。例如，薄膜沉積可能牽涉到化學氣相沉積(CVD)、物理氣相沉積(PVD)、電解的電鍍以及無電的電鍍製程。每個層一般是被圖案化，以形成主動構件、被動構件或是構件間的電連接的部分。
該些層可利用微影而被圖案化，微影係牽涉到光敏材料(例如，光阻)在待被圖案化的層之上的沉積。一圖案係利用光從一光罩轉印至光阻。該光阻圖案遭受到光的部分係利用一溶劑來移除，露出下面待被圖案化的層的部分。該光阻的剩餘部分係被移除，留下一圖案化的層。或者是，某些類型的材料係藉由利用例如是無電的電鍍及電解的電鍍的技術來直接將該材料沉積到該些區域或是沉積到由一先前的沉積/蝕刻製程所形成的空孔中而被圖案化。
在一現有的圖案之上沉積一材料薄膜可能會擴大下面的圖案並且產生一非均勻平坦的表面。一均勻平坦的表面是產生較小且更緊密聚集的主動及被動構件所需的。平坦化可被利用來從晶圓的表面移除材料並且產生一均勻平坦的表面。平坦化係牽涉到利用一拋光墊來拋光晶圓的表面。一研磨劑材料及腐蝕性化學品係在拋光期間被加到晶圓的表面。該研磨劑的機械性作用以及該化學品的腐蝕性作用的組合係移除任何不規則的表面構形，產生一均勻平坦的表面。
後端製造係指切割或單粒化完成的晶圓成為個別的晶粒並且接著為了結構的支撐及環境的隔離來封裝該晶粒。為了單粒化晶粒，晶圓係沿著該晶圓的非功能區域(稱為切割道或劃線)來被劃線且截斷。該晶圓係利用一雷射切割工具或鋸刀而被單粒化。在單粒化之後，該個別的晶粒係被安裝到一封裝基板，該封裝基板係包含用於和其它系統構件互連的接腳或接觸墊。形成在半導體晶粒之上的接觸墊係接著連接至該封裝內的接觸墊。該些電連接可以利用銲料凸塊、柱形凸塊、導電膏、或是引線接合來做成。一封裝材料或是其它模製材料係沉積在該封裝之上，以提供實體支撐及電氣隔離。該完成的封裝係接著被插入一電氣系統中，並且使得該半導體元件的功能為可供其它系統構件利用的。
圖3係描繪具有複數個安裝於其表面上之半導體封裝的晶片載體基板或印刷電路板(PCB)52之電子元件50。視應用而定，電子元件50可具有一種類型之半導體封裝或多種類型之半導體封裝。不同類型之半導體封裝係為了說明之目的而展示於圖3中。
電子元件50可以是一使用該些半導體封裝以執行一或多種電功能之獨立的系統。或者，電子元件50可以是一較大系統之子構件。舉例而言，電子元件50可以是行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)、或是其它電子通訊元件的一部份。或者是，電子元件50可以是一可插入電腦中之顯示卡、網路介面卡或其它信號處理卡。該半導體封裝可包括微處理器、記憶體、特殊應用積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散元件或其它半導體晶粒或電氣構件。小型化及重量減輕是這些產品能夠被市場接受所不可少的。在半導體元件間的距離必須縮短以達到更高的密度。
在圖3中，PCB 52係提供一般的基板以供安裝在該PCB上之半導體封裝的結構支撐及電氣互連。導電的信號線路54係利用蒸鍍、電解的電鍍、無電的電鍍、網版印刷、或其它適合的金屬沉積製程而被形成在PCB 52的一表面之上或是在層內。信號線路54提供在半導體封裝、安裝的構件、以及其它外部的系統構件的每一個之間的電通訊。線路54亦提供電源及接地連接給每個半導體封裝。
在某些實施例中，一半導體元件具有兩個封裝層級。第一層級的封裝是一種用於將半導體晶粒機械及電氣地附接至一中間載體的技術。第二層級的封裝係牽涉到將該中間載體機械及電氣地附接至PCB。在其它實施例中，一半導體元件可以只有該第一層級的封裝，其中晶粒是直接機械及電氣地安裝到PCB上。
為了說明之目的，包含引線接合封裝56及覆晶58之數種類型的第一層級的封裝係被展示在PCB 52上。此外，包含球狀柵格陣列(BGA)60、凸塊晶片載體(BCC)62、雙排型封裝(DIP)64、平台柵格陣列(LGA)66、多晶片模組(MCM)68、四邊扁平無引腳封裝(QFN)70及四邊扁平封裝72之數種類型的第二層級的封裝係被展示安裝在PCB 52上。視系統需求而定，以第一及第二層級的封裝類型的任意組合來組態的半導體封裝的任何組合及其它電子構件可連接至PCB 52。在某些實施例中，電子元件50包含單一附接的半導體封裝，而其它實施例需要多個互連的封裝。藉由在單一基板之上組合一或多個半導體封裝，製造商可將預製的構件納入電子元件及系統中。由於半導體封裝包括複雜的功能，因此可使用較便宜構件及流線化製程來製造電子元件。所產生的元件不太可能發生故障且製造費用較低，從而降低消費者成本。
圖4a-4c係展示範例的半導體封裝。圖4a係描繪安裝在PCB 52上的DIP 64之進一步的細節。半導體晶粒74係包括一含有類比或數位電路的作用區域，該些類比或數位電路係被實施為形成在晶粒內之主動元件、被動元件、導電層及介電層，並且根據該晶粒的電設計而電互連。例如，該電路可包含形成在半導體晶粒74的作用區域內之一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸墊76是一或多個層的導電材料，例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)或銀(Ag)，並且電連接至形成在半導體晶粒74內之電路元件。在DIP 64的組裝期間，半導體晶粒74係利用一金矽共晶層或例如是熱環氧樹脂的黏著劑材料而被安裝至一中間載體78。封裝主體係包含一種例如是聚合物或陶瓷的絕緣封裝材料。導線80及引線接合82係在半導體晶粒74及PCB 52之間提供電互連。封裝材料84係為了環境保護而沉積在該封裝之上以防止濕氣及微粒進入該封裝且污染晶粒74或引線接合82。
圖4b係描繪安裝在PCB 52上之BCC 62的進一步細節。半導體晶粒88係利用一種底膠填充(underfill)或是環氧樹脂黏著材料92而被安裝在載體90之上。引線接合94係在接觸墊96及98之間提供第一層級的封裝互連。模製化合物或封裝材料100係沉積在半導體晶粒88及引線接合94之上以提供實體支撐及電氣隔離給該元件。接觸墊102係利用一例如是電解的電鍍或無電的電鍍之合適的金屬沉積製程而被形成在PCB 52的一表面之上以避免氧化。接觸墊102係電連接至PCB 52中的一或多個導電信號線路54。凸塊104係形成在BCC 62的接觸墊98以及PCB 52的接觸墊102之間。
在圖4c中，半導體晶粒58係以覆晶型第一層級的封裝方式面向下安裝到中間載體106。半導體晶粒58的作用區域108係包含類比或數位電路，該些類比或數位電路係被實施為根據該晶粒的電設計所形成的主動元件、被動元件、導電層及介電層。例如，該電路可包含一或多個電晶體、二極體、電感器、電容器、電阻器以及作用區域108內之其它電路元件。半導體晶粒58係透過凸塊110電氣及機械地連接至載體106。
BGA 60係以BGA型第二層級的封裝方式利用凸塊112電氣及機械地連接至PCB 52。半導體晶粒58係透過凸塊110、信號線114及凸塊112電連接至PCB 52中的導電信號線路54。一種模製化合物或封裝材料116係沉積在半導體晶粒58及載體106之上以提供實體支撐及電氣隔離給該元件。該覆晶半導體元件係提供從半導體晶粒58上的主動元件到PCB 52上的導電跡線之短的導電路徑，以便縮短信號傳遞距離、降低電容以及改善整體電路效能。在另一實施例中，半導體晶粒58可在無中間載體106的情況下，利用覆晶型第一層級的封裝直接機械及電連接至PCB 52。
圖5a係展示一具有一種例如是矽、鍺、砷化鎵、磷化銦或矽碳化物的主體基板材料122以供結構支撐的半導體晶圓120。如上所述，複數個半導體晶粒或構件124係形成在晶圓120上且藉由如上所述的切割道126分開。
圖5b係展示半導體晶圓120的一部份的橫截面圖。每個半導體晶粒124係具有一包含類比或數位電路的作用表面130，該類比或數位電路被實施為形成在該晶粒內且根據該晶粒的電設計及功能電互連的主動元件、被動元件、導電層以及介電層。例如，該電路可包含一或多個電晶體、二極體以及其它形成在作用表面130內之電路元件以實施類比電路或數位電路，例如數位信號處理器(DSP)、ASIC、記憶體或是其它信號處理電路。半導體晶粒124亦可包含整合被動元件(IPD)，例如電感器、電容器及電阻器，以供RF信號處理使用。在一實施例中，半導體晶粒124是一覆晶類型的半導體晶粒。
一導電層132係利用PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程而形成在作用表面130以及再分布(redistribution)介電質保護層之上。導電層132可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag、或是其它合適的導電材料。導電層132的一部分係運作為接觸墊134，該些接觸墊134係電連接至作用表面130上的電路，並且電連接至該下一層級的封裝互連，例如，形成接觸墊134上的凸塊。
圖5c係展示半導體晶圓120中構成兩個相鄰的半導體晶粒124的一部分之平面圖。接觸墊134可以形成在半導體晶粒124的一周邊附近並且在該半導體晶粒的內部。導電層132的另一部分係提供形成在作用表面130之上並且電連接至接觸墊134以供信號繞線至該作用表面上的電路之信號線路136。
一保護及平坦化金屬圖案138係利用圖案化及PVD、CVD、電解的電鍍、無電的電鍍製程或是其它合適的金屬沉積製程以形成在作用表面130之上。更明確地說，保護層138係沿著每個半導體晶粒124之相鄰周邊的接觸墊134的邊緣，亦即，沿著切割道126或是部分在切割道126之上來形成，以平坦化該邊緣或角落墊134附近的保護層140並且平衡在該些墊之上的應力分布以便於改善可靠度。保護層138可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的材料。保護圖案138係在和導電層132相同的製程序列期間被圖案化及沉積。保護圖案138係和接觸墊134及線路136以及作用表面130上的電路電氣隔離開。
在一實施例中，保護圖案138a是一大致直的仿真(dummy)金屬線路圖案，其係在半導體晶粒124的一周邊附近並且在周邊的接觸墊134之外且相鄰周邊的接觸墊134，其在半導體晶粒的角落處具有角度。保護圖案138a之直的線路圖案可以視需要而為斷開或分段的，以避免和信號線路136或是作用表面130的其它對電敏感的區域電氣接觸。此外，保護圖案138b係以一種多邊形或是圓形的形狀(例如，三角形)而被設置在半導體晶粒124的角落處，以依循保護圖案138a的角度。
一絕緣層或保護層140係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆、疊層或是熱氧化而形成在作用表面130、導電層132以及保護圖案138之上。該絕緣層140可以是一或多個層的二氧化矽(SiO2)、矽氮化物(Si3N4)、氮氧化矽(SiON)、五氧化二鉭(Ta2O5)、鋁氧化物(Al2O3)、聚合物介電質(例如，聚醯亞胺、PBO、WPR、以聚合物基礎的較低溫固化聚合物)、銲料光罩、或是其它具有類似的絕緣性質及結構性質的適當的材料。絕緣層140的一部分係藉由一蝕刻製程而被移除以露出接觸墊134。
保護圖案138係提供在半導體晶粒124的邊緣附近(例如，在區域142中)的絕緣層140之改良的局部平坦化。換言之，保護圖案138係在顯影期間減低侵蝕並且維持絕緣層140的厚度，使得區域142中的絕緣層140具有和該半導體晶粒124的內部部分實質相同的厚度。由於保護圖案138a及138b的支持，在區域142中的絕緣層140係抵擋在曝光後的顯影期間的侵蝕。此外，保護圖案138係有助於半導體晶粒124的方位識別以及局部應力消除。
在圖5d中，半導體晶圓120係利用鋸刀或雷射切割工具139透過切割道126而被單粒化為個別的半導體晶粒124。半導體晶粒124可以安裝到一基板或是堆疊在任意的封裝配置中。例如，圖6係展示在晶圓級晶片尺寸封裝(WLCSP)147中，半導體晶粒124係利用凸塊144安裝到基板143且被封裝材料145所覆蓋。保護圖案138係維持整個半導體晶粒124(包含其邊緣)的絕緣層140的均勻厚度及覆蓋。
圖7a是該保護圖案從圖5b延伸的另一實施例的平面圖，其中導電層132形成在作用表面130之上作為接觸墊134及信號線路136。一保護圖案146係利用圖案化及PVD、CVD、電解的電鍍、無電的電鍍製程或是其它合適的金屬沉積製程以形成在作用表面130之上。更明確地說，保護圖案146係沿著每個半導體晶粒124之相鄰周邊的接觸墊134的邊緣，亦即，沿著切割道126或是部分在切割道126之上，並且沿著半導體晶圓120的邊緣來形成。保護圖案146可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的材料。保護圖案146可以在和導電層132相同的製程序列期間被圖案化及沉積。保護圖案146係和接觸墊134及線路136以及作用表面130上的電路電氣隔離開。
在此例中，保護圖案146a是一仿真金屬線路圖案，其係在半導體晶粒124的一周邊附近並且在周邊的接觸墊134之外且相鄰周邊的接觸墊134。保護圖案146a係依循接觸墊134的輪廓。例如，在圓形的接觸墊134附近的保護圖案146a是圓形的。保護圖案146a的線路圖案可以視需要而為斷開或分段的，以避免和信號線路136或是作用表面130的其它對電敏感的區域電氣接觸。此外，保護圖案146b係以任意規則或不規則的形狀(例如，十字形、鑽石形、或是多邊形)被設置在半導體晶粒124的角落處。
一絕緣層或保護層148係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆或是熱氧化而形成在作用表面130、導電層132以及保護圖案146之上。該絕緣層140可以是一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似的絕緣性質及結構性質的適當的材料。絕緣層148的一部分係藉由一蝕刻製程而被移除以露出接觸墊134。
如同圖7b中所示，保護圖案146係提供在半導體晶粒124的邊緣附近(例如，在區域150中)的絕緣層140之改良的局部平坦化。換言之，保護圖案146係在顯影期間減低侵蝕並且維持絕緣層148的厚度，使得區域150中的絕緣層148具有和該半導體晶粒124的內部部分實質相同的厚度。由於保護圖案146a及146b的支持，在區域150中的絕緣層148係抵擋在曝光後的顯影期間的侵蝕。此外，保護圖案146係有助於半導體晶粒124的方位識別以及局部應力消除。
圖8a是該保護圖案從圖5b延伸的另一實施例的平面圖，其中導電層132形成在作用表面130之上作為接觸墊134及信號線路136。一保護圖案152係利用圖案化及PVD、CVD、電解的電鍍、無電的電鍍製程或是其它合適的金屬沉積製程以形成在作用表面130之上。更明確地說，保護圖案152係沿著每個半導體晶粒124之相鄰周邊的接觸墊134的邊緣，亦即，沿著切割道126或是部分在切割道126之上，並且沿著半導體晶圓120的邊緣來形成。保護圖案152可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的材料。保護圖案152可以在和導電層132相同的製程序列期間被圖案化及沉積。保護圖案152係和接觸墊134及線路136以及作用表面130上的電路電氣隔離開。
在此例中，保護圖案152a是複數個直的平行的仿真金屬線路圖案，其係在半導體晶粒124的一周邊附近並且在周邊的接觸墊134之外且相鄰周邊的接觸墊134，其在半導體晶粒的角落處具有角度。保護圖案152a之直的平行的線路圖案可以視需要而為斷開或分段的，以避免和信號線路136或是作用表面130的其它對電敏感的區域電氣接觸。此外，保護圖案152b係以一種多邊形或是圓形的形狀(例如，三角形)而被設置在半導體晶粒124的角落處，以依循保護圖案152a的角度。
一絕緣層或保護層154係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆或是熱氧化而形成在作用表面130、導電層132以及保護圖案152之上。該絕緣層154可以是一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似的絕緣性質及結構性質的適當的材料。絕緣層154的一部分係藉由一蝕刻製程而被移除以露出接觸墊134。
如同圖8b中所示，保護圖案152係提供在半導體晶粒124的邊緣附近(例如，在區域156中)的絕緣層154之改良的局部平坦化。換言之，保護圖案152係在顯影期間減低侵蝕並且維持絕緣層154的厚度，使得區域156中的絕緣層154具有和半導體晶粒124的內部部分實質相同的厚度。由於保護圖案152a及152b的支持，在區域156中的絕緣層154係抵擋在曝光後的顯影期間的侵蝕。此外，保護圖案152係有助於半導體晶粒124的方位識別以及局部應力消除。
圖9係展示一利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆或熱氧化而形成在半導體晶粒124的作用表面130及導電層132之上的絕緣層或保護層160的另一實施例。該絕緣層160可以是一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似的絕緣性質及結構性質的適當的材料。絕緣層160的一部分係藉由一蝕刻製程而被移除以露出接觸墊134。
一絕緣層或保護層162係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆或熱氧化而形成在絕緣層160以及露出的接觸墊134之上。該絕緣層162可以是一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似的絕緣性質及結構性質的適當的材料。絕緣層162的一部分係藉由一蝕刻製程而被移除以露出接觸墊134。
一導電層或RDL 164係形成在絕緣層162及接觸墊134之上。一保護圖案166係利用圖案化以及PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程而形成在絕緣層162之上。保護圖案166可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的材料。保護圖案166可以在和導電層164相同的製程序列期間被圖案化及沉積。保護圖案166係和導電層164電氣隔離開。
一絕緣層或保護層168係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆或熱氧化而形成在絕緣層162及導電層164、以及保護圖案166之上。該絕緣層168可以是一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似的絕緣性質及結構性質的適當的材料。絕緣層168的一部分係藉由一蝕刻製程而被移除以露出導電層164。凸塊170係形成在露出的導電層164之上。該絕緣層168可以具有一指定的開口以界定該切割道。
保護圖案166係提供絕緣層168之改良的局部平坦化。換言之，由於該保護圖案的支持，保護圖案166係在顯影期間減低侵蝕並且維持絕緣層168的厚度。
圖10係展示具有一封裝材料172形成在半導體晶粒124之上作為一展開形式晶圓級晶片尺寸封裝(Fo-WLCSP)的一基板之另一實施例。一絕緣層或保護層174係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆或熱氧化而形成在半導體晶粒124的作用表面130及導電層132之上。該絕緣層174可以是一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似的絕緣性質及結構性質的適當的材料。絕緣層174的一部分係藉由一蝕刻製程而被移除以露出接觸墊134。
一絕緣層或保護層176係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆或熱氧化而形成在絕緣層174以及露出的接觸墊134之上。該絕緣層176可以是一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似的絕緣性質及結構性質的適當的材料。絕緣層176的一部分係藉由一蝕刻製程而被移除以露出接觸墊134。
一導電層或RDL 178係形成在絕緣層176及接觸墊134之上。一保護圖案180係利用圖案化以及PVD、CVD、電解的電鍍、無電的電鍍製程、或是其它合適的金屬沉積製程而形成在絕緣層176之上。保護圖案180可以是一或多個層的Al、Cu、Sn、Ni、Au、Ag、或是其它適當的材料。保護圖案180可以在和導電層178相同的製程序列期間被圖案化及沉積。保護圖案180係和導電層178電氣隔離開。
一絕緣層或保護層182係利用PVD、CVD、印刷、旋轉塗覆、噴霧塗覆或熱氧化而形成在絕緣層176及導電層178、以及保護圖案180之上。該絕緣層182可以是一或多個層的SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是其它具有類似的絕緣性質及結構性質的適當的材料。絕緣層182的一部分係藉由一蝕刻製程而被移除以露出導電層178。凸塊184係形成在露出的導電層178之上。
保護圖案180係提供絕緣層182之改良的局部平坦化。換言之，由於該保護圖案的支持，保護圖案180係在顯影期間減低侵蝕並且維持絕緣層182的厚度。
儘管本發明的一或多個實施例已經詳細地描述，本領域技術人員將會體認到可在不脫離本發明如以下申請專利範圍中闡述的範疇下，對那些實施例進行修改及改編。
10．．．半導體晶圓
12．．．半導體晶粒
14．．．切割道
16．．．接觸墊
18．．．保護層
20．．．邊緣
50．．．電子元件
52．．．印刷電路板(PCB)
54．．．信號線路
56．．．封裝
58．．．覆晶
60．．．球狀柵格陣列(BGA)
62．．．凸塊晶片載體(BCC)
64．．．雙排型封裝(DIP)
66．．．平台柵格陣列(LGA)
68．．．多晶片模組(MCM)
70．．．四邊扁平無引腳封裝(QFN)
72．．．四邊扁平封裝
74．．．半導體晶粒
76．．．接觸墊
78．．．中間載體
80．．．導線
82．．．引線接合
84．．．封裝材料
88．．．半導體晶粒
90．．．載體
92．．．底膠填充(環氧樹脂黏著材料)
94．．．引線接合
96、98．．．接觸墊
100．．．模製化合物(封裝材料)
102．．．接觸墊
104．．．凸塊
106．．．中間載體
108．．．作用區域
110、112．．．凸塊
114．．．信號線
116．．．模製化合物(封裝材料)
120．．．半導體晶圓
122．．．主體基板材料
124．．．半導體晶粒(構件)
126．．．切割道
130．．．作用表面
132．．．導電層
134．．．接觸墊
136．．．信號線路
138．．．保護及平坦化金屬圖案(保護層)
138a、138b．．．保護圖案
139．．．鋸刀(雷射切割工具)
140．．．保護層(絕緣層)
142．．．區域
143．．．基板
144．．．凸塊
145．．．封裝材料
146．．．保護圖案
146a、146b．．．保護圖案
147．．．晶圓級晶片尺寸封裝(WLCSP)
148．．．絕緣層(保護層)
150．．．區域
152．．．保護圖案
152a、152b．．．保護圖案
154．．．絕緣層(保護層)
156．．．區域
160．．．絕緣層(保護層)
162．．．絕緣層(保護層)
164．．．導電層(RDL)
166．．．保護圖案
168．．．絕緣層(保護層)
170．．．凸塊
172．．．封裝材料
174．．．絕緣層(保護層)
176．．．絕緣層(保護層)
178．．．導電層(RDL)
180．．．保護圖案
182．．．絕緣層(保護層)
184．．．凸塊
圖1係描繪一習知的半導體晶圓，其具有一形成在該半導體晶粒之上的保護層；
圖2係描繪該習知的半導體晶圓的一帶有該保護層的侵蝕的邊緣；
圖3係描繪一具有不同類型的封裝安裝到其表面的PCB；
圖4a-4c係描繪安裝到該PCB之代表性的半導體封裝的進一步細節；
圖5a-5d係描繪一種在一半導體晶粒附近為了一絕緣層的局部平坦化而形成一保護圖案的製程；
圖6係描繪在一WLCSP中具有安裝到一基板的保護圖案之半導體晶粒；
圖7a-7b係描繪為了一絕緣層的局部平坦化，一依循該接觸墊的一輪廓的保護圖案；
圖8a-8b係描繪為了一絕緣層的局部平坦化，一具有平行的區段的保護圖案；
圖9係描繪在一具有RDL的WLCSP中形成在一重新繞線的保護層之上的保護圖案；以及
圖10係描繪在一具有RDL的Fo-WLCSP中形成在一重新繞線的保護層之上的保護圖案。
124．．．半導體晶粒(構件)
126．．．切割道
132．．．導電層
134．．．接觸墊
136．．．信號線路
148．．．絕緣層(保護層)
150．．．區域

Claims (25)

  1. 一種製造一半導體元件之方法，其係包括：提供一具有複數個藉由一切割道分開的半導體晶粒的半導體晶圓；在該半導體晶粒的一作用表面之上形成一接觸墊；在該半導體晶粒的該作用表面之上且在該半導體晶粒的接觸墊及切割道之間形成一保護圖案；在該作用表面、接觸墊以及保護圖案之上形成一第一絕緣層；以及移除該第一絕緣層的一部分以露出該接觸墊，其中該保護圖案係減低在該半導體晶粒的接觸墊及切割道之間的第一絕緣層的侵蝕。
  2. 如申請專利範圍第1項之方法，其中該保護圖案係包含一金屬層。
  3. 如申請專利範圍第1項之方法，其中該保護圖案係分段的。
  4. 如申請專利範圍第1項之方法，其進一步包含在該半導體晶粒的作用表面之上形成一具有一至該接觸墊的開口的第二絕緣層。
  5. 如申請專利範圍第1項之方法，其中該保護圖案係依循該接觸墊的一輪廓。
  6. 如申請專利範圍第1項之方法，其中該保護圖案係包含複數個平行的區段。
  7. 如申請專利範圍第1項之方法，其進一步包含在該半導體晶粒的角落處形成該保護圖案。
  8. 一種製造一半導體元件之方法，其係包括：提供一半導體晶圓；在該半導體晶圓的一表面之上形成一導電層；在該半導體晶圓的表面之上且在該導電層及該半導體晶圓的一邊緣之間形成一保護圖案；在該半導體晶圓的表面、導電層及保護圖案之上形成一絕緣層；以及移除該絕緣層的一部分以露出該導電層的一部分，其中該保護圖案係維持在該導電層及該半導體晶圓的邊緣之間的絕緣層。
  9. 如申請專利範圍第8項之方法，其中該保護圖案係包含一金屬層。
  10. 如申請專利範圍第8項之方法，其中該保護圖案係分段的。
  11. 如申請專利範圍第8項之方法，其中該保護圖案係依循該導電層的該露出的部分的一輪廓。
  12. 如申請專利範圍第8項之方法，其中該保護圖案係包含複數個平行的區段。
  13. 如申請專利範圍第8項之方法，其進一步包含在該半導體晶粒的角落處形成該保護圖案。
  14. 一種製造一半導體元件之方法，其係包括：提供一半導體晶粒；在該半導體晶粒的一表面之上形成一導電層；在該半導體晶粒的表面之上相鄰該導電層形成一保護圖案；以及在該半導體晶粒的表面、導電層及保護圖案之上形成一第一絕緣層，其中該保護圖案係維持相鄰該導電層的第一絕緣層。
  15. 如申請專利範圍第14項之方法，其進一步包含移除該絕緣層的一部分以露出該導電層的一部分，其中該保護圖案係減低相鄰該導電層的第一絕緣層的侵蝕。
  16. 如申請專利範圍第14項之方法，其中該保護圖案係包含一金屬層。
  17. 如申請專利範圍第14項之方法，其中該保護圖案係分段的。
  18. 如申請專利範圍第14項之方法，其進一步包含在該半導體晶粒之上形成一封裝材料。
  19. 如申請專利範圍第14項之方法，其進一步包含在該半導體晶粒的表面之上形成一具有一至該導電層的開口的第二絕緣層。
  20. 如申請專利範圍第14項之方法，其進一步包含在該半導體晶粒的角落處形成該保護圖案。
  21. 一種半導體元件，其係包括：一半導體晶粒；一形成在該半導體晶粒的一表面之上的導電層；一形成在該半導體晶圓的表面之上相鄰該導電層的保護圖案；以及一形成在該半導體晶粒的表面、導電層及保護圖案之上的絕緣層，其中該保護圖案係維持相鄰該導電層的該絕緣層。
  22. 如申請專利範圍第21項之半導體元件，其中該保護圖案係包含一金屬層。
  23. 如申請專利範圍第21項之半導體元件，其中該保護圖案係分段的。
  24. 如申請專利範圍第21項之半導體元件，其中該保護圖案係依循該導電層的露出部分的一輪廓。
  25. 如申請專利範圍第21項之半導體元件，其中該保護圖案係包含複數個平行的區段。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI708286B (zh) * 2018-10-02 2020-10-21 南亞科技股份有限公司 半導體裝置及其製作方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8659123B2 (en) * 2011-09-28 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Metal pad structures in dies
US8685761B2 (en) * 2012-02-02 2014-04-01 Harris Corporation Method for making a redistributed electronic device using a transferrable redistribution layer
US9257412B2 (en) * 2012-09-12 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Stress reduction apparatus
US9224688B2 (en) * 2013-01-04 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Metal routing architecture for integrated circuits
TWI515903B (zh) 2013-09-30 2016-01-01 台達電子工業股份有限公司 半導體裝置
US9502270B2 (en) * 2014-07-08 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
JP2016111285A (ja) * 2014-12-10 2016-06-20 株式会社東芝 半導体装置
KR20160083408A (ko) 2014-12-31 2016-07-12 삼성전자주식회사 퓨즈 패키지 및 이를 이용한 발광소자 모듈
JPWO2017056297A1 (ja) * 2015-10-01 2018-06-07 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR20220090664A (ko) * 2020-12-22 2022-06-30 삼성전자주식회사 스트립 기판 및 반도체 패키지

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3421204A (en) 1967-05-03 1969-01-14 Sylvania Electric Prod Method of producing semiconductor devices
US4651409A (en) * 1984-02-09 1987-03-24 Ncr Corporation Method of fabricating a high density, low power, merged vertical fuse/bipolar transistor
KR100190927B1 (ko) * 1996-07-18 1999-06-01 윤종용 슬릿이 형성된 금속막을 구비한 반도체 칩 장치
JPH10154670A (ja) * 1996-11-26 1998-06-09 Toshiba Corp 半導体装置の製造方法
US6235551B1 (en) * 1997-12-31 2001-05-22 Micron Technology, Inc. Semiconductor device including edge bond pads and methods
US6008070A (en) * 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
US6432752B1 (en) * 2000-08-17 2002-08-13 Micron Technology, Inc. Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages
US6762502B1 (en) * 2000-08-31 2004-07-13 Micron Technology, Inc. Semiconductor device packages including a plurality of layers substantially encapsulating leads thereof
US7340181B1 (en) 2002-05-13 2008-03-04 National Semiconductor Corporation Electrical die contact structure and fabrication method
TWI241702B (en) 2003-07-28 2005-10-11 Siliconware Precision Industries Co Ltd Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure
US8026128B2 (en) * 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
TWI534915B (zh) * 2003-11-10 2016-05-21 恰巴克有限公司 引線上凸塊之倒裝晶片互連
US7235867B1 (en) * 2004-11-01 2007-06-26 Advanced Micro Devices, Inc. Semiconductor device with electrically biased die edge seal
JP5427337B2 (ja) 2005-12-21 2014-02-26 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置及びその製造方法、カメラモジュール
US8193639B2 (en) * 2010-03-30 2012-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy metal design for packaging structures
US9202713B2 (en) * 2010-07-26 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI708286B (zh) * 2018-10-02 2020-10-21 南亞科技股份有限公司 半導體裝置及其製作方法
US11063003B2 (en) 2018-10-02 2021-07-13 Nanya Technology Corporation Semiconductor device with diced semiconductor chips and method for manufacturing the same

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