CN114999947A - 形成小z半导体封装的方法和半导体器件 - Google Patents

形成小z半导体封装的方法和半导体器件 Download PDF

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Publication number
CN114999947A
CN114999947A CN202210680608.8A CN202210680608A CN114999947A CN 114999947 A CN114999947 A CN 114999947A CN 202210680608 A CN202210680608 A CN 202210680608A CN 114999947 A CN114999947 A CN 114999947A
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semiconductor die
semiconductor
encapsulant
bumps
semiconductor device
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K.K.侯
S.金努萨米
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Semtech Corp
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Semtech Corp
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Abstract

本发明涉及形成小z半导体封装的方法和半导体器件，涉及一种制造半导体器件的方法，包括：提供半导体管芯；在半导体管芯上形成背侧保护层；在载体上布置半导体管芯，其中背侧保护层位于半导体管芯和载体之间；在将所述半导体管芯布置所述载体上之后，在所述半导体管芯上沉积密封剂，其中所述密封剂基本上覆盖所述半导体管芯的有源表面和侧表面；在半导体管芯的有源表面上平坦化密封剂；和在所述密封剂上形成导电层并使导电层电连接到所述半导体管芯。

Description

形成小z半导体封装的方法和半导体器件
本申请是分案申请，其母案申请的发明名称是“形成小z半导体封装的方法和半导体器件”，其母案申请的申请日是2015年11月6日，其母案申请的申请号是：201510750963.8。
技术领域
本发明一般地涉及半导体器件，并且更具体地涉及形成具有减少的z维度的半导体封装的方法和半导体器件。
背景技术
半导体器件通常在现代电子产品中被发现。半导体器件在电气组件的数目和密度方面变化。分立半导体器件通常包含一种类型的电气组件，例如，发光二极管（LED）、小信号晶体管、电阻器、电容器、电感器和功率金属氧化物半导体场效应晶体管（MOSFET）。集成半导体器件通常包含数百到数百万的电气组件。集成半导体器件的示例包括微控制器、微处理器和各种信号处理电路。
半导体器件执行范围广泛的功能，诸如信号处理、高速计算、传送和接收电磁信号、控制电子设备、将太阳光变换为电力以及创建用于电视显示的视觉图像。在娱乐、通信、功率转换、网络、计算机和消费产品的领域发现半导体器件。在军事应用、航空、汽车、工业控制器和办公设备中也发现半导体器件。
半导体器件利用半导体材料的电气性质。半导体材料的结构允许通过电场或基极电流的施加或者通过掺杂工艺来操纵材料的导电率。掺杂将杂质引入半导体材料以操纵和控制半导体器件的导电率。
半导体器件包含有源和无源电气结构。包括双极和场效应晶体管的有源结构控制电流的流动。通过改变电场或基极电流的施加以及掺杂的水平，晶体管促进或限制电流的流动。包括电阻器、电容器和电感器的无源结构创建执行各种电气功能所需要的电压和电流之间的关系。无源和有源结构被电气连接以形成电路，该电路使得半导体器件能够执行高速操作和其他有用功能。
半导体器件通常使用两个复杂制造工艺（即，前端制造和后端制造，每一个可能涉及数百个步骤）来制造。前端制造涉及在半导体晶片的表面上形成多个管芯。每个半导体管芯通常是相同的，并且包含通过电气连接有源和无源组件形成的电路。后端制造涉及从完成的晶片单体化个别的半导体管芯并且封装该管芯以提供结构支撑、电气互连和环境隔离。如本文中使用的术语“半导体管芯”指代词语的单数和复数形式二者，并且相应地，可以指代单个半导体器件和多个半导体器件二者。
半导体制造的一个目标是生产较小的半导体器件。较小的器件通常消耗较少的功率，具有较高的性能，并且被更有效地生产。此外，较小的半导体器件具有较小的覆盖区域，这对于较小的最终产品是所期望的。较小的半导体管芯大小通过前端工艺的改进来实现，从而导致具有较小、较高密度的有源和无源组件的半导体管芯。后端工艺的提高也导致具有较小覆盖区域的半导体器件，并且通过改进电气互连和封装材料来实现。减小的封装轮廓对蜂窝或智能电话行业中的封装来说特别重要。
封装大小的减小通过减少封装覆盖区域，即，通过减小封装的x和y维度来实现。封装大小的减小还通过减少封装高度或厚度，即，通过减少封装的z维度来实现。z维度的减少通过减小封装内的半导体管芯的厚度来完成。然而，减小半导体管芯厚度增加了半导体管芯的易碎性，从而使得半导体管芯和整体封装更容易受到损害。此外，形成具有减小的厚度的封装通常涉及增加总成本并且减小生产量的耗时的制造工艺。
发明内容
存在形成具有减小的厚度同时减少制造时间和成本的鲁棒半导体器件的需要。因此，在一个实施例中，本发明是一种制作半导体器件的方法，该方法包括下述步骤：提供多个第一半导体管芯，该第一半导体管芯包括在第一半导体管芯上形成的多个凸块；在与凸块相对的第一半导体管芯之上形成保护层；在第一半导体管芯之上沉积密封剂；从凸块之上去除密封剂的一部分；以及在凸块和密封剂之上形成导电层。
在另一实施例中，本发明是一种制作半导体器件的方法，该方法包括下述步骤：提供第一半导体管芯；在第一半导体管芯之上形成第一保护层；在第一半导体管芯之上沉积密封剂；从第一半导体管芯之上去除密封剂的一部分；以及在密封剂的第一表面之上形成第一导电层。
在另一实施例中，本发明是一种制作半导体器件的方法，该方法包括下述步骤：提供第一半导体管芯；在第一半导体管芯之上沉积密封剂；从在第一半导体管芯之上去除密封剂的一部分；以及在密封剂之上形成导电层。
在另一实施例中，本发明是一种半导体器件，该半导体器件包括第一半导体管芯和在第一半导体管芯之上形成的保护层。密封剂被沉积在第一半导体管芯周围。在相对于保护层的第一半导体管芯之上形成导电层。
附图说明
图1a-1h图示了在半导体管芯之上形成保护层的方法；
图2a-2c图示了形成具有暴露的后表面的半导体管芯的方法；
图3a-3g图示了形成具有在半导体管芯之上形成的背侧保护层的半导体器件的方法；
图4图示了具有在半导体管芯之上形成的背侧保护层的半导体器件；
图5图示了具有带有暴露的后表面的半导体管芯的半导体器件；
图6图示了具有在半导体管芯之上布置的散热器的半导体器件；
图7图示了具有堆叠的半导体管芯的半导体器件；
图8a-8h图示了制作具有跨半导体器件的表面布置的保护层的半导体器件的方法；
图9图示了具有跨半导体器件的表面布置的保护层的半导体器件；
图10图示了具有跨半导体器件的表面形成的保护层的堆叠的半导体管芯的半导体器件；
图11a-11c图示了形成具有用于电气连接堆叠的器件的导电通孔的半导体器件的方法；
图12图示了在开放半导体器件堆叠中具有多个半导体器件的半导体封装；以及
图13图示了在封闭半导体器件堆叠中具有多个半导体器件的半导体封装。
具体实施方式
在以下参考附图的描述中，在一个或多个实施例中描述本发明，在附图中，相同的数字表示相同或相似的元件。尽管在用于实现本发明的目的的最佳模式方面描述了本发明，但是本领域技术人员将理解，本公开意在涵盖如由所附权利要求以及如由以下公开和附图支持的权利要求等价物限定的本发明的精神的范围内的替代、修改和等价物。
半导体器件通常使用两个复杂的制造工艺：前端制造和后端制造来制造。前端制造涉及在半导体晶片的表面上形成多个管芯。晶片上的每个管芯包含电气连接以形成功能电气电路的有源和无源电气组件。诸如晶体管和二极管的有源电气组件具有用于控制电流的流动的能力。诸如电容器、电感器和电阻器的无源电气组件创建执行电气电路功能所需要的电压和电流之间的关系。
通过一系列工艺步骤在半导体晶片的表面之上形成无源和有源组件，一系列工艺步骤包括掺杂、沉积、光刻、蚀刻和平坦化。掺杂通过诸如离子注入或热扩散的技术将杂质引入半导体材料。掺杂工艺通过响应于电场或基极电流动态地改变半导体材料导电率来修改有源器件中的半导体材料的导电率。晶体管包含不同类型和程度的掺杂的区域，该不同类型和程度的掺杂的区域按照使得晶体管能够促进或限制在施加电场或基极电流时的电流的流动所需要的那样来布置。
有源和无源组件由具有不同电气性质的材料层形成。这些层可以通过部分地按被沉积的材料的类型确定的各种沉积技术来形成。例如，薄膜沉积能够涉及化学气相沉积（CVD）、物理气相沉积（PVD）、电解电镀和非电解镀工艺。每个层通常被图案化以形成有源组件、无源组件或组件之间的电气连接的一部分。
后端制造指代将完成的晶片切割或单体化成个别的半导体管芯并且封装该半导体管芯以用于结构支撑、电气互连和环境隔离。为了单体化半导体管芯，沿着晶片的称为锯切道或划线的非功能区来刻划并且划破晶片。使用激光切割工具或锯片来单体化晶片。在单体化之后，个别的半导体管芯被安装到包括用于与其他系统组件互连的管脚或接触焊盘的封装衬底。然后，在半导体管芯之上形成的接触焊盘被连接到封装内的接触焊盘。电气连接用导电层、凸块、柱状凸块、导电胶或焊线制作。密封剂或其他成型材料被沉积在封装之上以提供物理支撑和电气隔离。然后，完成的封装被插入电气系统，并且使得半导体器件的功能可用于其他系统组件。
图1a示出了具有诸如硅、锗、磷化铝、砷化铝、砷化镓、氮化镓、磷化铟、碳化硅的基底衬底材料102或用于结构支撑的其他块体半导体材料的半导体晶片100。由非有源的、管芯间的晶片区域或如以上描述的锯切道106分离的多个半导体管芯或组件104形成在晶片100上。锯切道106提供用于将半导体晶片100单体化成个别的半导体管芯104的切割区域。
图1b示出了半导体晶片100的一部分的横截面视图。每个半导体管芯104具有后表面或非有源表面108以及包含模拟或数字电路的有源表面110，模拟或数字电路被实现为根据管芯的电气设计和功能在管芯内形成并且电气互连的有源器件、无源器件、导电层和电介质层。例如，该电路包括一个或多个晶体管、二极管以及在有源表面110内形成的其他电路元件，用于实施模拟电路或数字电路，诸如数字信号处理器（DSP）、ASIC、MEMS、存储器或其他信号处理电路。半导体管芯104还包含集成无源器件（IPD），诸如电感器、电容器和电阻器，以用于RF信号处理。
使用PCD、CVD、电解电镀、非电解镀工艺或其他适当的金属沉积工艺在有源表面110之上形成导电层112。导电层112包括铝（Al）、铜（Cu）、锡（Sn）、镍（Ni）、金（Au）、银（Ag）、钯（Pd）、SnAg、SnAgCu、CuNi、CuNiAu、CuNiPdAu或其他适当的导电材料或其组合的一个或多个层。导电层112作为电气连接到有源表面110上的电路的接触焊盘进行操作。接触焊盘112促进在半导体管芯104内的有源电路和外部器件之间的后续电气互连，例如印刷电路板（PCB）。
使用蒸发、电解电镀、非电解镀、落球或丝网印刷工艺在接触焊盘112之上沉积导电凸块材料。凸块材料是具有可选焊剂溶体的Al、Sn、Ni、Au、Ag、铅（Pb）、铋（Bi）、Cu、焊料及其组合。例如，凸块材料是共晶Sn/Pb、高铅焊料或无铅焊料。凸块材料使用适当的粘附或接合工艺被接合到接触焊盘112。凸块材料通过对该材料加热到材料的熔点以上而被回流以形成球或凸块114。在一些应用中，凸块114被二次回流以改善与接触焊盘112的电气连接。凸块114还可以被压焊或热压焊到接触焊盘112。凸块114表示在接触焊盘112之上形成的一种类型的互连结构。互连结构还可以使用柱状凸块、微型凸块或其他电气互连。
在图1c中，使用层压、丝网印刷、旋转涂布、喷涂或其他适当的方法来在凸块114和晶片100之上形成临时保护层116。临时保护层116包含光致抗蚀剂、液体涂布材料、干膜、聚合物膜、聚合物复合材料或具有柔度、结构支撑、热稳定性和易剥离的性质的其他材料的一个或多个层。保护层116覆盖凸块114和有源表面110。在一个实施例中，保护层116是背面研磨带。保护层116是牺牲层，该牺牲层用于在后续制造工艺期间，例如在晶片100的背面研磨期间，提供结构支撑并且保护有源表面110。在沉积保护层116之后，诸如UV曝光和加热工艺的额外处理被应用，以提供必要的粘附性和机械性质。
在图1d中，晶片100的背侧表面108经受用研磨机118的背面研磨操作，以减小半导体管芯104的厚度。背面研磨操作从表面108去除基底衬底材料102的一部分，并且留下具有新的背侧表面120的半导体管芯104。化学蚀刻、等离子体蚀刻、化学机械研磨（CMP）或激光直接消融（LDA）工艺用于去除基体衬底材料102的一部分。在一个实施例中，背面研磨操作将半导体管芯104的厚度减小到25-300微米（μm），即半导体管芯104在背面研磨之后具有在25-300μm之间的z维度。保护层116在背面研磨操作期间保护有源表面110，并且防止研磨碎屑污染接触焊盘112和有源表面110内的器件。保护层116还在背面研磨期间和之后在结构上支撑半导体管芯104。由保护层116提供的结构支撑允许从表面108去除基底衬底材料102的较大部分。
在图1e中，在半导体管芯104的表面120上形成背侧保护层122。通过层压、丝网印刷、旋转涂布、喷涂或其他适当的方法来形成背侧保护层122。背侧保护层122是下述材料中的一个或多个层：具有或没有填料的光敏聚合物电介质膜、非光敏聚合物电介质膜、环氧材料、环氧树脂、聚合物材料、聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯、或具有适当填料的聚合物、热固性塑料层压板、或具有类似绝缘和结构性质的其他材料。背侧保护层122是不导电的，并且在环境上保护半导体管芯104的背侧表面120。背侧保护层还提供用于增加刚性并且减少半导体管芯104的易碎性的结构支撑。背侧保护层122还可以提供散热，以改善半导体器件的热性能。背侧保护层122还可以提供用于控制总体封装翘曲的翘曲调谐能力。
在图1f中，在界面层或双侧带126之上布置半导体晶片100。界面层126通过膜框架或临时载体124被适当保持。界面层126在膜框架124之上被形成为临时粘附接合膜、蚀刻停止层或分离层。晶片100被安装到界面层126，其中背侧保护层122朝着界面层126定向并且接触界面层126。
膜框架124、界面层126和晶片100在炉中或者利用加热板在一定温度下被加热并且在足以释放保护层116并且暴露凸块114和有源表面110的持续时间内被加热。如果在保护层116释放时背侧保护层122没有被充分固化，则允许晶片100、膜框架124和界面层126继续在一定温度下并且在足以允许背侧保护层122完全固化的持续时间内进行烘烤。
图1g示出了在去除保护层116之后的半导体晶片100。半导体晶片100使用锯片或激光切割工具128贯穿锯切道106被单体化成个别的半导体管芯104。替代地，使用化学或等离子体蚀刻工艺来单体化半导体管芯104。
图1h示出了单体化之后的半导体管芯104。在半导体管芯104的后表面120上形成背侧保护层122。背侧保护层120保护后表面120免受污染并且在物理上加强半导体管芯104。然后，半导体管芯104被清洗、干燥和照射。清洗工艺包括旋转冲洗干燥（SRD）工艺、等离子体清洗工艺、干洗工艺、湿法清洗工艺或其组合。半导体管芯104被检查并且电气测试，以用于在单体化之前或之后识别已知的良好管芯（KGD）。然后，将被清洗和检查的半导体管芯104装载到拾放设备以用于进一步处理。
图2a-2c示出了形成具有暴露的背侧表面120的半导体管芯104的方法。从图1d继续，半导体晶片100被布置在界面层126和膜框架124之上。图2a示出了具有朝着界面层126定向并且与界面层126接触的后表面120的、在膜框架124之上安装的半导体晶片100。
膜框架124、界面层126和晶片100在炉中或者利用加热板在一定温度下被加热并且在足以释放保护层116并且暴露凸块114和有源表面110的持续时间内被加热。图2b示出了在去除保护层116之后的半导体晶片100。使用锯片或激光切割工具128贯穿锯切道106将半导体晶片100单体化成个别的半导体管芯104。替代地，使用等离子体或化学蚀刻工艺来单体化半导体管芯104。
图2c示出了单体化之后的半导体管芯104。半导体管芯104具有暴露的背侧表面120。然后，个别的半导体管芯104被清洗、干燥和照射。清洗工艺包括SRD工艺、等离子体清洗工艺、干法清洗工艺、湿法清洗工艺或其组合。半导体管芯104被检查并且电气测试，以用于在单体化之后识别KGD。然后，将被清洗和检查的半导体管芯104装载到拾放设备以用于进一步处理。
图3a-3g示出了形成具有在半导体管芯之上形成的背侧保护层的半导体器件的方法。图3a示出了包含诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其他适当的低成本刚性材料的牺牲基底材料的载体或临时衬底130的一部分的横截面视图。界面层或双面带132在载体130之上被形成为临时粘附接合膜、蚀刻停止层或热释放层。例如使用拾放操作来在载体130和界面层132之上布置图1h的半导体管芯104，其中背侧保护层122朝着载体定向。
图3b示出了作为重构或重新配置的晶片134被安装到界面层132和载体130的半导体管芯104。凸块114远离载体130被定向。通过界面层132来在载体130之上适当地保持半导体管芯104。在半导体管芯104周围布置可重新使用的保护环136。
在图3c中，使用丝网印刷、喷涂、锡膏印刷、压缩成型、传递成型、液体密封剂成型、真空层压、旋转涂布或其他适当的涂覆方法来在半导体管芯104和载体130之上沉积密封剂或成型化合物138。密封剂138被沉积在半导体管芯104周围，并且覆盖凸块114、有源表面110和半导体管芯104的四个侧表面104。密封剂138包括聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有适当填料的聚合物。密封剂138是不导电的并且在环境上保护半导体管芯104免受外部元件和污染物的影响。
在图3d中，保护环136被去除，并且密封剂138的表面140经受研磨操作以平面化密封剂138并且暴露凸块114。研磨机142从表面140去除密封剂138的一部分。研磨操作显露出凸块114的一部分并且留下具有平面化表面144的密封剂。在研磨之后，表面144与凸块114共面。
在图3e中，使用诸如印刷、PVD、CVD、溅射、电解电镀和非电解镀的图案化和金属沉积工艺来在凸块114和密封剂138的表面144之上形成导电层146。导电层146是Al、Cu、Sn、Ni、Au、Ag或其他适当导电材料的一个或多个层。导电层146操作为在半导体管芯104之上形成的再分布层（RDL）。导电层146提供从凸块114延伸到在半导体管芯104和密封剂138之上的其他区域的导电路径。导电层146的一部分电气连接到凸块114。导电层146的其他部分根据半导体管芯104的设计和功能电气共用或电气隔离。
在一个实施例中，在暴露凸块114之后，通过将重构的晶片134放入高速纳米颗粒喷射或激光印刷机来形成导电层146。然后，以期望的图案在凸块114和密封剂138之上直接印刷导电层146的迹线。纳米Cu或Ag迹线用于形成导电层146。在印刷完成之后，将迹线固化或烧结。替代地，迹线与印刷实时被同时地烧结。
在另一实施例中，在暴露凸块114之后，在密封剂138的表面144和凸块114上执行去污操作。在去污之后，在炉中干燥密封的半导体管芯104。在干燥之后，执行非电解镀操作。接下来，执行干膜层压工艺，之后是干膜图案化和铜电解电镀。然后，去除干膜，并且执行闪刻（flash etching）和退火工艺，以完成在凸块114和密封剂138之上的导电层146的形成。
在另一实施例中，通过使用喷涂、旋转涂布或其他适当的涂覆工艺跨暴露的凸块114和密封剂138的表面144沉积丝网涂布或光致抗蚀剂层来形成导电层146。然后，将重构的晶片放置在炉中以干燥光致抗蚀剂层中。在干燥工艺之后，UV曝光用于图案化光致抗蚀剂层。执行去离子（DI）冲洗以留下在光致抗蚀剂层中形成的期望迹线图案。然后，执行非电解镀以在图案化的光致抗蚀层中沉积导电层146。非电解镀之后是冲洗和干燥工艺以去除光致抗蚀剂层，并且留下在密封剂138的表面144和凸块114之上形成的图案化导电层146。
转到图3f，使用PVD、CVD、印刷、层压、旋转涂布、喷涂或其他适当的涂覆工艺在密封剂138和导电层146之上形成绝缘或钝化层148。绝缘层148包含下述的一个或多个层：阻焊、二氧化硅（SiO2）、氮化硅（Si3N4）、氮氧化硅（SiON）、五氧化二钽（Ta2O5）、氧化铝（Al2O3）、氧化铪（HfO2）、苯并环丁烯（BCB）、聚酰亚胺（PI）、聚苯并恶唑（PBO）、聚合物或具有类似结构和绝缘性质的其他材料。通过LDA、蚀刻或其他适当工艺来去除绝缘层148的一部分，以在导电层146之上形成多个开口150。开口150暴露导电层146以用于后续的电气互连。
在图3g中，使用蒸发、电解电镀、非电解镀、落球或丝网印刷工艺在开口150中在导电层146之上沉积导电凸块材料。在一个实施例中，用落球模板（即不需要掩模）来沉积凸块材料。凸块材料是具有可选焊剂溶体的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料是共晶Sn/Pb、高铅焊料或无铅焊料。凸块材料使用适当的粘附或接合工艺被接合到导电层146。凸块材料通过对该材料加热到材料的熔点以上而被回流以形成球或凸块152。在一些应用中，凸块152被二次回流以改善与导电层146的电气接触。凸块152还可以被压焊或热压焊到导电层146。凸块152表示在导电层146之上形成的一种类型的互连结构。互连结构还可以使用导电胶、柱状凸块、微型凸块或其他电气互连。
然后，使用锯片或激光切割工具154来将重构的晶片134单体化成个别的半导体器件或封装160。在单体化之后，使用热烘烤、UV光或机械剥离从界面层132释放半导体器件160。
图4示出了单体化之后的半导体器件160。半导体管芯104通过凸块114和导电层146被电气连接到凸块152以用于外部互连。密封剂138被沉积在半导体管芯104和背侧保护层122周围。从界面层132释放半导体管芯104暴露背侧保护层122和密封剂138的表面156。密封剂138的表面156与背侧保护层122的表面共面。
在半导体管芯104和密封剂138的表面144之上形成导电层146。导电层146允许来自半导体管芯104的信号跨半导体器件160被重新路由。导电层146的一部分沿着密封剂138的表面144、平行于半导体管芯104的有源表面110水平延伸，以横向重新分配来自凸块114的电信号。形成在密封剂138之上延伸即延伸到半导体管芯104的覆盖区域外的导电层146提供了在凸块152的位置和设计布局中的较大灵活性。例如，凸块152的间距被选择为反映具有行业标准输入/输出（I/O）密度的衬底，或者凸块152的间距和布局被选择为匹配具有独特I/O密度和图案的衬底。互连布局中的较大灵活性使得半导体器件160与较大数目的其他器件兼容。此外，与将半导体管芯104安装到预成型的中介层衬底相反，在密封剂138和半导体管芯104上形成导电层146减小了半导体器件160的总厚度或z维度。
在半导体管芯104的表面120上形成背侧保护层122。背侧保护层122加强并且保护半导体器件160内的半导体管芯104。背侧保护层122在环境上保护半导体管芯104免受外部元件的影响，并且提供刚性和物理支撑以加强半导体管芯104。背侧保护层122减少在处理或其他制造工艺期间（例如在密封剂138的沉积期间或在导电层146的形成期间）半导体管芯104将被损坏的可能性。良好半导体器件160的生产量由于背侧保护层122使得半导体管芯104在制造期间和制造之后二者不太容易受到损坏而增加。
因为半导体管芯104的厚度在图1d中所示的背面研磨操作中被减小，所以半导体器件160具有减小的z维度。因为保护层116在背面研磨期间支撑半导体管芯104，并且背侧保护层122在背面研磨之后支撑半导体管芯104，所以从半导体管芯104去除更大部分的基底衬底材料102。因此，半导体管芯104和半导体器件160的整体厚度被减小。具有背侧保护层122的密封的半导体管芯104使得鲁棒的半导体器件160具有减小的z维度。
图5示出了半导体器件170。半导体器件170包括具有暴露的后表面120的半导体管芯104。半导体管芯104通过凸块114和导电层146电气连接到凸块152以用于外部互连。
在半导体管芯104和密封剂138的表面144之上形成导电层146。导电层146允许来自半导体管芯104的信号跨半导体器件160被重新路由。导电层146的一部分沿着密封剂138的表面144、平行于半导体管芯104的有源表面110水平延伸，以横向重新分配来自凸块114的电信号。形成在密封剂138之上延伸即在半导体管芯104的覆盖区域外延伸的导电层146提供了在凸块152的位置和设计布局中的较大灵活性。例如，凸块152的间距被选择为反映具有行业标准I/O密度的衬底，或者凸块152的间距和布局被选择为匹配具有独特I/O密度和图案的衬底。互连布局中的较大灵活性使得半导体器件170与较大数目的其他器件兼容。此外，与将半导体管芯104安装到预成型的中介层衬底相反，在密封剂138和半导体管芯104上形成导电层146减小了半导体器件170的总厚度或z维度。
通过在具有与界面层132接触的后表面120的载体130之上布置图2c的半导体管芯104来形成半导体器件170。然后，制造如图3b-3g所示继续。在从界面层132释放半导体管芯104之后，半导体管芯104的后表面120与密封剂138的表面156共面。
因为半导体管芯104的厚度在图1d中所示的背面研磨操作中被减小，所以半导体器件170具有减小的z维度。因为保护层116在背面研磨期间支撑半导体管芯104，所以从半导体管芯104去除更大部分的基底衬底材料102。因此，半导体管芯104和半导体器件170的总厚度被减小。暴露的后表面120允许从半导体管芯104的更大散热。采用具有暴露的后表面120的半导体管芯104还进一步减小半导体器件170的总厚度。
图6示出了类似于图4中的半导体器件160的，具有布置在背侧保护层122和密封剂138的表面156之上的散热器182的半导体器件180。替代地，散热器182被布置在具有暴露的后表面120的半导体管芯104之上，即在类似于图5的半导体器件170的器件之上。散热器182是Cu、Al或具有高导热率的其他材料。在一个实施例中，背侧保护层122是热界面层（TIM），其被布置在半导体管芯104的后表面120和散热器182之间，以促进从半导体管芯104到散热器182的热流动以及热连接。TIM是氧化铝、氧化锌、氮化硼或粉状的银。散热器182有助于由半导体管芯104生成的热的分布和耗散。
在载体之上布置半导体管芯104之前，通过在载体130和界面层132之上层压导电箔在半导体管芯104之上形成散热器182。然后，使用拾放操作将半导体管芯104安装到导电箔，其中凸块114远离导电箔被定向。背侧保护层或TIM 122包括用于在导电箔之上适当地保持半导体管芯104的粘合材料。然后，如图3b-3g所示，制造工艺继续用切割工具154切割贯穿密封剂138和导电箔，即散热器182，以将重构的晶片134单体化成个别的半导体器件180。
替代地，在从界面层132和载体130去除重构的晶片134之后，在半导体管芯104和密封剂138的表面156之上形成散热器182。在去除载体130和界面层132之后，使用层压、PVD、CVD、电解电镀、非电解镀工艺或者其他适当的金属沉积工艺来将散热器182的导电材料布置在半导体管芯104和密封剂138的表面156之上。然后，将具有在半导体管芯104和密封剂138之上形成的导电材料182的重构的晶片134单体化成半导体器件180。在一个实施例中，划切带或其他支撑载体被附着到重构的晶片134以在散热器182的形成期间和在单体化期间支撑重构的晶片134。散热器182耗散由半导体管芯104生成的热，并且提高半导体器件180的热性能和总体功能。
图7示出了具有在半导体管芯104之上布置的半导体管芯192的半导体器件190。半导体管芯104具有暴露的后表面120。替代地，在具有在后表面120之上形成的背侧保护层122的半导体管芯104之上布置半导体管芯192。
半导体管芯192具有后表面或非有源表面193和包含模拟或数字电路的有源表面194，该模拟或数字电路被实施为根据管芯的电气设计和功能在管芯内形成并且电气互连的有源器件、无源器件、导电层和电介质层。例如，该电路包括一个或多个晶体管、二极管和在有源表面194内形成的其他电路元件，用于实施模拟电路或数字电路，诸如DSP、ASIC、MEMS、存储器或其他信号处理电路。半导体管芯192还包含IPD，诸如电感器、电容器和电阻器，以用于RF信号处理。
使用PVD、CVD、电解电镀、非电解镀工艺或其他适当金属沉积工艺在有源表面194之上形成导电层196。导电层196包括Al、Cu、Sn、Ni、Au、Ag、Pd、SnAg、SnAgCu、CuNi、CuNiAu、CuNiPdAu或其他适当的导电材料或其组合中的一个或多个层。导电层196操作为电气连接到有源表面194上的电路的接触焊盘。接触焊盘196促进在半导体管芯192内的有源电路和外部器件之间的后续电气互连。
使用蒸发、电解电镀、非电解镀、落球或丝网印刷工艺在接触焊盘196之上沉积导电凸块材料。凸块材料是具有可选焊剂溶体的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料是共晶Sn/Pb、高铅焊料或无铅焊料。凸块材料使用适当的粘附或接合工艺被接合到接触焊盘196。凸块材料通过对该材料加热到材料的熔点以上而被回流以形成球或凸块199。在一些应用中，凸块199被二次回流以改善与接触焊盘196的电气连接。凸块199还可以被压焊或热压焊到接触焊盘196。凸块199表示在接触焊盘196之上形成的一种类型的互连结构。互连结构还可以使用柱状凸块、微型凸块或其他电气互连。
贯穿半导体管芯192形成多个硅通孔（TSV）198。TSV 198从后表面193延伸到半导体管芯192的有源表面194。TSV 198是垂直互连结构，该结构提供在后表面193之上布置的器件或组件（例如，半导体管芯104）和在有源表面194之上布置的器件或组件（例如，导电层146）之间的电气互连。
半导体管芯192被安装到半导体管芯104。凸块114将半导体管芯104电气地并且冶金地连接到半导体管芯192的TSV 198。在半导体管芯104和半导体管芯192之上和周围沉积密封剂138。密封剂138在凸块114周围并且在半导体管芯104的有源表面110和半导体管芯192的后表面193之间流动。在一个实施例中，在沉积密封剂138之前，在半导体管芯104的有源表面110和半导体管芯192的后表面193之间沉积底层填料。
密封剂138经受研磨操作，以暴露凸块199并且平面化具有凸块199的密封剂138的表面144。在密封剂138的表面144和凸块199之上形成导电层146。导电层146的一部分电气连接到凸块199。导电层146的其他部分根据半导体管芯104和半导体管芯192的设计和功能而被电气共用或电气隔离。在导电层146之上形成绝缘层148和凸块152。
半导体管芯104通过凸块114、TSV 198、凸块199和导电层146电气连接到凸块152以用于外部互连。半导体管芯192通过凸块199和导电层146被电气连接到凸块152以用于外部互连。TSV 198将半导体管芯104电气连接到半导体管芯192。
在半导体管芯192和密封剂138的表面144之上形成导电层146。导电层146允许来自半导体管芯104和192的信号跨半导体器件190被重新路由。导电层146的一部分沿着密封剂138的表面144、平行于半导体管芯192的有源表面194水平延伸，以横向再分配来自凸块199的电信号。形成在密封剂138之上延伸（即，在半导体管芯192的覆盖区域外延伸）的导电层146提供了在凸块152的位置和设计布局中的较大灵活度。例如，凸块152的间距被选择为反映具有行业标准I/O密度的衬底，或者凸块152的间距和布局被选择为匹配具有独特I/O密度和图案的衬底。互连布局中的较大灵活度使得半导体器件190与较大数目的其他衬底和器件兼容。此外，与将半导体管芯104和192安装到预成型的中介层衬底相反，在密封剂138和半导体管芯192上形成导电层146，减小了半导体器件190的总厚度或z维度。
因为半导体管芯104的厚度在图1d中所示的背面研磨操作中被减小，所以半导体器件190具有减小的z维度。因为保护层116在背面研磨期间支撑半导体管芯104，所以从半导体管芯104去除更大部分的基底衬底材料102。因此，半导体管芯104和半导体器件190的总厚度被减小。在半导体管芯104之上布置具有TSV 198的半导体管芯192允许半导体器件190在单个封装内结合具有不同功能的多个半导体管芯。连接半导体器件190内的多个半导体管芯提高了半导体器件190的电气性能和总体功能。
图8a-8h图示了制作具有跨半导体器件的表面布置的保护层的半导体器件的方法。图8a示出了包含诸如硅、聚合物、氧化铍、玻璃或用于结构支撑的其他适当的低成本刚性材料的牺牲基底材料的载体或临时衬底200的一部分的横截面视图。在载体200之上形成界面层或双面胶带202作为临时粘附接合膜、蚀刻停止层或热释放层。例如使用拾放操作在载体200和界面层202之上布置图2c的半导体管芯104，其中背侧表面120朝着载体200的界面层202定向并且与载体200的界面层202接触。
图8b示出了安装到界面层202和载体200作为重构或重新配置的晶片204的半导体管芯104。凸块114远离载体200被定向。通过界面层202在载体200之上适当地保持半导体管芯104。在半导体管芯104周围布置可重新使用的保护环206。
在图8c中，使用丝网印刷、喷涂、锡膏印刷、压缩成型、传递成型、液体密封剂成型、真空层压、旋转涂布或其他适当的涂覆方法在半导体管芯104和载体200之上沉积密封剂或成型化合物208。在半导体管芯104之上和周围沉积密封剂208。密封剂208覆盖凸块114、有源表面110和半导体管芯104的四个侧表面。密封剂208包括聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯或具有适当填料的聚合物。密封剂208是不导电的，并且在环境上保护半导体管芯104免受外部元件和污染物的影响。
在图8d中，去除保护环206，并且密封剂208的表面210经受研磨操作以平面化密封剂208并且暴露凸块114。研磨机212从表面210去除密封剂208的一部分。研磨操作显露出凸块114的一部分，并且留下具有新的平面化表面214的密封剂208。在研磨之后，表面214与凸块114的暴露的表面共面。
在图8e中，使用诸如印刷、PVD、CVD、溅射、电解电镀和非电解镀的图案化和金属沉积工艺在凸块114和密封剂208的表面214之上形成导电层216。导电层216是Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层216的一部分电气连接到凸块114。导电层216的其他部分根据半导体管芯104的设计和功能被电气共用或电气隔离。导电层216操作为在半导体管芯104之上形成的RDL。导电层216提供从凸块114延伸到半导体管芯104和密封剂208之上的其他区域的导电路径。
在一个实施例中，在暴露凸块114之后，将重构的晶片204放置在高速纳米颗粒喷射或激光印刷机中。然后，以期望的图案在凸块114和表面214之上直接印刷导电层216的迹线。纳米Cu或Ag迹线用于形成导电层216。在印刷完成之后，将迹线固化或烧结，以完成导电层216的形成。替代地，迹线与印刷同时（即实时）地烧结。
在另一实施例中，在暴露凸块114之后，对密封剂208的表面214和凸块114执行去污操作。在去污之后，在炉中干燥密封的半导体管芯104。在干燥之后，执行非电解镀操作。接下来，执行干膜层压工艺，之后是干燥膜图案化和铜电解电镀。然后，去除干膜，并且执行闪速蚀刻和退火工艺，以完成导电层216的形成。
在另一实施例中，通过使用喷涂、旋转涂布或其他适当的涂覆工艺跨暴露的凸块114和密封剂208的表面214沉积丝网涂布或光致抗蚀剂层来形成导电层216。然后，将重构的晶片204放置在炉中以干燥光致抗蚀剂层中。在干燥工艺之后，UV曝光用于图案化光致抗蚀剂层。执行DI冲洗以留下在光致抗蚀剂层中形成的期望迹线图案。然后，执行非电解镀以在图案化的光致抗蚀层中沉积导电层146。非电解镀之后是冲洗和干燥工艺以去除光致抗蚀剂层，并且留下在密封剂208的表面214和凸块114之上形成的图案化导电层216。
转到图8f，使用PVD、CVD、印刷、层压、旋转涂布、喷涂或其他适当的涂覆工艺在密封剂208和导电层216之上形成绝缘或钝化层218。绝缘层218包含下述的一个或多个层：阻焊、SiO2、Si3N4、SiON、Ta2O5、Al2O3、HfO2、BCB、PI、PBO、聚合物或具有类似结构和绝缘性质的其他材料。通过LDA、蚀刻或其他适当工艺来去除绝缘层218的一部分，以在导电层216之上形成多个开口。绝缘层218中的开口暴露导电层216以用于后续的电气互连。
使用蒸发、电解电镀、非电解镀、落球或丝网印刷工艺在绝缘层218中的开口中在导电层216之上沉积导电凸块材料。在一个实施例中，用落球模板即不需要掩模来沉积凸块材料。凸块材料是具有可选焊剂溶体的Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料及其组合。例如，凸块材料是共晶Sn/Pb、高铅焊料或无铅焊料。凸块材料使用适当的粘附或接合工艺被接合到导电层216。凸块材料通过对该材料加热到材料的熔点以上而被回流以形成球或凸块220。在一些应用中，凸块220被二次回流以改善与导电层216的电气连接。凸块220还可以被压焊或热压焊到导电层216。凸块220表示在导电层216之上形成的一种类型的互连结构。互连结构还可以使用导电胶、柱状凸块、微型凸块或其他电气互连。
在图8g中，通过化学蚀刻、机械剥离、CMP、机械研磨、热烘、激光扫描、UV释放或湿法剥离来去除临时载体200和界面层202。在去除载体200和界面层202之后，暴露密封剂208的表面221和半导体管芯104的后表面120。
然后，在半导体管芯104的表面120和密封剂208的表面221之上形成背侧保护层222。背侧保护层222通过层压、丝网印刷、旋转涂布、喷涂或其他适当的涂覆方法来形成。背侧保护层222是下述中的一个或多个层：具有或不具有填料的光敏聚合物电介质膜、非光敏聚合物电介质膜、环氧材料、环氧树脂、聚合物材料、聚合物复合材料，诸如具有填料的环氧树脂、具有填料的环氧丙烯酸酯、或具有适当填料的聚合物、热固性塑料层压材料、或具有类似绝缘和结构性质的其他材料。背侧保护层222是不导电的，并且提供对半导体管芯104和重构的晶片204的环境保护和物理支撑。背侧保护层222还可以提供散热，以改善半导体器件的热性能。背侧保护层222还可以提供用于控制总体封装翘曲的翘曲调谐能力。
在图8h中，重构的晶片204被布置在具有朝着载体定向的背侧保护层222的临时载体224之上。类似于界面层202，可选界面层或双面胶带可以被布置在背侧保护层222和载体224的表面之间。在一个实施例中，背侧保护层222在载体224之上形成，并且然后重构的晶片204被安装在保护层222上，其中半导体管芯104的表面120被布置在保护层222上并且与保护层222接触。
重构的晶片204被加热以固化背侧保护层222。然后，使用锯片或激光切割工具228将重构的晶片204单体化成个别的半导体器件或封装230。在单体化之后，使用热烘烤、UV光或机械剥离来从载体224释放半导体器件230。
图9示出了单体化之后的半导体器件230。半导体管芯104通过凸块114和导电层216电气连接到凸块220以用于外部互连。在半导体管芯104和密封剂208的表面214之上形成导电层216。导电层216的一部分沿着密封剂208的表面214、平行于半导体管芯104的有源表面110水平延伸，以横向重新分配来自凸块114的电信号。形成在密封剂208之上延伸（即，在半导体管芯104的覆盖区域外延伸）的导电层216提供在凸块220的位置和设计布局中的较大灵活性。例如，凸块220的间距被选择为反映具有行业标准I/O密度的衬底，或者凸块152的间距和布局被选择为匹配具有独特I/O密度和图案的衬底。互连布局中的较大灵活性使得半导体器件230与较大数目的其他衬底和器件兼容。与将半导体管芯104安装到预成型的中介层衬底相反，在密封剂208和半导体管芯104上形成导电层216减小了半导体器件230的总厚度或z维度。
在半导体管芯104和密封剂208之上形成背侧保护层222。背侧保护层222覆盖半导体管芯104的后表面120以及密封剂208的表面221。背侧保护层222在环境上保护半导体管芯104免受外部元件的影响，并且提供刚性和物理支撑以加强半导体器件230。由于背侧保护层222的存在，半导体器件230在后续处理和加工期间不太容易受到损坏。良好半导体器件230的总体功能和生产量由于背侧保护层222使得半导体器件230不太容易受到损坏而增加。
因为半导体管芯104的厚度在图1d中所示的背面研磨操作中被减小，所以半导体器件230具有减小的z维度。因为保护层116在背面研磨期间支撑半导体管芯104，并且背侧保护层222提供刚性并且加强半导体管芯104和器件230，所以从半导体管芯104去除更大部分的基底衬底材料102。因此，半导体管芯104和半导体器件230的总厚度被减小。具有密封的半导体管芯104和背侧保护层222的半导体器件230提供具有减小的z维度的鲁棒的半导体器件，背侧保护层222覆盖半导体器件230的整个表面。
图10示出了类似于图7中的器件190的具有布置在半导体管芯104之上的半导体管芯192的半导体器件236。背侧保护层222覆盖密封剂208和半导体管芯104的后表面120。半导体管芯104的凸块114电气地并且冶金地连接到半导体管芯192的TSV 198。半导体管芯192的凸块199电气连接到导电层216。半导体管芯104通过凸块114、TSV 198、凸块199和导电层216电气连接到凸块220，以用于外部互连。半导体管芯192通过凸块199和导电层216电气连接到凸块220，以用于外部互连。TSV 198电气连接半导体管芯104和半导体管芯192。连接在半导体器件236内的多个半导体管芯增加了半导体器件236的总体功能。
使用锡膏印刷、喷射分配、压缩成型、传递成型、液体密封剂成型、真空层压、旋转涂布、成型底层填料或其他适当的涂覆工艺在半导体管芯104的有源表面110和半导体管芯192的后表面193之间沉积底层填料材料238。底层填料238是环氧材料、环氧树脂粘合材料、聚合物材料、膜或其他非导电材料。底层填料238被布置在凸块114周围。底层填料238是不导电的，并且在环境上保护半导体管芯免受外部元件和污染物的影响。底层填料238还增加在半导体管芯104和半导体管芯192之间的接合强度。
在底层填料材料238、半导体管芯104和半导体管芯192周围沉积密封剂208。执行研磨操作，以显露出凸块199并且平面化具有凸块199的密封剂208的表面214。在凸块199和密封剂208的表面214之上形成导电层216。导电层216的一部分电气连接到凸块199。导电层216的其他部分根据半导体管芯104和192的设计和功能被电气共用或电气隔离。
导电层216允许来自半导体管芯104和192的信号跨半导体器件236被重新路由。导电层216的一部分沿着密封剂208的表面214、平行于半导体管芯192的有源表面194水平延伸，以横向重新分配来自凸块199的电信号。形成在密封剂208之上延伸（即在半导体管芯192的覆盖区域外延伸）的导电层216提供了在凸块220的位置和设计布局中的较大灵活性。例如，凸块220的间距被选择为反映具有行业标准I/O密度的衬底，或者凸块220的间距和布局被选择为匹配具有独特I/O密度和图案的衬底。互连布局中的较大灵活性使得半导体器件236与较大数目的其他衬底和器件兼容。此外，与将半导体管芯104和192安装到预成型的中介层衬底相反，在密封剂208和半导体管芯192上形成导电层216减小了半导体器件236的总厚度或z维度。
背侧保护层222覆盖密封剂208的表面和半导体管芯104的后表面120。背侧保护层222加强半导体器件236，并且保护半导体管芯104在后续处理和加工期间免受损坏。由于背侧保护层222的存在，半导体器件236在后续处理和加工期间不太容易受到损坏。良好半导体器件236的总体功能和生产量由于背侧保护层222使得半导体器件236不太容易受到损坏而增加。
因为半导体管芯104的厚度在图1d中所示的背面研磨操作中被减小，所以半导体器件236具有减小的z维度。因为保护层116在背面研磨期间支撑半导体管芯104，并且背侧保护层222提供刚性并且支撑器件236内的半导体管芯104，所以从半导体管芯104去除更大部分的基底衬底材料102。因此，半导体管芯104和半导体器件236的总厚度被减小。具有密封的半导体管芯104和192以及背侧保护层222的半导体器件236提供具有减小的z维度的鲁棒的半导体器件，背侧保护层222覆盖半导体器件236的整个表面。在半导体管芯104之上布置具有TSV 198的半导体管芯192允许半导体器件236根据单个封装内的不同功能来结合多个半导体管芯。连接半导体器件236内的多个半导体管芯增加半导体器件236的电气性能和总体功能。
图11a-11c图示了制作具有用于电气连接堆叠的半导体器件的导电通孔的半导体器件的方法。从图3f继续，在导电层146之上形成凸块152之后，通过化学蚀刻、机械剥离、CMP、机械研磨、热烘、激光扫描、UV释放或湿法剥离来去除临时载体130和界面层132，并且在载体或临时衬底240和界面层242之上安装重构的晶片134。图11a示出了在载体240和具有凸块152的界面层242之上布置的重构的晶片134，凸块152朝着界面层242定向并且与界面层242接触。载体240包含牺牲基底材料，诸如硅、聚合物、氧化铍、玻璃或其他适当的低成本、刚性材料，以用于结构支撑。在载体240之上形成界面层或双面胶带242作为临时粘附接合膜、蚀刻停止层或热释放层。
通过使用激光器246的LDA贯穿密封剂138的表面156形成多个通孔244。替代地，通过机械钻孔、深反应离子蚀刻（DRIE）或其他适当的形成工艺来形成通孔244。通孔244完全贯穿密封剂138从表面144延伸到表面156。
在图11b中，使用电解电镀、非电解镀工艺或其他适当的沉积工艺来用Al、Cu、Sn、Ni、Au、Ag、Ti、W或其他适当的导电材料填充通孔244，以形成导电通孔248。导电通孔248完全贯穿密封剂138延伸以提供在密封剂138的表面144和156之间的电气互连。导电层146的一部分连接到导电通孔248。
使用诸如印刷、PVD、CVD、溅射、电解电镀和非电解镀的图案化和金属沉积工艺在导电通孔248和密封剂138的表面156之上形成导电层或RDL 250。导电层250包括Al、Cu、Sn、Ni、Au、Ag或其他适当的导电材料的一个或多个层。导电层250的一部分电气连接到导电通孔248，并且操作为电气连接到导电通孔248的接触焊盘。导电层250的其他部分根据半导体管芯104的设计和功能被电气共用或电气隔离，并且半导体器件随后安装在导电层250之上。
在图11c中，使用锯片或激光切割工具252来将重构的晶片134单体化成个别的半导体器件260。在单体化之后，使用热烘烤、UV光或机械剥离来从载体240和界面层242释放半导体器件260。
图12示出了包括堆叠的半导体器件260的半导体封装262。顶部半导体器件260的凸块152电气地并且冶金地连接到底部半导体器件260的导电层250。导电通孔248将顶部半导体器件260内的半导体管芯104电气连接到底部半导体器件260内的半导体管芯104。可以在半导体封装262内堆叠任何数目的半导体器件260。顶部半导体器件260包括用于附加器件集成的接触焊盘250。在半导体封装262内结合作为顶部器件的半导体器件260创建开放堆叠配置，即，允许附加半导体器件或组件被堆叠在顶部半导体器件260之上并且与顶部半导体器件260电气连接的配置。堆叠多个器件和组件增加了半导体封装262的总体电气性能和功能。
在半导体管芯104的表面120上形成背侧保护层122。背侧保护层122加强并且保护半导体器件260内的半导体管芯104。背侧保护层122在环境上保护半导体管芯104，并且提供刚性和物理支撑，以加强半导体管芯104。背侧保护层122降低了下述可能性：半导体管芯104将在处理和其他制造工艺期间，例如在密封剂138的沉积期间，或者在形成导电通孔248和导电层250期间被损坏。背侧保护层122降低了半导体管芯104将在半导体器件260的堆叠期间被损坏的可能性。良好半导体封装262的生产量由于背侧保护层122使得半导体管芯104和半导体器件260不太容易受到损坏而增加。
因为半导体管芯104的厚度在图1d中所示的背面研磨操作中被减小，所以半导体器件262具有减小的z维度。因为保护层116在背面研磨期间支撑半导体管芯104，并且背侧保护层122在背面研磨之后支撑半导体管芯104，所以从半导体管芯104去除更大部分的基底衬底材料102。因此，半导体管芯104和半导体器件260的厚度被减小。减少半导体器件的厚度减少了半导体封装262的总的z维度。
贯穿密封剂138形成导电通孔248提供了贯穿半导体器件260的垂直互连。形成具有垂直互连结构的半导体器件260允许多个半导体管芯和器件在半导体封装262内被堆叠。结合多个半导体管芯和器件增加了半导体封装262的总体电气性能和功能性。
图13图示了包括在图11c的半导体器件260之上布置的图9的半导体器件230的半导体封装264。半导体器件230的凸块220电气地并且冶金地连接到半导体器件260的导电层250。半导体器件230中的半导体管芯104通过凸块114、导电层216、凸块220、导电层250、TSV248和导电层146电气连接到凸块152以用于外部互连。导电通孔248提供贯穿半导体器件260的垂直互连，并且将半导体器件230中的半导体管芯104电气连接到半导体器件260中的半导体管芯104。
在半导体封装264内结合作为顶部半导体器件的半导体器件230创建封闭的堆叠配置，即，不允许附加半导体器件或组件在顶部半导体器件之上堆叠并且与顶部半导体器件电气连接的配置。然而，任何数目的半导体器件260或其他半导体组件可以在半导体器件230和半导体器件260之间堆叠或者在与半导体器件230相对的半导体器件260之上堆叠。
背侧保护层222覆盖半导体管芯104的后表面120以及密封剂208的表面。背侧保护层222在环境上保护半导体管芯104免受外部元件的影响，并且提供刚性并且物理支撑以加强半导体器件230。由于背侧保护层222的存在，半导体器件230在处理和加工期间不太容易受到损坏。例如，背侧保护层222降低了半导体器件230将在半导体器件230附连到半导体器件260期间被损坏的可能性。良好半导体封装264的总体功能和生产量由于背侧保护层222使得半导体器件230不太容易受到损坏而增加。
在半导体管芯104的表面120上形成背侧保护层122。背侧保护层122加强并且保护半导体器件260内的半导体管芯104。背侧保护层122降低了半导体管芯104将在处理或其他制造工艺期间被损坏的可能性。背侧保护层122还降低了半导体器件260将在半导体器件230的附连到半导体器件260期间被损坏的可能性。良好半导体封装264的生产量由于背侧保护层122使得半导体器件260不太容易受到损坏而增加。
因为半导体器件230和260内的半导体管芯104的厚度在图1d中所示的背面研磨操作中被减小，所以半导体封装264具有减小的z维度。因为保护层116在背面研磨期间支撑半导体管芯104，并且背侧保护层122和222在背面研磨之后提供刚性并且支撑半导体管芯104，所以从半导体管芯104去除更大部分的基底衬底材料102。因此，半导体管芯104和半导体器件230和260的厚度被减小。减小半导体器件230和260的厚度减小了半导体封装262的总的z维度。
贯穿密封剂138形成的导电通孔248提供了贯穿半导体器件260的垂直互连。形成具有垂直互连结构的半导体器件260允许半导体器件230在半导体器件260之上被堆叠。在半导体封装264内结合多个半导体器件提高了半导体封装262的电气性能和总体功能。
尽管已经详细说明了本发明的一个或多个实施例，但是本领域技术人员将领会的是，对这些实施例的修改和适配可以在不背离如所附权利要求中所阐述的本发明的范围的情况下进行。

Claims (15)

1.一种制造半导体器件的方法，包括：
提供半导体管芯；
在半导体管芯上形成背侧保护层；
在载体上布置半导体管芯，其中背侧保护层位于半导体管芯和载体之间；
在将所述半导体管芯布置所述载体上之后，在所述半导体管芯上沉积密封剂，其中所述密封剂基本上覆盖所述半导体管芯的有源表面和侧表面；
在半导体管芯的有源表面上平坦化密封剂；和
在所述密封剂上形成导电层并使导电层电连接到所述半导体管芯。
2.根据权利要求1所述的方法，还包括固化背侧保护层。
3.根据权利要求2所述的方法，还包括单体化所述背侧保护层和密封剂。
4.根据权利要求1所述的方法，还包括在半导体管芯和背侧保护层上布置散热器。
5.根据权利要求1所述的方法，其中所述半导体管芯的表面与所述密封剂的表面共面。
6.根据权利要求1所述的方法，还包括：
在半导体管芯的有源表面上形成焊料凸块；
将密封剂沉积在焊料凸块上；和
平坦化密封剂以暴露出焊料凸块，其中密封剂的表面与焊料凸块的表面共面。
7.一种制造半导体器件的方法，包括：
提供半导体管芯；
在半导体管芯的有源表面上形成凸块；
在半导体芯片的有源表面上沉积密封剂；
在所述半导体芯片的有源表面上平坦化密封剂以暴露出所述凸块；和
在密封剂和凸块上形成导电层。
8.根据权利要求7所述的方法，还包括沉积所述密封剂，使得所述密封剂基本上覆盖所述半导体管芯的有源表面和侧表面。
9.根据权利要求7所述的方法，其中所述密封剂的表面在平坦化后与所述凸块的表面共面。
10.根据权利要求7所述的方法，还包括在导电层上形成导电通孔通过密封剂。
11.一种半导体器件，包括：
半导体管芯；
凸起，形成在半导体管芯的有源表面上；
密封剂，沉积在凸块和半导体管芯的有源表面上，其中密封剂的表面与凸块的表面共面；和
导电层，形成在所述密封剂的表面和所述凸块的表面上。
12.根据权利要求11所述的半导体器件，还包括在导电层上形成通过密封剂的导电通孔。
13.根据权利要求11所述的半导体器件，还包括形成通过半导体管芯的硅通孔。
14.根据权利要求11所述的半导体器件，还包括布置在密封剂上与导电层相对的散热器。
15.根据权利要求11所述的半导体器件，还包括形成在半导体管芯上与凸块相对的背侧保护层。
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KR102045175B1 (ko) 2019-11-14
EP3125283A3 (en) 2017-04-19
CN106409699A (zh) 2017-02-15
EP3125283A2 (en) 2017-02-01
TWI655692B (zh) 2019-04-01
TW201705315A (zh) 2017-02-01
US9899285B2 (en) 2018-02-20
CN106409699B (zh) 2022-07-08
KR20190019998A (ko) 2019-02-27
KR20170015260A (ko) 2017-02-08
US20170033026A1 (en) 2017-02-02

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