TWI534974B - 半導體裝置以及形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的基板之方法 - Google Patents

半導體裝置以及形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的基板之方法 Download PDF

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TWI534974B
TWI534974B TW100130046A TW100130046A TWI534974B TW I534974 B TWI534974 B TW I534974B TW 100130046 A TW100130046 A TW 100130046A TW 100130046 A TW100130046 A TW 100130046A TW I534974 B TWI534974 B TW I534974B
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conductive layer
substrate
recess
semiconductor
semiconductor die
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TW100130046A
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TW201222756A (en
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瑞莎Ａ 派蓋菈
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史達晶片有限公司
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Description

半導體裝置以及形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的基板之方法
本發明大體上關於半導體裝置，且更明確地說，係關於半導體裝置以及形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的晶圓級基板或引線架之方法。
在現代的電子產品中經常會發現半導體裝置。半導體裝置會有不同數量與密度的電組件。離散式半導體裝置通常含有一種類型的電組件，舉例來說，發光二極體(Light Emitting Diode，LED)、小訊號電晶體、電阻器、電容器、電感器、以及功率金屬氧化物半導體場效電晶體(Metal Oxide Semiconductor Field Effect Transistor，MOSFET)。整合式半導體裝置通常含有數百個至數百萬個電組件。整合式半導體裝置的範例包含微控制器、微處理器、電荷耦合裝置(Charged-Coupled Device，CCD)、太陽能電池、以及數位微鏡裝置(Digital Micro-mirror Device，DMD)。
半導體裝置會實施各式各樣的功能，例如，訊號處理、高速計算、傳送與接收電磁訊號、控制電子裝置、將太陽光轉換成電能、以及產生電視顯示器的視覺投影。在娛樂領域、通訊領域、電力轉換領域、網路領域、電腦領域、以及消費性產品領域中皆會發現半導體裝置。在軍事應用、航空、自動車、工業控制器、以及辦公室設備中同樣會發現半導體裝置。
半導體裝置會利用半導體材料的電氣特性。半導體材料的原子結構會使得可藉由施加電場或基礎電流或是經由摻雜的處理來操縱其導電性。摻雜會將雜質引入至該半導體材料之中，用以操縱及控制該半導體裝置的傳導性。
一半導體裝置會含有主動式電氣結構與被動式電氣結構。主動式結構(其包含雙極電晶體與場效電晶體)會控制電流的流動。藉由改變摻雜的程度以及施加電場或基礎電流，該電晶體會提高或限制電流的流動。被動式結構(其包含電阻器、電容器、以及電感器)會創造用以實施各式各樣電功能所需要的電壓和電流之間的關係。該等被動式結構與主動式結構會被電連接以形成讓該半導體裝置實施高速計算及其它實用功能的電路。
半導體裝置通常會使用兩種複雜的製程來製造，也就是，前端製造以及後端製造，每一者皆可能涉及數百道步驟。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。每一個晶粒通常會相同並且含有藉由電連接主動式組件和被動式組件而形成的電路。後端製造涉及從已完成的晶圓中單體化裁切個別的晶粒並且封裝該晶粒，用以提供結構性支撐及環境隔離。
半導體製造的其中一個目標便係生產較小的半導體裝置。較小的裝置通常會消耗較少電力，具有較高效能，並且能夠更有效地生產。此外，較小的半導體裝置還會有較小的覆蓋面積，這係較小的末端產品所需要的。藉由改善前端製程可以達成較小的晶粒尺寸，從而導致具有較小以及較高密度之主動式組件和被動式組件的晶粒。後端製程可以藉由改善電互連材料及封裝材料而導致具有較小覆蓋面積的半導體裝置封裝。
半導體裝置通常會被堆疊或被鑲嵌至一基板，以達有效的整合。已知的係，半導體裝置和基板之間的電互連(舉例來說，凸塊互連)在熱應力或機械應力的作用下會脫離或脫層。先前技術已經使用數種不同的技術來製造更耐用的電互連。舉例來說，該等凸塊會被回焊或擠壓至一引線的穿孔或孔洞之中，用以形成一機械性接合。然而，接合強度會受限於該機械性接合的表面之間的剪力強度。
本技術領域需要提供一種不會受到熱應力與機械應力破壞的電互連接合。據此，於其中一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一基板，其具有第一表面與第二反向表面；在該基板的該第一表面上形成一第一抗蝕刻阻劑傳導層；以及在該基板中蝕刻複數個第一凹處，俾便穿過該第一抗蝕刻阻劑傳導層中的一開口。該等第一凹處的寬度大於該第一抗蝕刻阻劑傳導層中的該開口的寬度。該方法還進一步包含下面步驟：在該等第一抗蝕刻阻劑傳導層的多個部分之間於該基板中蝕刻複數個第二凹處；提供一半導體晶粒，其具有被形成在該半導體晶粒的一主動表面上的多個接觸觸墊上的複數個凸塊；利用被設置在該第一抗蝕刻阻劑傳導層上的該等凸塊將該半導體晶粒鑲嵌至該基板；回焊該等凸塊，以便電連接至該第一抗蝕刻阻劑傳導層並且讓凸塊材料流入該等第一凹處之中；將一囊封劑沉積在該半導體晶粒與基板上；以及往下移除該基板的第二表面的一部分直到該等第二凹處為止，用以在該第一抗蝕刻阻劑傳導層的下方形成多條電隔離的基礎引線。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一基板，其具有第一表面與第二反向表面；在該基板的該第一表面上形成一第一傳導層；在該基板中形成一第一凹處，俾便穿過該第一傳導層中的一開口；在該基板的該第二表面上形成一第二傳導層；在該第一傳導層或第二傳導層的多個部分之間於該基板中形成一第二凹處；將一半導體晶粒鑲嵌至該第一傳導層或第二傳導層；將一囊封劑沉積在該半導體晶粒與基板上；以及往下移除該基板的一部分直到該第二凹處為止，用以在該等第一傳導層與第二傳導層之間形成多條電隔離的基礎引線。
於另一實施例中，本發明係一種製造半導體裝置的方法，其包括下面步驟：提供一基板；在該基板的一第一表面上形成一第一傳導層；在該基板中形成一凹處，俾便穿過該第一傳導層中的一開口；將一半導體晶粒鑲嵌至該基板；將一囊封劑沉積在該半導體晶粒與基板上；以及移除該基板的一部分，用以在該第一傳導層的下方形成多條電隔離的基礎引線。
於另一實施例中，本發明係一種半導體裝置，其包括一基板以及被形成在該基板的一第一表面上的第一傳導層，其在該基板中會形成一凹處，俾便穿過該第一傳導層中的一開口。一半導體晶粒會被鑲嵌在該基板上。一囊封劑會被沉積在該半導體晶粒與基板上。該基板的一部分會被移除，用以在該第一傳導層的下方形成多條電隔離的基礎引線。
下面的說明書中會參考圖式於一或多個實施例中來說明本發明，於該等圖式中，相同的符號代表相同或雷同的元件。雖然本文係以達成本發明目的的最佳模式來說明本發明；不過，熟習本技術的人士便會明白，本發明希望涵蓋受到下面揭示內容及圖式支持的隨附申請專利範圍及它們的等效範圍所定義的本發明的精神與範疇內可能併入的替代例、修正例、以及等效例。
半導體裝置通常會使用兩種複雜的製程來製造：前端製造和後端製造。前端製造涉及在一半導體晶圓的表面上形成複數個晶粒。該晶圓上的每一個晶粒皆含有主動式電組件和被動式電組件，它們會被電連接而形成功能性電路。主動式電組件(例如電晶體與二極體)能夠控制電流的流動。被動式電組件(例如電容器、電感器、電阻器、以及變壓器)會創造用以實施電路功能所需要的電壓和電流之間的關係。
被動式組件和主動式組件會藉由一連串的製程步驟被形成在該半導體晶圓的表面上方，該等製程步驟包含：摻雜、沉積、光微影術、蝕刻、以及平坦化。摻雜會藉由下面的技術將雜質引入至半導體材料之中，例如：離子植入或是熱擴散。摻雜製程會修正主動式裝置中半導體材料的導電性，將該半導體材料轉換成絕緣體、導體，或是響應於電場或基礎電流來動態改變半導體材料傳導性。電晶體含有不同類型和摻雜程度的多個區域，它們會在必要時被排列成用以在施加該電場或基礎電流時讓該電晶體可以提高或限制電流的流動。
主動式組件和被動式組件係由具有不同電氣特性的多層材料所構成。該等層能夠藉由各式各樣的沉積技術來形成，該等沉積技術部分取決於要被沉積的材料的類型。舉例來說，薄膜沉積可能包含：化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、電解質電鍍製程、以及無電極電鍍製程。每一層通常都會被圖樣化，以便形成主動式組件、被動式組件、或是組件之間的電連接線的一部分。
該等層能夠利用光微影術被圖樣化，其涉及在要被圖樣化的層的上方沉積光敏材料，舉例來說，光阻。一圖樣會利用光從一光罩處被轉印至該光阻。該光阻圖樣中受到光作用的部分會利用溶劑移除，從而露出下方層之中要被圖樣化的部分。該光阻中的剩餘部分會被移除，從而留下一已圖樣化層。或者，某些類型的材料會利用無電極電鍍以及電解質電鍍之類的技術將該材料直接沉積至由先前沉積及/或蝕刻製程所形成的區域或空隙(void)之中而被圖樣化。
在一既有圖樣的上方沉積一薄膜材料可能會擴大下方圖樣並且產生一不均勻平坦的表面。生產較小且更密集封裝的主動式組件和被動式組件需要用到均勻平坦的表面。平坦化作用可用來從晶圓的表面處移除材料，並且產生一均勻平坦的表面。平坦化作用涉及利用一研磨墊來研磨晶圓的表面。有磨蝕作用的材料以及腐蝕性的化學藥劑會在研磨期間被加到該晶圓的表面。由化學藥劑的磨蝕性作用及腐蝕性作用所組成的組合式機械作用會移除任何不規律的拓樸形狀，從而產生一均勻平坦的表面。
後端製造係指將已完成的晶圓切割或單體化裁切成個別晶粒，並且接著封裝該晶粒，以達結構性支撐及環境隔離的效果。為單體化裁切該晶粒，晶圓會沿著該晶圓中被稱為切割道(saw street)或切割線(scribe)的非功能性區域被刻痕並且折斷。該晶圓會利用雷射切割工具或鋸片來進行單體化裁切。經過單體化裁切之後，個別晶粒便會被鑲嵌在包含接針或接觸觸墊的封裝基板上，以便和其它系統組件進行互連。被形成在該半導體晶粒上方的接觸觸墊接著會被連接至該封裝裡面的接觸觸墊。該等電連接線可利用焊料凸塊、短柱凸塊、導電膏、或是焊線來製成。一囊封劑或是其它模造材料會被沉積在該封裝的上方，用以提供物理性支撐和電隔離。接著，該已完成的封裝便會被插入一電氣系統之中並且讓其它系統組件可取用該半導體裝置的功能。
圖1圖解一電子裝置50，其具有一晶片載體基板或是印刷電路板(Printed Circuit Board，PCB)52，在其表面上鑲嵌著複數個半導體封裝。電子裝置50可能具有一類型的半導體封裝或是多種類型的半導體封裝，端視應用而定。為達解釋的目的，圖1中顯示不同類型的半導體封裝。
電子裝置50可能係一單機型系統，其會使用該等半導體封裝來實施一或多項電功能。或者，電子裝置50可能係一較大型系統中的一子組件。舉例來說，電子裝置50可能係一蜂巢式電話、一個人數位助理(Personal Digital Assistant，PDA)、一數位錄像機(Digital Video Camera，DVC)、或是其它電子通訊裝置的一部分。或者，電子裝置50可能係一圖形卡、一網路介面卡、或是能夠被插入一電腦之中的其它訊號處理卡。該半導體封裝可能包含：微處理器、記憶體、特定應用積體電路(Application Specific Integrated Circuits，ASIC)、邏輯電路、類比電路、RF電路、離散式裝置、或是其它半導體晶粒或電組件。此等產品要被市場接受，微型化以及減輕重量很重要。半導體裝置之間的距離必須縮短，以便達到更高的密度。
在圖1中，PCB 52提供一通用基板，用以結構性支撐及電互連被鑲嵌在該PCB之上的半導體封裝。多條導體訊號線路54會利用下面製程被形成在PCB 52的一表面上方或是多層裡面：蒸發製程、電解質電鍍製程、無電極電鍍製程、網印製程、或是其它合宜的金屬沉積製程。訊號線路54會在該等半導體封裝、被鑲嵌的組件、以及其它外部系統組件中的每一者之間提供電通訊。線路54還會提供連接至每一個該等半導體封裝的電力連接線及接地連接線。
於某些實施例中，一半導體裝置會有兩個封裝層。第一層封裝係一種用於以機械方式及電氣方式將該半導體晶粒附接至一中間載板的技術。第二層封裝則涉及以機械方式及電氣方式將該中間載板附接至該PCB。於其它實施例中，一半導體裝置可能僅有該第一層封裝，其中，該晶粒會以機械方式及電氣方式直接被鑲嵌至該PCB。
為達解釋的目的，圖中在PCB 52之上顯示數種類型的第一層封裝，其包含焊線封裝56以及覆晶58。除此之外，圖中還顯示被鑲嵌在PCB 52之上的數種類型第二層封裝，其包含：球柵陣列(Ball Grid Array，BGA)60；凸塊晶片載板(Bump Chip Carrier，BCC)62；雙直列封裝(Dual In-line Package，DIP)64；平台格柵陣列(Land Grid Array，LGA)66；多晶片模組(Multi-Chip Module，MCM)68；方形扁平無引線封裝(Quad Flat Non-leaded package，QFN)70；以及方形扁平封裝72。端視系統需求而定，被配置成由具有第一層封裝樣式和第二層封裝樣式之任何組合以及其它電子組件所組成的任何半導體封裝組合皆能夠被連接至PCB 52。於某些實施例中，電子裝置50包含單一附接半導體封裝；而其它實施例則可能要求多個互連封裝。藉由在單一基板上方組合一或多個半導體封裝，製造商便能夠將事先製造的組件併入電子裝置和系統之中。因為該等半導體封裝包含精密的功能，所以，電子裝置能夠使用較便宜的組件及有效率的製程來製造。所產生的裝置比較不可能失效而且製造價格較低廉，從而會降低消費者的成本。
圖2a至2c所示的係示範性半導體封裝。圖2a所示的係被鑲嵌在PCB 52之上的DIP 64的進一步細節。半導體晶粒74包含一含有類比電路或數位電路的主動區，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、傳導層、以及介電層，並且會根據該晶粒的電氣設計來進行電互連。舉例來說，該電路可能包含被形成在半導體晶粒74的該主動區裡面的一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。接觸觸墊76係一或多層導體材料(例如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或是銀(Ag))，並且會被電連接至形成在半導體晶粒74裡面的電路元件。在DIP 64的組裝期間，半導體晶粒74會利用一金-矽共熔合金層或是膠黏材料(例如熱環氧樹脂或環氧樹脂)被鑲嵌在一中間載板78上。該封裝主體包含一絕緣封裝材料，例如聚合物或是陶瓷。導體引線80以及焊線82會在半導體晶粒74與PCB 52之間提供電互連。囊封劑84會被沉積在該封裝的上方，防止濕氣和粒子進入該封裝並污染晶粒74或焊線82，以便達到環境保護的目的。
圖2b所示的係被鑲嵌在PCB 52之上的BCC 62的進一步細節。半導體晶粒88會利用底層填充材料或環氧樹脂膠黏材料92會被鑲嵌在載板90的上方。焊線94會在接觸觸墊96與98之間提供第一層封裝互連。模造化合物或囊封劑100會被沉積在半導體晶粒88和焊線94的上方，用以為該裝置提供物理性支撐以及電隔離效果。多個接觸觸墊102會利用合宜的金屬沉積製程(例如電解質電鍍或無電極電鍍)被形成在PCB 52的一表面上方，用以防止氧化。接觸觸墊102會被電連接至PCB 52中的一或多條導體訊號線路54。多個凸塊104會被形成在BCC 62的接觸觸墊98和PCB 52的接觸觸墊102之間。
在圖2c中，半導體晶粒58會利用覆晶樣式的第一層封裝以面朝下的方式被鑲嵌至中間載板106。半導體晶粒58的主動區108含有類比電路或數位電路，該等類比電路或數位電路會被施行為根據該晶粒的電氣設計所形成的主動式裝置、被動式裝置、傳導層、以及介電層。舉例來說，該電路可能包含被形成在主動區108裡面的一或多個電晶體、二極體、電感器、電容器、電阻器、以及其它電路元件。半導體晶粒58會經由多個凸塊110以電氣方式及機械方式被連接至載板106。
BGA 60會以利用多個凸塊112的BGA樣式第二層封裝以電氣方式及機械方式被連接至PCB 52。半導體晶粒58會經由凸塊110、訊號線114、以及凸塊112被電連接至PCB 52中的導體訊號線路54。一模造化合物或囊封劑116會被沉積在半導體晶粒58和載板106的上方，用以為該裝置提供物理性支撐以及電隔離效果。該覆晶半導體裝置會從半導體晶粒58上的該等主動式裝置處至PCB 52上的傳導軌提供一條短的電傳導路徑，以便縮短訊號傳播距離、降低電容、並且改善整體電路效能。於另一實施例中，該半導體晶粒58會利用覆晶樣式的第一層封裝以機械方式及電氣方式直接被連接至PCB 52，而沒有中間載板106。
圖3a顯示一半導體晶圓120，其具有一基板材料122，例如，矽、鍺、砷化鎵、磷化銦、或是碳化矽，用以達到結構性支撐的目的。如上面所述，複數個半導體晶粒或組件124會被形成在晶圓120之上，藉由切割道126來分離。
圖3b所示的係半導體晶圓120的一部分的剖視圖。每一個半導體晶粒124都有一背表面128與一含有類比電路或數位電路的主動表面130，該等類比電路或數位電路會被施行為被形成在該晶粒裡面的主動式裝置、被動式裝置、傳導層、以及介電層，並且會根據該晶粒的電氣設計來進行電互連。舉例來說，該電路可能包含被形成在主動表面130裡面的一或多個電晶體、二極體、以及其它電路元件，用以施行類比電路或數位電路，例如，數位訊號處理器(Digital Signal Processor，DSP)、ASIC、記憶體、或是其它訊號處理電路。半導體晶粒124可能還含有用於RF訊號處理的整合被動元件(IPD)，例如，電感器、電容器、以及電阻器。
一導電層132會使用PVD製程、CVD製程、電解質電鍍製程、無電極電鍍製程、或是其它合宜的金屬沉積製程被形成在主動表面130上方。傳導層132可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。傳導層132的操作如同被電連接至主動表面130上之該等電路的接觸觸墊。多個凸塊134會被形成在接觸觸墊132上。於其中一實施例中，半導體晶粒124係一覆晶類型的半導體晶粒。
在圖3c中，半導體晶圓120會利用鋸片或雷射切割工具136經由切割道(saw street)126被單體化裁切成個別的半導體晶粒124。每一個半導體晶粒124皆會有被形成在接觸觸墊132上方的多個凸塊134。
圖4a至4k配合圖1以及2a至2c來圖解一用以形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的晶圓級基板的製程。圖4a所示的係一晶圓級基板或引線架140，其含有Cu、Cu合金、Al、或是其它合宜的導體材料。基板140具有表面142以及反向表面144。如下面所述，晶圓級基板140具有用以處理多個半導體晶粒的足夠面積。
在圖4b中，一抗蝕刻阻劑傳導層146會利用圖樣化以及電解質電鍍或無電極電鍍製程被形成在基板140的表面142上方。基板140上方的傳導層146的位置會對應於隨後被鑲嵌的半導體晶粒的凸塊場所。一開口148會被形成在傳導層146之每一部分的中央區域中。該開口148可藉由選擇性圖樣化或是藉由移除一部分的傳導層146來形成。圖4c所示的係基板140上方的傳導層146中的多個開口148的平面圖。
一抗蝕刻阻劑傳導層150同樣會利用圖樣化以及電解質電鍍或無電極電鍍製程被形成在基板140的表面144上方。傳導層146與150可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。於其中一實施例中，傳導層146與150係一已事先電鍍引線架上的Ag或Au(Ag/PPF電鍍)。傳導層146與150的操作如同稍後被鑲嵌的半導體晶粒的接觸觸墊或互連結構，例如，凸塊。
在圖4d中，基板140會被部分蝕刻穿過表面142，用以穿過開口148形成凹處152。該蝕刻製程還會在傳導層146的多個部分之間形成多個凹處154。用以形成凹處152與154的蝕刻係利用一鹼性等向濕式蝕刻阻劑來實施。傳導層146與150的Ag/PPF電鍍本質會抵抗該蝕刻製程。該蝕刻阻劑在移除基板140裡面的材料時的反應會比移除傳導層146與150的反應更為激烈。因此，凹處152的內部區域A會寬於開口148的直徑或寬度D，如圖4e中所示。該等凹處154會創造多列基礎引線或凸出部140a、140b、140c、140d、140e、以及140f，它們係延伸自剩餘的基板140g。於其中一實施例中，凹處152會被蝕刻至50至75微米(μm)的深度，以便確保會有耐用的基礎引線140a至140f。
在圖4f至4g中，圖3a至3c中的半導體晶粒124會利用一拾取與放置操作被定位在基礎引線140a至140f上方的傳導層146並且被鑲嵌至傳導層146。多個凸塊134會以冶金方式及電氣方式被連接至傳導層146並且藉由回焊與加壓的方式置於凹處152之中。一作用力F會被施加至半導體晶粒124的背表面128，用以幫助將液狀的凸塊材料插置在凹處152之中。用以將凸塊134扣接在凹處152裡面所需要的作用力會在真空中達成。於短柱凸塊的情況中，可以使用熱擠壓接合來將凸塊134扣接在凹處152裡面。假設內部區域A寬於開口148的寬度W，凸塊134會被鎖定至基礎引線140a至140f。由於開口148的較寬內部區域A及較窄寬度W的本質的關係，凸塊134非常耐用，不會與傳導層146脫離。也就是，較寬內部區域A裡面已硬化的凸塊材料不會通過傳導層146中開口148的較窄寬度W。於另一實施例中，一或多個離散式半導體組件會被鑲嵌至基礎引線140a至140f上方的傳導層146。
圖4h所示的另一實施例中，凸塊材料155會在鑲嵌半導體晶粒124之前先被沉積至凹處152之中。該已事先沉積的凸塊材料會在回焊期間以冶金方式來連結凸塊134，以便形成凸塊鎖定特徵。
在圖4i中，一囊封劑或模造化合物156會利用焊膏印刷(paste printing)塗敷機、壓縮模造(compressive molding)塗敷機、轉印模造(transfer molding)塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124與基板140的上方，其包含被沉積在凹處154之中以及基礎引線140a至140f附近。囊封劑156可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑156係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物破壞。一旦被囊封之後，大部分的半導體晶粒124(其具有被鎖定至基礎引線140a至140f的多個凸塊134)便會進一步降低脫層的發生機率。
在圖4j中，一部分的基板140g會藉由一蝕刻製程被移除，用以將基礎引線140a至140f分離並且電隔離成由基板140的蝕刻後區域所定義的多列。傳導層146與150的Ag/PPF電鍍本質會抵抗該蝕刻製程。該蝕刻阻劑在移除基板140裡面的材料時的反應會比移除傳導層146與150的反應更為激烈。因此，基板140中介於傳導層150之間的部分會被移除，因為沒有反向的傳導層146與150。相反地，因為該等傳導層的抗蝕刻阻劑本質的關係，基板140中介於反向傳導層146與150之間的部分(也就是，基礎引線140a至140f)以及傳導層146與150在該蝕刻製程之後仍會保持完整。基礎引線140a至140f會為半導體晶粒124提供垂直的電連接。
在圖4k中，晶圓級基板140會利用鋸片或雷射切割工具158被單體化裁切穿過囊封劑156，用以分離該半導體晶粒並且提供個別的埋置晶圓級球柵陣列(embedded Wafer-Level Ball grid array，eWLB)、晶圓級晶片規模封裝(Wafer Level Chip Scale Package，WLCSP)、以及方形扁平包裝無負載(Quad Flat pack Non-loaded，QFN)半導體封裝160，以便作進一步整合。
圖5所示的係在單體化裁切之後的其中一種此類半導體封裝160。半導體晶粒124會被電連接至基礎引線140a至140f以及傳導層146與150。凸塊134會在回焊期間被鎖定至凹處152，以便達到不會受熱應力與機械應力影響的強韌接合效果。凸塊材料流入凹處152之中會減少橫向流動並且降低和相鄰基礎引線發生電氣短路的風險。在更高的I/O數中，基礎引線之間的間距會縮減。
圖6a至6f配合圖1以及2a至2c來圖解用以形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的晶圓級基板的另一製程。接續圖4d，凸塊材料162會利用蒸發製程、電解質電鍍製程、無電極電鍍製程、丸滴製程(ball drop)、或是網印製程被沉積在傳導層146上方以及凹處152之中。該凸塊材料可能係Al、Sn、Ni、Au、Ag、Pb、Bi、Cu、焊料、以及它們的組合，其會有一非必要的助熔溶劑。舉例來說，該凸塊材料可能是Sn/Pb共熔合金、高鉛焊料、或是無鉛焊料。
在圖6b與6c中，圖3a至3c的半導體晶粒124(在本案例中並沒有凸塊134)會利用一拾取與放置操作被定位在傳導層146與凸塊材料162上方並且被鑲嵌至傳導層146與凸塊材料162。半導體晶粒124的接觸觸墊132會藉由在回焊溫度與壓力下回焊凸塊材料162而以冶金方式及電氣方式被連接至傳導層146，以便形成電互連線164。假設內部區域A寬於開口148的寬度W，電互連線164會被鎖定至基礎引線140a至140f。因為開口148的較寬內部區域A及較窄寬度W的本質的關係，該電互連線164非常耐用，不會與傳導層146脫離。也就是，較寬內部區域A裡面已硬化的凸塊材料162不會通過傳導層146中開口148的較窄寬度W。於另一實施例中，一或多個離散式半導體組件會被鑲嵌在基礎引線140a至140f上方。
在圖6d中，一囊封劑或模造化合物166會利用焊膏印刷塗敷機、壓縮模造塗敷機、轉印模造塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124與基板140的上方，其包含被沉積在凹處154之中以及基礎引線140a至140f附近。囊封劑166可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑166係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物破壞。一旦被囊封之後，大部分的半導體晶粒124(其具有被鎖定至基礎引線140a至140f的多條電互連線164)便會進一步降低脫層的發生機率。
在圖6e中，一部分的基板140g會藉由一蝕刻製程被移除，用以將基礎引線140a至140f分離並且電隔離成由基板140的蝕刻後區域所定義的多列。傳導層146與150的Ag/PPF電鍍本質會抵抗該蝕刻製程。該蝕刻阻劑在移除基板140裡面的材料時的反應會比移除傳導層146與150的反應更為激烈。因此，基板140中介於傳導層150之間的部分會被移除，因為沒有反向的傳導層146與150。相反地，因為該等傳導層的抗蝕刻阻劑本質的關係，基板140中介於反向傳導層146與150之間的部分(也就是，基礎引線140a至140f)以及傳導層146與150在該蝕刻製程之後仍會保持完整。基礎引線140a至140f會為半導體晶粒124提供垂直的電連接。
在圖6f中，晶圓級基板140會利用鋸片或雷射切割工具168被單體化裁切穿過囊封劑166，用以分離該半導體晶粒並且提供個別的eWLB、WLCSP、以及QFN半導體封裝170，以便作進一步整合，雷同於圖5。
圖7a至7b所示的係具有該晶圓級基板或引線架之另一種排列的半導體封裝172的一實施例，雷同於圖4a至4k。在圖7a中，晶圓級基板或引線架174包含具有多個開口178的抗蝕刻阻劑傳導層176以及被形成在該基板之反向表面上的抗蝕刻阻劑傳導層180。於此情況中，傳導層176a在基板174的一中央或內部部分上方為電氣連續，在該內部傳導層176a中有複數個開口178a。傳導層176b會被形成在該內部傳導層176a附近。該等複數個開口178a會在傳導層176a的較大接觸觸墊(舉例來說，用於高電流電力連接與接地連接)下方於基板174中提供多個凹處181。傳導層176a下方的基板174中的該等多個凹處181會利用多條通道互連。傳導層176a附近的傳導層176b的每一個部分都具有針對基板174中之單一凹處181的單一開口178b。在圖7b中，在鑲嵌半導體晶粒124及沉積囊封劑156之後，雷同於圖4f至4j，該蝕刻製程會電隔離傳導層176與180之間的基礎引線174a、174b、以及174c。多個凸塊134會被回焊至被形成在基板174中的凹處181之中，以便達到凸塊鎖定特徵。被電連接至基礎引線174b的多個凸塊134具有共同電性。
圖8a至8b所示的係具有該晶圓級基板或引線架之另一種排列的半導體封裝182的一實施例，雷同於圖4a至4k。在圖8a中，晶圓級基板或引線架184包含具有多個開口188的抗蝕刻阻劑傳導層186以及被形成在該基板之反向表面上的抗蝕刻阻劑傳導層190。於此情況中，傳導層186a係被形成在基板184的一中央或內部部分上方，而在該中央傳導層186a附近的傳導層186b則會橫向細長狀。每一個傳導層186a與186b都具有針對基板184中之單一凹處189的單一開口188。在圖8b中，在鑲嵌半導體晶粒124及沉積囊封劑156之後，雷同於圖4f至4j，該蝕刻製程會電隔離傳導層186與190之間的基礎引線184a、184b、184c、以及184d。多個凸塊134會被回焊至被形成在基板184中的凹處189之中，以便達到凸塊鎖定特徵。該等橫向細長的基礎引線184a與184d可以在較高I/O數中達到互連扇出的目的。
圖9a至9g配合圖1以及2a至2c來圖解用以形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的晶圓級基板的另一製程。圖9a所示的係一晶圓級基板或引線架190，其含有Cu、Cu合金、Al、或是其它合宜的導體材料。基板190具有表面192以及反向表面194。如下面所述，晶圓級基板190具有用以處理多個半導體晶粒的足夠面積。
一抗蝕刻阻劑傳導層196會利用圖樣化以及電解質電鍍或無電極電鍍製程被形成在基板190的表面192上方。基板190上方的傳導層196的位置會對應於隨後被鑲嵌的半導體晶粒的凸塊場所。一抗蝕刻阻劑傳導層198會利用圖樣化以及電解質電鍍或無電極電鍍製程被形成在基板190的反向表面194上方。傳導層196與198可能係由下面所製成的一或多層：Al、Cu、Sn、Ni、Au、Ag、或是其它合宜的導電材料。於其中一實施例中，傳導層196與198係一已事先電鍍引線架上的Ag或Au。傳導層196與198的操作如同稍後被鑲嵌的半導體晶粒的接觸觸墊或互連結構，例如，凸塊。
一開口200會被形成在傳導層198的每一個部分的一中央區域中。該開口200可藉由選擇性圖樣化或是藉由移除一部分的傳導層198來形成。圖9b所示的係基板190上方的傳導層198中的多個開口200的平面圖。
在圖9c中，基板190會被部分蝕刻穿過表面192，用以在傳導層196的相鄰部分之間形成多個凹處202。傳導層196的Ag/PPF電鍍本質會抵抗該蝕刻製程。該蝕刻阻劑在移除基板190裡面的材料時的反應會比移除傳導層196的反應更為激烈。因此，凹處202會創造多列基礎引線或凸出部190a、190b、190c、190d、190e、以及190f，它們係延伸自剩餘的基板190g。
在圖9d中，圖3a至3c中的半導體晶粒124會利用一拾取與放置操作被定位在基礎引線190a至190f上方的傳導層196並且被鑲嵌至傳導層196。多個凸塊134會以冶金方式及電氣方式被連接至傳導層196。
在圖9e中，一囊封劑或模造化合物204會利用焊膏印刷塗敷機、壓縮模造塗敷機、轉印模造塗敷機、液體囊封劑模造塗敷機、真空層疊塗敷機、旋塗塗敷機、或是其它合宜的塗敷機被沉積在半導體晶粒124與基板190的上方，其包含被沉積在凹處202之中。囊封劑204可能係聚合物復合材料，例如，具有填充劑的環氧樹脂、具有填充劑的環氧丙烯酸酯、或是具有適當填充劑的聚合物。囊封劑204係非導體並且會為該半導體裝置提供環境保護，避免受到外部元素與污染物破壞。
基板190會被部分蝕刻，穿過表面194，用以形成穿過開口200的凹處206。傳導層198的Ag/PPF電鍍本質會抵抗該蝕刻製程。該蝕刻阻劑在移除基板190裡面的材料時的反應會比移除傳導層198的反應更為激烈。因此，凹處206的內部區域A會寬於開口200的直徑或寬度D，雷同於圖4e。於其中一實施例中，凹處206會被蝕刻至50至75微米(μm)的深度，以便確保會有耐用的基礎引線190a至190f。該蝕刻製程還會移除基板190g的部分，用以分離並且電隔離成由基板190的蝕刻後區域所定義的多列。基板190中介於傳導層198之間的部分會被移除，因為沒有反向的抗蝕刻阻劑傳導層196，所以，基礎引線190a至190f以及傳導層196與198在該蝕刻製程之後仍會保持完整。基礎引線190a至190f會為半導體晶粒124提供垂直的電連接。
在圖9f中，晶圓級基板190會利用鋸片或雷射切割工具208被單體化裁切穿過囊封劑204，用以分離該半導體晶粒並且提供個別的eWLB、WLCSP、以及QFN半導體封裝210，以便作進一步整合。
在圖9g中，PCB 212有多個接觸觸墊214，於該等接觸觸墊上沉積著凸塊材料216。半導體封裝210會被鑲嵌在接觸觸墊214的上方。凸塊材料216會被回焊，而且一作用力F會被施加至半導體封裝210的背表面128，用以幫助將液狀的凸塊材料插置在基礎引線190a至190f的凹處206之中。用以將凸塊材料216扣接在凹處206裡面所需要的作用力會在真空中達成。假設內部區域A寬於開口200的寬度W，凸塊材料216會被鎖定至基礎引線190a至190f的凹處206。由於開口200的較寬內部區域A及較窄寬度W的本質的關係，凸塊材料216非常耐用，不會與傳導層146脫離。也就是，較寬內部區域A裡面已硬化的凸塊材料不會通過傳導層198中開口200的較窄寬度W。
圖10所示的係被鑲嵌在PCB 212上方的半導體封裝210。半導體晶粒124會被電連接至基礎引線190a至190f以及傳導層196與198。凸塊材料216會在回焊期間被鎖定至凹處206，以便達到不會受熱應力與機械應力影響的強韌接合效果。凸塊材料流入凹處206之中會減少橫向流動並且降低和相鄰基礎引線發生電氣短路的風險。在更高的I/O數中，基礎引線之間的間距會縮減。
圖11a與11b所示的係具有該晶圓級基板或引線架之另一種排列的半導體封裝220的一實施例，雷同於圖9a至9g。晶圓級基板或引線架222包含抗蝕刻阻劑傳導層226以及被形成在該基板之反向表面上的具有多個開口230的抗蝕刻阻劑傳導層228。於此情況中，傳導層228在基板222的一中央或內部部分上方為電氣連續，在該內部傳導層228a中有複數個開口230a，如圖11a中所示。該等複數個開口230a會在傳導層228a的較大接觸觸墊下方於基板222中提供多個凹處232。傳導層228a下方的基板222中的該等多個凹處232會利用多條通道互連。傳導層228a附近的傳導層228b的每一個部分都具有單一開口230b。在圖11b中，在鑲嵌半導體晶粒124及沉積囊封劑204之後，雷同於圖9d至9f，該蝕刻製程會電隔離傳導層226與228之間的基礎引線222a、222b、以及222c。多個凸塊134會被回焊至被形成在基板222中的凹處232之中，以便達到凸塊鎖定特徵。被電連接至基礎引線222b的多個凸塊134具有共同電性。
雖然本文已經詳細解釋過本發明的一或多個實施例；不過，熟練的技術人士便會瞭解，可以對該些實施例進行修正與改變，其並不會脫離後面申請專利範圍中所提出的本發明的範疇。
50．．．電子裝置
52．．．印刷電路板(PCB)
54．．．線路
56．．．焊線封裝
58．．．覆晶
60．．．球柵陣列(BGA)
62．．．凸塊晶片載板(BCC)
64．．．雙直列封裝(DIP)
66．．．平台格柵陣列(LGA)
68．．．多晶片模組(MCM)
70．．．方形扁平無引線封裝(QFN)
72．．．方形扁平封裝
74．．．半導體晶粒
76．．．接觸觸墊
78．．．中間載板
80．．．導體引線
82．．．焊線
84．．．囊封劑
88．．．半導體晶粒
90．．．載板
92．．．底層填充材料或環氧樹脂膠黏材料
94．．．焊線
96．．．接觸觸墊
98．．．接觸觸墊
100．．．模造化合物或囊封劑
102．．．接觸觸墊
104．．．凸塊
106．．．中間載板
108．．．主動區
110．．．凸塊
112．．．凸塊
114．．．訊號線
116．．．模造化合物或囊封劑
120．．．半導體晶圓
122．．．基板材料
124．．．半導體晶粒或組件
126．．．切割道
128．．．背表面
130．．．主動表面
132．．．接觸觸墊
134．．．凸塊
136．．．鋸片或雷射切割工具
140．．．晶圓級基板或引線架
140a．．．基礎引線或凸出部
140b．．．基礎引線或凸出部
140c．．．基礎引線或凸出部
140d．．．基礎引線或凸出部
140e．．．基礎引線或凸出部
140f．．．基礎引線或凸出部
140g．．．剩餘的基板
142．．．表面
144．．．反向表面
146．．．抗蝕刻阻劑傳導層
148．．．開口
150．．．抗蝕刻阻劑傳導層
152．．．凹處
154．．．凹處
155．．．凸塊材料
156．．．囊封劑或模造化合物
158．．．鋸片或雷射切割工具
160．．．半導體封裝
162．．．凸塊材料
164．．．電互連線
166．．．囊封劑或模造化合物
168．．．鋸片或雷射切割工具
170．．．半導體封裝
172．．．半導體封裝
174．．．晶圓級基板或引線架
174a．．．基礎引線
174b．．．基礎引線
174c．．．基礎引線
176a．．．抗蝕刻阻劑傳導層
176b．．．抗蝕刻阻劑傳導層
178a．．．開口
178b．．．開口
180．．．抗蝕刻阻劑傳導層
181．．．凹處
182．．．半導體封裝
184．．．晶圓級基板或引線架
184a．．．基礎引線
184b．．．基礎引線
184c．．．基礎引線
184d．．．基礎引線
186a．．．抗蝕刻阻劑傳導層
186b．．．抗蝕刻阻劑傳導層
188．．．開口
189．．．凹處
190(圖8b)．．．抗蝕刻阻劑傳導層
190(圖9a)．．．晶圓級基板或引線架
190a．．．基礎引線或凸出部
190b．．．基礎引線或凸出部
190c．．．基礎引線或凸出部
190d．．．基礎引線或凸出部
190e．．．基礎引線或凸出部
190f．．．基礎引線或凸出部
190g．．．剩餘的基板
192．．．表面
194．．．反向表面
196．．．抗蝕刻阻劑傳導層
198．．．抗蝕刻阻劑傳導層
200．．．開口
202．．．凹處
204．．．囊封劑或模造化合物
206．．．凹處
208．．．鋸片或雷射切割工具
210．．．半導體封裝
212．．．PCB
214．．．接觸觸墊
216．．．凸塊材料
220．．．半導體封裝
222．．．晶圓級基板或引線架
222a．．．基礎引線
222b．．．基礎引線
222c．．．基礎引線
226．．．抗蝕刻阻劑傳導層
228a．．．抗蝕刻阻劑傳導層
228b．．．抗蝕刻阻劑傳導層
230a．．．開口
230b．．．開口
232．．．凹處
圖1所示的係一印刷電路板，在其表面上鑲嵌著不同類型的封裝；
圖2a至2c所示的係被鑲嵌在該印刷電路板上的半導體封裝的進一步細節；
圖3a至3c所示的係一半導體晶圓，其具有藉由切割道來分離的複數個半導體晶粒；
圖4a至4k所示的係一用以形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的晶圓級基板的製程；
圖5所示的係具有穿過該抗蝕刻阻劑傳導層而被回焊至該基板中用於凸塊鎖定的凹處之中的凸塊的半導體晶粒；
圖6a至6f所示的係用以形成具有用於凸塊鎖定而被形成穿過抗蝕刻阻劑傳導層之凹處的晶圓級基板的另一製程；
圖7a至7b所示的係該抗蝕刻阻劑傳導層的另一種排列，其中央部分具有被形成在該基板之中的複數個凹處；
圖8a至8b所示的係該抗蝕刻阻劑傳導層的另一種排列，其橫向細長部分係用於在該基礎載板之中形成該等凹處；
圖9a至9g所示的係用以形成具有用於凸塊鎖定材料而被形成穿過抗蝕刻阻劑傳導層之凹處的晶圓級基板的另一製程；
圖10所示的係穿過該抗蝕刻阻劑傳導層而被回焊至該基板的凹處之中的凸塊材料；以及
圖11a至11b所示的係該抗蝕刻阻劑傳導層的另一種排列，其中央部分具有被形成在該基板之中的複數個凹處。
124．．．半導體晶粒或組件
128．．．背表面
130．．．主動表面
132．．．接觸觸墊
134．．．凸塊
140．．．晶圓級基板或引線架
140a．．．基礎引線或凸出部
140b．．．基礎引線或凸出部
140c．．．基礎引線或凸出部
140d．．．基礎引線或凸出部
140e．．．基礎引線或凸出部
140f．．．基礎引線或凸出部
140g．．．剩餘的基板
142．．．表面
144．．．反向表面
146．．．抗蝕刻阻劑傳導層
148．．．開口
150．．．抗蝕刻阻劑傳導層
152．．．凹處
154．．．凹處
155．．．凸塊材料
156．．．囊封劑或模造化合物
158．．．鋸片或雷射切割工具

Claims (23)

  1. 一種製造半導體裝置的方法，其包括：提供一基板，其具有第一表面與第二反向表面；在該基板的該第一表面上形成一第一抗蝕刻阻劑傳導層；在該基板中蝕刻複數個第一凹處，俾便穿過該第一抗蝕刻阻劑傳導層中的一開口，該等第一凹處的寬度大於該第一抗蝕刻阻劑傳導層中的該開口的寬度；在該等第一抗蝕刻阻劑傳導層的多個部分之間於該基板中蝕刻複數個第二凹處；提供一半導體晶粒，其具有被形成在該半導體晶粒的一主動表面上的多個接觸觸墊上的複數個凸塊；利用被設置在該第一抗蝕刻阻劑傳導層上的該等凸塊將該半導體晶粒鑲嵌至該基板；回焊該等凸塊，以便電連接至該第一抗蝕刻阻劑傳導層並且讓凸塊材料流入該等第一凹處之中；將一囊封劑沉積在該半導體晶粒與基板上；以及往下移除該基板的第二表面的一部分直到該等第二凹處為止，用以在該第一抗蝕刻阻劑傳導層的下方形成多條電隔離的基礎引線。
  2. 如申請專利範圍第1項的方法，其中，該等第一凹處中的該凸塊材料會將該等凸塊鎖定至該等基礎引線。
  3. 如申請專利範圍第1項的方法，其進一步包含在該基板的該第二表面上形成一第二抗蝕刻阻劑傳導層。
  4. 如申請專利範圍第1項的方法，其中，該第一抗蝕刻阻劑傳導層的一部分包含複數個開口。
  5. 如申請專利範圍第1項的方法，其中，該第一抗蝕刻阻劑傳導層包含一橫向細長的部分。
  6. 如申請專利範圍第1項的方法，其進一步包含：在鑲嵌該半導體晶粒之前先在該等第一凹處中沉積凸塊材料；利用被設置在該第一抗蝕刻阻劑傳導層上的該等凸塊將該半導體晶粒鑲嵌至該基板；以及回焊該等凸塊，以便以冶金的方式連結該等第一凹處中的該凸塊材料。
  7. 一種製造半導體裝置的方法，其包括下面步驟：提供一基板，其包含第一表面與第二反向表面；在該基板的該第一表面上形成一第一傳導層；在該基板中形成一第一凹處，俾便穿過該第一傳導層中的一開口；在該基板的該第二表面上形成一第二傳導層；在該第一傳導層或第二傳導層的多個部分之間於該基板中形成一第二凹處；將一半導體晶粒鑲嵌至該第一傳導層或第二傳導層；將一囊封劑沉積在該半導體晶粒與基板上；以及往下移除該基板的一部分直到該第二凹處為止，用以在該等第一傳導層與第二傳導層之間形成多條電隔離的基礎引線。
  8. 如申請專利範圍第7項的方法，其中，該第一傳導層與第二傳導層包含一抗蝕刻阻劑材料。
  9. 如申請專利範圍第7項的方法，其中，該第一凹處的寬度大於該第一傳導層中該開口的寬度。
  10. 如申請專利範圍第7項的方法，其進一步包含：利用被設置在該第一傳導層上的凸塊材料將該半導體晶粒鑲嵌至該基板；以及回焊該凸塊材料，以便將該半導體晶粒電連接至該第一傳導層並且讓凸塊材料流入該第一凹處之中。
  11. 如申請專利範圍第7項的方法，其進一步包含：提供一印刷電路板(PCB)；以及將該半導體裝置的該等基礎引線鑲嵌至該PCB。
  12. 如申請專利範圍第7項的方法，其進一步包含：利用被設置在該第一傳導層上的凸塊將該半導體晶粒鑲嵌至該基板；以及回焊該等凸塊，以便讓凸塊材料流入該第一凹處之中。
  13. 如申請專利範圍第7項的方法，其進一步包含：將凸塊材料沉積在該第一傳導層上；以及將該凸塊材料回焊至該第一凹處之中。
  14. 一種製造半導體裝置的方法，其包括：提供一基板；在該基板的一第一表面上形成一第一傳導層；在該基板中形成一凹處，俾便穿過該第一傳導層中的一開口； 將一半導體晶粒設置於該基板上；將一凸塊材料沉積在該凹處中；以及移除該基板的一部分，用以在該第一傳導層的下方形成多條電隔離的基礎引線。
  15. 如申請專利範圍第14項的方法，其中，該第一傳導層包含一抗蝕刻阻劑材料。
  16. 如申請專利範圍第14項的方法，其中，該凹處的寬度大於該第一傳導層中該開口的寬度。
  17. 如申請專利範圍第14項的方法，其進一步包含將該凸塊材料回焊以電連接該半導體晶粒和該第一傳導層。
  18. 如申請專利範圍第14項的方法，其進一步包含在和該基板的該第一表面反向的該基板的一第二表面上形成一第二傳導層。
  19. 如申請專利範圍第14項的方法，其進一步包含藉由在該凸塊材料上設置該半導體晶粒而將該半導體晶粒鑲嵌至該基板。
  20. 一種半導體裝置，其包括：一基板；一第一傳導層，其係被形成在該基板的一第一表面上，該基板中會形成一凹處，俾便穿過該第一傳導層中的一開口；一半導體晶粒，其會被設置在該基板上；以及一凸塊材料，其被沉積在該第一傳導層上，其中該凸塊材料會延伸至該凹處之中。
  21. 如申請專利範圍第20項的半導體裝置，其中，該第一傳導層包含一抗蝕刻阻劑材料。
  22. 如申請專利範圍第20項的半導體裝置，其中，該凹處的寬度大於該第一傳導層中該開口的寬度。
  23. 如申請專利範圍第20項的半導體裝置，其進一步包含一第二傳導層，其會被形成在和該基板的該第一表面反向的該基板的一第二表面上。
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