TWI743956B - 晶片封裝結構及其形成方法 - Google Patents

晶片封裝結構及其形成方法 Download PDF

Info

Publication number
TWI743956B
TWI743956B TW109128579A TW109128579A TWI743956B TW I743956 B TWI743956 B TW I743956B TW 109128579 A TW109128579 A TW 109128579A TW 109128579 A TW109128579 A TW 109128579A TW I743956 B TWI743956 B TW I743956B
Authority
TW
Taiwan
Prior art keywords
layer
conductive
bonding pad
containing layer
package structure
Prior art date
Application number
TW109128579A
Other languages
English (en)
Other versions
TW202109806A (zh
Inventor
陳昱寰
許國經
陳承先
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202109806A publication Critical patent/TW202109806A/zh
Application granted granted Critical
Publication of TWI743956B publication Critical patent/TWI743956B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181Tantalum [Ta] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/1184Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13181Tantalum [Ta] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13184Tungsten [W] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024Applying flux to the bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8134Bonding interfaces of the bump connector
    • H01L2224/81355Bonding interfaces of the bump connector having an external coating, e.g. protective bond-through coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/8191Cleaning, e.g. oxide removal step, desmearing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/8191Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/81911Chemical cleaning, e.g. etching, flux
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/8191Cleaning, e.g. oxide removal step, desmearing
    • H01L2224/81912Mechanical cleaning, e.g. abrasion using hydro blasting, brushes, ultrasonic cleaning, dry ice blasting, gas-flow
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145Organic substrates, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3675Cooling facilitated by shape of device characterised by the shape of the housing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

提供晶片封裝結構的形成方法。此方法包含提供佈線基底。此方法包含在第一焊墊上方依序形成含鎳層和含金層。此方法包含形成導電保護層覆蓋含鎳層上方的含金層。此方法包含經由導電凸塊和圍繞導電凸塊的助焊劑層將晶片接合至佈線基底。導電凸塊在第二焊墊和晶片之間。此方法包含在導電保護層覆蓋含鎳層的同時移除助焊劑層。

Description

晶片封裝結構及其形成方法
本發明實施例是關於半導體製造技術,特別是關於晶片封裝結構及其形成方法。
半導體裝置用於各種電子應用中,例如個人電腦、手機、數位相機和其他電子設備。半導體裝置的製造通常藉由在半導體基底上方依序沉積絕緣層或介電層、導電層和半導體層,並使用光學微影製程和蝕刻製程將這些不同材料層圖案化,以在半導體基底上形成電路組件和元件。
通常在半導體晶圓上製造許多積體電路。可以在晶圓級上處理和封裝晶圓的晶粒,並且已開發了用於晶圓級封裝的各種技術。
根據一些實施例提供晶片封裝結構的形成方法。此方法包含提供佈線基底。佈線基底包含基底、第一焊墊、第二焊墊和絕緣層。第一焊墊和第二焊墊分別在基底的第一表面和第二表面上方。絕緣層在第一表面上方並部分地覆蓋第一焊墊,並且第一焊墊比第二焊墊寬。此方法包含在第一焊墊上方 依序形成含鎳層和含金層。此方法包含形成導電保護層覆蓋含鎳層上方的含金層。導電保護層、含金層和含鎳層由不同的材料製成,並且絕緣層的第一頂表面與第一焊墊的第二頂表面之間的第一距離大於導電保護層的第三頂表面與第二頂表面之間的第二距離。此方法包含經由第一導電凸塊和圍繞第一導電凸塊的第一助焊劑層將晶片接合至佈線基底。第一導電凸塊在第二焊墊和晶片之間並連接第二焊墊和晶片。此方法包含在導電保護層覆蓋含鎳層的同時移除第一助焊劑層。
根據另一些實施例提供晶片封裝結構的形成方法。此方法包含提供佈線基底。佈線基底包含基底、第一焊墊、第二焊墊和絕緣層,第一焊墊和第二焊墊分別在基底的第一表面和第二表面上方,並且絕緣層在第一表面和第一焊墊上方且具有開口,開口部分地暴露出第一焊墊。此方法包含在開口中依序形成含鎳層和含金層。此方法包含在含金層上方形成導電保護層,其中導電保護層的第一孔隙率小於含金層的第二孔隙率。此方法包含在導電保護層形成於含金層上方之後,經由第一導電凸塊將晶片接合至佈線基底的第二焊墊。此方法包含在將晶片接合至第二焊墊之後,在導電保護層上方形成導電結構。此方法包含使導電結構和導電保護層回焊,以將導電結構和導電保護層熔融並混合在一起,藉此形成第二導電凸塊。
根據又另一些實施例提供晶片封裝結構。此晶片封裝結構包含第一佈線基底,第一佈線基底包含基底、第一焊墊、第二焊墊和絕緣層,第一焊墊和第二焊墊分別位於基底的第一表面和第二表面上方,絕緣層在第一表面上方且部分地覆蓋第一焊墊,並且第一焊墊比第二焊墊寬。此晶片封裝結構包含在第一焊墊上方的含鎳層。此晶片封裝結構包含在含鎳層上方的導電保護 層。導電保護層包含錫,並且第一焊墊上方的導電保護層和絕緣層圍繞凹槽。此晶片封裝結構包含在基底的第二表面上方的晶片。此晶片封裝結構包含在第二焊墊和晶片之間的導電凸塊。
100,200,270,290,300,400,490,510,520,600,700,800,900:晶片封裝結構
110,280,280a:佈線基底
111:基底
111a,111b,178a:表面
112:貫穿基底導孔
113a,113b,114a,114b,284:佈線層
115a,115b,288:焊墊
115b1,118a1,118b1,122a,132,262:頂表面
116a,116b,286:導電導孔
117a,117b,118a,118b,282:絕緣層
122:含鎳層
124:含鈀層
126:含金層
130:導電保護層
134:彎曲的頂表面
140,450:載體基底
150:導電層
160,190:助焊劑材料層
170:晶片
172:半導體基底
172a:前表面
172b:後表面
174:介電層
176:導電墊
178:互連層
180,210,260,410,480:導電凸塊
220,420,460:助焊劑層
230,G:載體基底
240:底部填充層
250,440:模製層
260a:導電結構
289:彈性接觸結構
430,470:裝置
610,710,730:黏著層
620:散熱蓋
720:散熱環
740:散熱板
A:切割線
C:金屬間化合物層
D1,D2,D3,D4:距離
E:槽
F:除焊溶液
P1,P2:開口
R1:凹槽
T1,T2,T3,T3’,T4,T5:厚度
W1,W2,W3,W4:寬度
藉由以下的詳細描述配合所附圖式,可以更加理解本發明實施例的內容。需強調的是,根據產業上的標準慣例,許多部件並未按照比例繪製。事實上,為了能清楚地討論,各種部件的尺寸可能被任意地增加或減少。
第1A~1M圖是根據一些實施例之用於形成晶片封裝結構的製程的各個階段的剖面示意圖。
第2A~2B圖是根據一些實施例之用於形成晶片封裝結構的製程的各個階段的剖面示意圖。
第3圖是根據一些實施例之晶片封裝結構的剖面示意圖。
第4A~4H圖是根據一些實施例之用於形成晶片封裝結構的製程的各個階段的剖面示意圖。
第5A~5B圖是根據一些實施例之用於形成晶片封裝結構的製程的各個階段的剖面示意圖。
第6圖是根據一些實施例之晶片封裝結構的剖面示意圖。
第7圖是根據一些實施例之晶片封裝結構的剖面示意圖。
第8圖是根據一些實施例之晶片封裝結構的剖面示意圖。
第9圖是根據一些實施例之晶片封裝結構的剖面示意圖。
以下內容提供許多不同實施例或範例,用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用於限定本發明實施例。舉例來說,敘述中若提及第一部件形成於第二部件上或上方,可能包含形成第一部件和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一部件和第二部件之間,使得第一部件和第二部件不直接接觸的實施例。另外,本發明實施例在不同範例中可重複使用參考標號及/或字母。此重複是為了簡化和清楚之目的,並非代表所討論的不同實施例及/或組態之間有特定的關係。
此外,本文可能使用空間相對用語,例如「下方」、「之下」、「下」、「上方」、「上」及類似的用詞,這些空間相對用語係為了便於描述如圖所示之一個(些)元件或部件與另一個(些)元件或部件之間的關係。這些空間相對用語用於涵蓋使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),則在此所使用的空間相對形容詞也將依轉向後的方位來解釋。應理解的是,可以在方法之前、期間和之後提供額外的操作,並且對於方法的其他實施例,可以替換或消除所描述的一些操作。
描述本發明實施例中的一些實施例。可以在這些實施例中描述的階段之前、期間及/或之後提供額外的操作。對於不同的實施例,可以替換或消除所描述的一些階段。可以將額外的部件添加到半導體裝置結構中。對於不同的實施例,可以替換或消除以下描述的一些部件。雖然以採用特定順序進行的操作討論一些實施例,但可以採用其他邏輯順序來進行這些操作。
第1A~1M圖是根據一些實施例之用於形成晶片封裝結構的製程的各個階段的剖面示意圖。根據一些實施例,如第1A圖所示,提供佈線基底110。根據一些實施例,佈線基底110包含基底111、貫穿基底導孔(或鍍覆通孔(plated through holes,PTH))112、佈線層113a、113b、114a和114b、焊墊115a和115b、導電導孔116a和116b以及絕緣層117a、117b、118a和118b。
根據一些實施例,基底111具有表面111a和111b。根據一些實施例,表面111a與表面111b相對。在一些實施例中,基底111由絕緣材料製成,例如纖維材料、聚合物材料或玻璃材料。舉例來說,纖維材料包含玻璃纖維材料。
在一些其他實施例中,根據一些實施例,基底111由半導體材料或導電材料製成。舉例來說,半導體材料包含矽或鍺。舉例來說,導電材料包含金屬材料。
根據一些實施例,貫穿基底導孔112穿過基底111。根據一些實施例,分別在表面111a和111b上方形成佈線層113a和113b。根據一些實施例,貫穿基底導孔112將佈線層113a電連接到佈線層113b。
根據一些實施例,如果基底111由半導體材料或導電材料製成,則在基底111與貫穿基底導孔112之間以及基底111與佈線層113a和113b之間形成絕緣層(未繪示),使基底111與貫穿基底導孔112以及佈線層113a和113b電絕緣。
根據一些實施例,在表面111a上方形成佈線層114a、焊墊115a、導電導孔116a以及絕緣層117a和118a。根據一些實施例,佈線層114a和導電導孔116a在絕緣層117a中。根據一些實施例,焊墊115a在絕緣層117a上方。根據 一些實施例,導電導孔116a在佈線層113a和114a之間以及佈線層114a和焊墊115a之間電連接。
根據一些實施例,在絕緣層117a和焊墊115a上方形成絕緣層118a。根據一些實施例,絕緣層118a具有開口P1。根據一些實施例,多個開口P1分別暴露出其下方的多個焊墊115a。根據一些實施例,絕緣層118a部分地覆蓋焊墊115a。
根據一些實施例,在表面111b上方形成佈線層114b、焊墊115b、導電導孔116b以及絕緣層117b和118b。根據一些實施例,佈線層114b和導電導孔116b在絕緣層117b中。根據一些實施例,焊墊115b在絕緣層117b上方。根據一些實施例,導電導孔116b在佈線層113b和114b之間以及佈線層114b和焊墊115b之間電連接。
根據一些實施例,在絕緣層117b和焊墊115b上方形成絕緣層118b。根據一些實施例,絕緣層118b具有開口P2。根據一些實施例,多個開口P2分別暴露出多個焊墊115b。根據一些實施例,絕緣層118b部分地覆蓋焊墊115b。
在一些實施例中,焊墊115b比焊墊115a寬。亦即,根據一些實施例,焊墊115b的寬度W1大於焊墊115a的寬度W2。根據一些實施例,焊墊115b用於與佈線基底(例如印刷電路板)接合。根據一些實施例,焊墊115a用於與晶片接合。根據一些實施例,寬度W1在約200μm至約600μm的範圍。根據一些實施例,寬度W2在約20μm至約110μm的範圍。在一些實施例中,開口P2的(最大)寬度W3大於開口P1的(最大)寬度W4。
根據一些實施例,貫穿基底導孔112、佈線層113a、113b、114a 和114b、焊墊115a和115b以及導電導孔116a和116b由導電材料製成,例如金屬材料或其合金。金屬材料包含鋁、銅或鎢。
根據一些實施例,如第1B圖所示,在焊墊115b的頂表面115b1上方形成含鎳層122。根據一些實施例,含鎳層122覆蓋頂表面115b1的整個露出部分,此露出部分由開口P2暴露出來。根據一些實施例,含鎳層122在開口P2中。根據一些實施例,含鎳層122由鎳或其合金製成。根據一些實施例,含鎳層122的形成使用鍍覆製程,例如無電鍍(electroless plating)製程。
根據一些實施例,如第1B圖所示,在含鎳層122上方形成含鈀層124。根據一些實施例,含鈀層124在開口P2中。根據一些實施例,含鈀層124具有在約0.02μm至約0.1μm的範圍的厚度T1。根據一些實施例,含鈀層124由鈀或其合金製成。根據一些實施例,含鈀層124的形成使用鍍覆製程,例如無電鍍製程。
根據一些實施例,如第1B圖所示,在含鈀層124上方形成含金層126。根據一些實施例,含金層126在開口P2中。根據一些實施例,含金層126具有在約0.02μm至約0.1μm的範圍的厚度T2。根據一些實施例,含金層126由金或其合金製成。根據一些實施例,含金層126的形成使用鍍覆製程,例如浸鍍(immersion plating)製程。
根據一些實施例,如第1B圖所示,在含金層126上方形成導電保護層130。在一些實施例中,導電保護層130的孔隙率低於含鈀層124的孔隙率並且低於含金層126的孔隙率。亦即,根據一些實施例,導電保護層130具有比含鈀層124和含金層126更緻密的結構。
在一些實施例中,導電保護層130的厚度T3大於含鈀層124的厚 度T1和含金層126的厚度T2之和。在一些實施例中,導電保護層130比焊墊115b上方的絕緣層118b薄。
根據一些實施例,厚度T3在約1μm至約25μm的範圍。根據一些實施例,厚度T3在約1μm至約10μm的範圍。根據一些實施例,導電保護層130覆蓋含鎳層122的整個頂表面122a。
如果不形成導電保護層130,則含鎳層122中的鎳原子可能會受到後續除焊(deflux)製程中使用的除焊溶液的影響,並且可能會遷移穿過含鈀層124和含金層126並被氧化。由於導電保護層130比含鈀層124和含金層126更緻密且更厚,導電保護層130可以將含鎳層122與除焊溶液隔開。因此,導電保護層130可以改善焊墊115b和導電凸塊之間的黏著性,導電凸塊隨後形成並連接在焊墊115b和晶片之間。導電保護層130的形成可以增強導電凸塊。
由於導電保護層130可以對含鎳層122提供更強的保護,可以使用對於助焊劑(flux)層具有更強移除能力的除焊溶液來更澈底地移除助焊劑層。因此,可以提升助焊劑層的移除製程的產率。
在一些實施例中,絕緣層118b的頂表面118b1與焊墊115b的頂表面115b1之間的距離D1大於導電保護層130的頂表面132與焊墊115b的頂表面115b1之間的距離D2。亦即,根據一些實施例,頂表面132低於頂表面118b1。
根據一些實施例,導電保護層130、含金層126、含鈀層124和含鎳層122由不同的材料製成。根據一些實施例,導電保護層130由金屬材料(例如錫)或其合金(例如錫合金)製成。根據一些實施例,導電保護層130的形成使用印刷製程或無電鍍製程。
根據一些實施例,如第1C圖所示,在導電保護層130上進行回焊 製程。在回焊製程期間,將含金層126和含鈀層124溶解在導電保護層130中,並在導電保護層130和含鎳層122之間形成金屬間化合物層C。根據一些實施例,金屬間化合物層C可以改善導電保護層130和含鎳層122之間的黏著性。
根據一些實施例,金屬間化合物層C在結構上比導電保護層130、含金層126和含鈀層124更緻密。在一些實施例中,金屬間化合物層C的厚度T4大於含鈀層124的厚度T1和含金層126的厚度T2之和(如第1B圖所示)。因此,根據一些實施例,金屬間化合物層C為含鎳層122提供比含鈀層124和含金層126更強的保護。結果,金屬間化合物層C和導電保護層130可以在後續製程期間一起保護含鎳層122免於受到損壞。
根據一些實施例,金屬間化合物層C由導電保護層130和含鎳層122的材料製成。根據一些實施例,金屬間化合物層C包含化合物材料。舉例來說,化合物材料包含錫和鎳,例如Ni3Sn4
根據一些實施例,在回焊製程之後,導電保護層130具有(最大)厚度T3’。根據一些實施例,厚度T3’大於含鈀層124的厚度T1和含金層126的厚度T2之和(如第1B圖所示)。根據一些實施例,厚度T3’大於厚度T3(如第1B圖所示)。
根據一些實施例,厚度T3’在約1μm至約25μm的範圍。根據一些實施例,厚度T3’在約1μm至約10μm的範圍。在一些實施例中,(回焊的)導電保護層130比焊墊115b上方的絕緣層118b薄。
根據一些實施例,導電保護層130具有彎曲的頂表面134。在一些實施例中,絕緣層118b的頂表面118b1與焊墊115b的頂表面115b1之間的距離D1大於彎曲的頂表面134與頂表面115b1之間的(最大)距離D3。
在一些實施例中,焊墊115b上方的導電保護層130和絕緣層118b圍繞凹槽R1。根據一些實施例,在焊墊115b之一上方的整個導電保護層130在對應的開口P2中。亦即,根據一些實施例,導電保護層130沒有延伸超出相應的開口P2,這避免導電保護層130在隨後的製程中接觸載體基底。
用於避免導電保護層130在後續製程中接觸載體基底的設計包含導電保護層130比焊墊115b上方的絕緣層118b薄(如第1B圖所示)、頂表面132低於頂表面118b1(如第1B圖所示)、以及絕緣層118b的頂表面118b1與焊墊115b的頂表面115b1之間的距離D1大於彎曲的頂表面134和頂表面115b1之間的(最大)距離D3(如第1C圖所示)。在一些其他實施例中(未繪示),根據設計需求,彎曲的頂表面134(或頂表面132)高於頂表面118b1。
根據一些實施例,如第1D圖所示,將佈線基底110上下翻轉並設置在載體基底140上方。根據一些實施例,載體基底140被配置為在隨後的製程步驟期間提供暫時的機械和結構支撐。根據一些實施例,載體基底140包含玻璃、氧化矽、氧化鋁、金屬、前述之組合或類似的材料。根據一些實施例,載體基底140包含金屬框。
根據一些實施例,如第1D圖所示,在焊墊115a上方形成導電層150。根據一些實施例,導電層150包含焊球。根據一些實施例,導電層150由導電材料製成,例如金屬(例如錫)或其合金(例如錫合金)。根據一些實施例,導電層150的形成包含在焊墊115a上方形成焊接材料層(未繪示);以及使焊接材料層回焊以形成導電層150。
根據一些實施例,如第1E圖所示,在導電層150上方進行熱壓縮製程以使導電層150的頂表面152變平。根據一些實施例,如第1F圖所示,在導 電層150和絕緣層118a的頂表面118a1上方形成助焊劑材料層160。助焊劑材料層160用於在隨後的晶片接合製程中確保導電層150和晶片上方的導電凸塊之間的接合,藉此提升晶片接合製程的產率。
在一些實施例中,助焊劑材料層160包含酒石酸(tartaric acid)、樹脂、胺及/或溶劑。在一些實施例中,胺是烷基取代的胺(alkyl substituted amine)、乙醇胺(ethanol amine)、乙氧基化胺(ethoxylated amine)或丙氧基化胺(propoxylated amine)。在一些實施例中,使用界面活性劑,有時稱為調流劑(flow modifier)。具體的界面活性劑取決於與助焊劑材料層160的相容性。在一些實施例中,界面活性劑是陰離子的,例如長鏈烷基羧酸,例如月桂酸(lauric acids)、硬脂酸(stearic acids)或類似的材料。根據一些實施例,使用浸漬(dipping)製程或噴塗(jetting)製程形成助焊劑材料層160。
根據一些實施例,如第1G圖所示,提供晶片170。根據一些實施例,晶片170包含半導體基底172、介電層174、導電墊176和互連層178。
根據一些實施例,半導體基底172具有前表面172a和與前表面172a相對的後表面172b。在一些實施例中,在前表面172a上方或鄰近前表面172a的半導體基底172中形成主動元件(例如電晶體、二極體或類似的元件)及/或被動元件(例如電阻器、電容器、電感器或類似的元件)。
在一些實施例中,半導體基底172至少由元素半導體材料製成,包含單晶、多晶或非晶結構的矽或鍺。在一些其他實施例中,半導體基底172由化合物半導體(例如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦)、合金半導體(例如SiGe或GaAsP)或前述之組合製成。半導體基底172還可以包含多層 半導體、絕緣體上覆半導體(semiconductor on insulator,SOI)(例如絕緣體上覆矽或絕緣體上覆鍺)或前述之組合。
根據一些實施例,介電層174形成在前表面172a上方。介電層174由聚合物材料製成,例如聚苯並
Figure 109128579-A0305-02-0014-1
唑(polybenzoxazole,PBO)層、聚醯亞胺(polyimide)層、苯環丁烯(benzocyclobutene,BCB)層、環氧樹脂(epoxy)層、感光材料層或其他合適的材料。
根據一些實施例,導電墊176形成在介電層174中。根據一些實施例,導電墊176電連接到在半導體基底172中/上方形成的裝置(未繪示)。根據一些實施例,導電墊176由導電材料製成,例如銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)或鉭合金。
根據一些實施例,互連層178形成在介電層174上方。根據一些實施例,互連層178包含介電層(未繪示)和在介電層中的導電互連結構(未繪示)。
根據一些實施例,如第1G圖所示,在互連層178上方形成導電凸塊180。根據一些實施例,互連層178的導電互連結構電連接到導電凸塊180和導電墊176。
根據一些實施例,導電凸塊180由導電材料製成,例如錫(Sn)或其合金。在一些其他實施例中,導電凸塊180由銅(Cu)、銅合金、鋁(Al)、鋁合金、鎢(W)、鎢合金、鈦(Ti)、鈦合金、鉭(Ta)或鉭合金製成。
根據一些實施例,如第1G圖所示,在導電凸塊180和互連層178 的表面178a上方形成助焊劑材料層190。助焊劑材料層190用於在隨後的晶片接合製程中確保導電凸塊180與導電層150之間的接合(如第1F圖所示),藉此提升晶片接合製程的產率。
在一些實施例中,助焊劑材料層190包含酒石酸、樹脂、胺及/或溶劑。在一些實施例中,胺是烷基取代的胺、乙醇胺、乙氧基化胺或丙氧基化胺。在一些實施例中,使用界面活性劑,有時稱為調流劑。具體的界面活性劑取決於與助焊劑材料層190的相容性。在一些實施例中,界面活性劑是陰離子的,例如長鏈烷基羧酸,例如月桂酸、硬脂酸或類似的材料。根據一些實施例,使用浸漬製程或噴塗製程來形成助焊劑材料層190。
根據一些實施例,如第1H圖所示,晶片170經由導電凸塊210和助焊劑層220接合至佈線基底110。根據一些實施例,助焊劑層220圍繞導電凸塊210。
根據一些實施例,導電凸塊210在焊墊115a和晶片170之間並連接焊墊115a和晶片170。根據一些實施例,導電凸塊210由導電層150和導電凸塊180形成。根據一些實施例,助焊劑層220由助焊劑材料層160和190形成。
根據一些實施例,導電保護層130比導電凸塊210薄。亦即,根據一些實施例,導電保護層130的(最大)厚度T3’小於導電凸塊210的厚度T5。
根據一些實施例,如第1I圖所示,移除助焊劑層220。根據一些實施例,助焊劑層220的移除製程包含浸漬製程或噴塗製程。舉例來說,根據一些實施例,在浸漬製程中,將佈線基底110浸入容納在槽E中的除焊溶液F中。根據一些實施例,助焊劑層220可以溶解在除焊溶液F中。
根據一些實施例,導電保護層130和金屬間化合物層C將含鎳層122與除焊溶液F隔開。根據一些實施例,導電保護層130直接接觸除焊溶液F。
根據一些實施例,除焊溶液F包含水性液體(例如去離子水)和溶劑,例如氫氟碳化物(hydrofluorocarbons,HFC’s)、氫氟氯碳化物(hydrochlorofluorocarbons,HCFC’s)、氟氯碳化物(chlorofluorocarbons)、醇、萜烯(terpenes)及前述之組合。
根據一些實施例,如第1J圖所示,佈線基底110設置在載體基底230上方。根據一些實施例,載體基底230被配置為在隨後的製程步驟期間提供暫時的機械和結構支撐。根據一些實施例,載體基底230包含玻璃、氧化矽、氧化鋁、金屬、前述之組合等。根據一些實施例,載體基底230包含金屬框。
根據一些實施例,如第1J圖所示,在晶片170和佈線基底110之間形成底部填充層240。根據一些實施例,底部填充層240包含絕緣材料,例如聚合物材料。
根據一些實施例,如第1J圖所示,在佈線基底110、晶片170和底部填充層240上方形成模製(molding)層250。根據一些實施例,模製層250封裝晶片170。根據一些實施例,模製層250圍繞晶片170、導電凸塊210和底部填充層240。根據一些實施例,模製層250由絕緣材料製成,例如聚合物材料。
根據一些實施例,如第1K圖所示,將佈線基底110上下翻轉並設置在載體基底G上方。根據一些實施例,載體基底G被配置為在隨後的製程步驟期間提供暫時的機械和結構支撐。根據一些實施例,載體基底G包含玻璃、氧化矽、氧化鋁、金屬、前述之組合或類似的材料。根據一些實施例,載體基底G包含金屬框。
根據一些實施例,如第1K圖所示,在導電保護層130上方形成導電結構260a。根據一些實施例,導電結構260a由導電材料製成,例如金屬(例如Sn)或前述之合金。在一些實施例中,導電結構260a和導電保護層130由相同的導電材料製成,例如錫或錫合金。
根據一些實施例,如第1K圖和第1L圖所示,對導電結構260a和導電保護層130進行回焊製程,以將導電結構260a和導電保護層130熔融並混合在一起,以形成導電凸塊260。
在一些實施例中,導電凸塊260的頂表面262與焊墊115b的頂表面115b1之間的距離D4大於絕緣層118b的頂表面118b1與頂表面115b1之間的距離D1。根據一些實施例,導電凸塊260比導電凸塊210更寬且更厚。因此,根據一些實施例,在後續製程中,導電凸塊260能夠與具有比晶片170的焊墊更大的焊墊的佈線基底接合。
根據一些實施例,如第1L圖所示,在佈線基底110上方沿著切割線A進行切割製程,以切割穿過佈線基底110和模製層250以形成晶片封裝結構270。
根據一些實施例,如第1M圖所示,晶片封裝結構270經由導電凸塊260接合至佈線基底280。佈線基底280包含印刷電路板或其他合適的佈線基底。根據一些實施例,佈線基底280包含絕緣層282、佈線層284、導電導孔286和焊墊288。
根據一些實施例,佈線層284和導電導孔286在絕緣層282中。根據一些實施例,焊墊288在絕緣層282上方。根據一些實施例,導電導孔286在佈線層284之間以及在佈線層284和焊墊288之間電連接。
根據一些實施例,佈線層284、導電導孔286和焊墊288由導電材料製成,例如金屬材料或前述之合金。金屬材料包含鋁、銅或鎢。
根據一些實施例,在此步驟中,大致形成了晶片封裝結構(或板級(board-level)封裝結構)100。根據一些實施例,晶片封裝結構100包含晶片封裝結構270、導電凸塊260和佈線基底280。根據一些實施例,晶片封裝結構100是球柵陣列(ball grid array,BGA)封裝結構。
第2A圖至第2B圖是根據一些實施例之用於形成晶片封裝結構的製程的各個階段的剖面示意圖。根據一些實施例,如第2A圖所示,在第1J圖的步驟之後,在佈線基底110上方沿著切割線A進行切割製程,以切割穿過佈線基底110和模製層250以形成晶片封裝結構290。
根據一些實施例,如第2B圖所示,提供佈線基底280a。根據一些實施例,佈線基底280a類似於第1M圖的佈線基底280,除了佈線基底280a還包含彈性接觸結構289。根據一些實施例,彈性接觸結構289被安裝到焊墊288。
根據一些實施例,如第2B圖所示,晶片封裝結構290經由導電保護層130和彈性接觸結構289接合至佈線基底280a。根據一些實施例,彈性接觸結構289直接接觸導電保護層130。根據一些實施例,彈性接觸結構289是彈性金屬條。
根據一些實施例,在此步驟中,大致形成了晶片封裝結構(或板級封裝結構)200。根據一些實施例,晶片封裝結構200包含晶片封裝結構290和佈線基底280a。根據一些實施例,晶片封裝結構200是平面網格陣列(land grid array,LGA)封裝結構。
第3圖是根據一些實施例之晶片封裝結構(或板級封裝結構)300的剖面示意圖。根據一些實施例,如第3圖所示,晶片封裝結構300類似於第2B圖的晶片封裝結構200,除了晶片封裝結構300的彈性接觸結構289穿入導電保護層130。導電保護層130可以將彈性接觸結構289固定到焊墊115b,以提升晶片封裝結構300的產率。根據一些實施例,晶片封裝結構300是平面網格陣列(LGA)封裝結構。
第4A~4H圖是根據一些實施例之用於形成晶片封裝結構的製程的各個階段的剖面示意圖。根據一些實施例,如第4A圖所示,在第1I圖的步驟之後,將佈線基底110設置在載體基底230上方。根據一些實施例,如第4A圖所示,導電層150的一部分未接合至晶片170。
根據一些實施例,如第4A圖所示,在晶片170和佈線基底110之間形成底部填充層240。根據一些實施例,如第4A圖所示,在導電層150的一部分和絕緣層118a的頂表面118a1上方形成助焊劑層420。
在一些實施例中,助焊劑層420包含酒石酸、樹脂、胺及/或溶劑。在一些實施例中,胺是烷基取代的胺、乙醇胺、乙氧基化胺或丙氧基化胺。在一些實施例中,使用界面活性劑,有時稱為調流劑。具體的界面活性劑取決於與助焊劑層420的相容性。在一些實施例中,界面活性劑是陰離子的,例如長鏈烷基羧酸,例如月桂酸、硬脂酸或類似的材料。根據一些實施例,使用浸漬製程或噴塗製程來形成助焊劑層420。
根據一些實施例,如第4B圖所示,裝置430經由導電凸塊410接合至佈線基底110。根據一些實施例,導電凸塊410由導電層150的一部分部分地形成。根據一些實施例,裝置430包含主動裝置或例如電阻器、電容器或電 感器的被動裝置。
根據一些實施例,如第4C圖所示,使用除焊製程移除助焊劑層420。根據一些實施例,如第4C圖所示,在佈線基底110、晶片170、底部填充層240、裝置430和導電凸塊410上方形成模製層440。根據一些實施例,模製層440封裝晶片170和裝置430。
根據一些實施例,模製層440圍繞晶片170、導電凸塊210、底部填充層240、裝置430和導電凸塊410。根據一些實施例,模製層440由絕緣材料製成,例如聚合物材料。
根據一些實施例,如第4D圖所示,將佈線基底110上下翻轉並設置在載體基底450上方。根據一些實施例,載體基底450被配置為在隨後的製程步驟期間提供暫時的機械和結構支撐。根據一些實施例,載體基底450包含玻璃、氧化矽、氧化鋁、金屬、前述之組合或類似的材料。根據一些實施例,載體基底450包含金屬框。
根據一些實施例,如第4D圖所示,在導電保護層130的一部分上方形成助焊劑層460。在一些實施例中,助焊劑層460包含酒石酸、樹脂、胺及/或溶劑。在一些實施例中,胺是烷基取代的胺、乙醇胺、乙氧基化胺或丙氧基化胺。
在一些實施例中,使用界面活性劑,有時稱為調流劑。具體的界面活性劑取決於與助焊劑層460的相容性。在一些實施例中,界面活性劑是陰離子的,例如長鏈烷基羧酸,例如月桂酸、硬脂酸或類似的材料。根據一些實施例,使用浸漬製程或噴塗製程來形成助焊劑層460。
根據一些實施例,如第4E圖所示,裝置470經由導電凸塊480接 合至佈線基底110。根據一些實施例,導電凸塊480由導電保護層130的一部分部分地形成。根據一些實施例,裝置470包含主動裝置或例如電阻器、電容器或電感器的被動裝置。
根據一些實施例,如第4F圖所示,使用除焊製程移除助焊劑層460。根據一些實施例,如第4G圖所示,進行第1K~1L圖的步驟以形成導電凸塊260並形成晶片封裝結構(或板級封裝結構)400。根據一些實施例,如第4H圖所示,進行第1M圖的步驟以經由導電凸塊260將晶片封裝結構400接合至佈線基底280。
根據一些實施例,在此步驟中,大致形成了晶片封裝結構490。根據一些實施例,晶片封裝結構490包含晶片封裝結構400、導電凸塊260和佈線基底280。根據一些實施例,晶片封裝結構490是球柵陣列(BGA)封裝結構。
第5A~5B圖是根據一些實施例之用於形成晶片封裝結構的製程的各個階段的剖面示意圖。根據一些實施例,如第5A圖所示,在第4F圖的步驟之後,在佈線基底110上方沿著切割線A進行切割製程,以切割穿過佈線基底110和模製層440以形成晶片封裝結構510。
根據一些實施例,如第5B圖所示,晶片封裝結構510經由導電保護層130和彈性接觸結構289接合至佈線基底280a。根據一些實施例,彈性接觸結構289直接接觸導電保護層130。根據一些實施例,彈性接觸結構289是彈性金屬條。根據一些實施例,彈性接觸結構289穿入導電保護層130。
根據一些實施例,在步驟中,大致形成了晶片封裝結構(或板級封裝結構)520。根據一些實施例,晶片封裝結構520包含晶片封裝結構510 和佈線基底280a。根據一些實施例,晶片封裝結構520是平面網格陣列(LGA)封裝結構。
第6圖是根據一些實施例之晶片封裝結構600的剖面示意圖。根據一些實施例,如第6圖所示,晶片封裝結構600類似於第1M圖的晶片封裝結構100,除了晶片封裝結構600還具有黏著層610和散熱蓋620。根據一些實施例,晶片封裝結構600沒有晶片封裝結構100的模製層250。
根據一些實施例,黏著層610形成在佈線基底110上方。根據一些實施例,黏著層610圍繞晶片170和底部填充層240。根據一些實施例,黏著層610具有環形形狀。根據一些實施例,散熱蓋620設置在晶片170和黏著層610上方。
根據一些實施例,黏著層610由聚合物製成,例如環氧樹脂或聚矽氧(silicone)。根據一些實施例,使用分配(dispensing)製程來形成黏著層610。根據一些實施例,散熱蓋620由高導熱率的材料製成,例如金屬材料(鋁或銅)、合金材料(例如不銹鋼)或鋁碳化矽(AlSiC)。
第7圖是根據一些實施例之晶片封裝結構700的剖面示意圖。根據一些實施例,如第7圖所示,晶片封裝結構700類似於第1M圖的晶片封裝結構100,除了晶片封裝結構700還具有黏著層710、散熱環720、黏著層730和散熱板740。根據一些實施例,晶片封裝結構700沒有晶片封裝結構100的模製層250。
根據一些實施例,黏著層710形成在佈線基底110上方。根據一些實施例,黏著層710圍繞晶片170和底部填充層240。根據一些實施例,黏著層710具有環形形狀。根據一些實施例,散熱環720設置在黏著層710上。
根據一些實施例,黏著層730形成在散熱環720上。根據一些實施例,黏著層730具有環形形狀。根據一些實施例,散熱板740設置在黏著層730和晶片170上方。
根據一些實施例,黏著層710和730由聚合物製成,例如環氧樹脂或聚矽氧。根據一些實施例,使用分配製程來形成黏著層710和730。
根據一些實施例,散熱環720和散熱板740由高導熱率的材料製成,例如金屬材料(鋁或銅)、合金材料(例如不銹鋼)或鋁碳化矽(AlSiC)。
第8圖是根據一些實施例之晶片封裝結構800的剖面示意圖。根據一些實施例,如第8圖所示,晶片封裝結構800類似於第3圖的晶片封裝結構300,除了晶片封裝結構800還具有黏著層610和散熱蓋620。
根據一些實施例,晶片封裝結構800沒有晶片封裝結構300的模製層250。根據一些實施例,彈性接觸結構289穿過導電保護層130。根據一些實施例,彈性接觸結構289直接接觸金屬間化合物層C。
根據一些實施例,黏著層610形成在佈線基底110上方。根據一些實施例,黏著層610圍繞晶片170和底部填充層240。根據一些實施例,黏著層610具有環形形狀。根據一些實施例,散熱蓋620設置在晶片170和黏著層610上方。
根據一些實施例,黏著層610由聚合物製成,例如環氧樹脂或聚矽氧。根據一些實施例,使用分配製程來形成黏著層610。根據一些實施例,散熱蓋620由高導熱率的材料製成,例如金屬材料(鋁或銅)、合金材料(例如不銹鋼)或鋁碳化矽(AlSiC)。
第9圖是根據一些實施例之晶片封裝結構900的剖面示意圖。根據一些實施例,如第9圖所示,晶片封裝結構900類似於第3圖的晶片封裝結構300,除了晶片封裝結構900還具有黏著層710、散熱環720、黏著層730和散熱板740。根據一些實施例,晶片封裝結構900沒有晶片封裝結構300的模製層250。
根據一些實施例,黏著層710形成在佈線基底110上方。根據一些實施例,黏著層710圍繞晶片170和底部填充層240。根據一些實施例,黏著層710具有環形形狀。根據一些實施例,散熱環720設置在黏著層710上方。
根據一些實施例,黏著層730形成在散熱環720上方。根據一些實施例,黏著層730具有環形形狀。根據一些實施例,散熱板740設置在黏著層730和晶片170上方。
根據一些實施例,黏著層710和730由聚合物製成,例如環氧樹脂或聚矽氧。根據一些實施例,使用分配製程來形成黏著層710和730。
根據一些實施例,散熱環720和散熱板740由高導熱率的材料製成,例如金屬材料(鋁或銅)、合金材料(例如不銹鋼)或鋁碳化矽(AlSiC)。
用於形成晶片封裝結構200、300、490、520、600、700、800和900的製程和材料可以與前述用於形成晶片封裝結構100的那些製程相似或相同。
根據一些實施例,提供晶片封裝結構及其形成方法。(用於形成晶片封裝結構的)方法在回焊製程之前在焊墊上方的含鎳層上方形成導電保護層,以保護含鎳層在回焊製程期間不被氧化。因此,改善焊墊與隨後在焊墊 與晶片之間形成的導電凸塊之間的黏著性。結果,提升晶片封裝結構的產率。
根據一些實施例,提供晶片封裝結構的形成方法。此方法包含提供佈線基底。佈線基底包含基底、第一焊墊、第二焊墊和絕緣層。第一焊墊和第二焊墊分別在基底的第一表面和第二表面上方。絕緣層在第一表面上方並部分地覆蓋第一焊墊,並且第一焊墊比第二焊墊寬。此方法包含在第一焊墊上方依序形成含鎳層和含金層。此方法包含形成導電保護層覆蓋含鎳層上方的含金層。導電保護層、含金層和含鎳層由不同的材料製成,並且絕緣層的第一頂表面與第一焊墊的第二頂表面之間的第一距離大於導電保護層的第三頂表面與第一焊墊的第二頂表面之間的第二距離。此方法包含經由導電凸塊和圍繞導電凸塊的助焊劑層將晶片接合至佈線基底。導電凸塊在第二焊墊和晶片之間。此方法包含在導電保護層覆蓋含鎳層的同時移除助焊劑層。
在一些實施例中,此方法更包含:在將晶片接合至佈線基底之前,回焊導電保護層,其中含金層溶解在導電保護層中,並且在導電保護層和含鎳層之間形成金屬間化合物層。
在一些實施例中,在回焊導電保護層之後,導電保護層具有彎曲的頂表面。
在一些實施例中,導電保護層覆蓋含鎳層的第四頂表面整個。
在一些實施例中,此方法更包含:在形成含金層於第一焊墊上方之前,在含鎳層上方形成含鈀層,其中含金層形成在含鈀層上方。
在一些實施例中,絕緣層具有開口暴露出第一焊墊的一部分,含鎳層、含鈀層和含金層在開口中且覆蓋所述部分,並且導電保護層整個在開口中。
在一些實施例中,此方法更包含:在將晶片接合至佈線基底之前,在第二焊墊上方形成導電層,其中第一導電凸塊的一部分由導電層形成。
在一些實施例中,佈線基底更包含在第一表面上方的第三焊墊,含鎳層、含金層和導電保護層更形成在第三焊墊上方,此方法更包含:在移除第一助焊劑層之後,經由第二導電凸塊和圍繞第二導電凸塊的第二助焊劑層將裝置接合至第三焊墊,其中第二導電凸塊由第三焊墊上方的導電保護層部分地形成;以及移除第二助焊劑層。
在一些實施例中,第一助焊劑層的移除包含使用除焊溶液以移除第一助焊劑層,並且導電保護層將含鎳層與除焊溶液隔開。
在一些實施例中,導電保護層比含金層緻密。
根據一些實施例,提供用於形成晶片封裝結構的方法。此方法包含提供佈線基底。佈線基底包含基底、第一焊墊、第二焊墊和絕緣層,第一焊墊和第二焊墊分別在基底的第一表面和第二表面上方,並且絕緣層在第一表面和第一焊墊上方且具有開口,開口部分地暴露出第一焊墊。此方法包含在開口中依序形成含鎳層和含金層。此方法包含在含金層上方形成導電保護層,其中導電保護層的第一孔隙率小於含金層的第二孔隙率,並且導電保護層比第一焊墊上方的絕緣層薄。此方法包含在導電保護層形成於含金層上方之後,經由第一導電凸塊將晶片接合至佈線基底的第二焊墊。此方法包含在將晶片接合至第二焊墊之後,在導電保護層上方形成導電結構。此方法包含使導電結構和導電保護層回焊,以將導電結構和導電保護層熔融並混合在一起,藉此形成第二導電凸塊。
在一些實施例中,導電保護層比第一焊墊上方的絕緣層薄。
在一些實施例中,導電結構和導電保護層由相同材料製成。
在一些實施例中,導電保護層比含金層厚。
在一些實施例中,第一焊墊比第二焊墊寬,並且第二導電凸塊比第一導電凸塊更寬且更厚。
根據一些實施例,提供晶片封裝結構。此晶片封裝結構包含第一佈線基底,第一佈線基底包含基底、第一焊墊、第二焊墊和絕緣層,第一焊墊和第二焊墊分別位於基底的第一表面和第二表面上方,絕緣層在第一表面上方且部分地覆蓋第一焊墊,並且第一焊墊比第二焊墊寬。此晶片封裝結構包含在第一焊墊上方的含鎳層。此晶片封裝結構包含在含鎳層上方的導電保護層。導電保護層包含錫,並且第一焊墊上方的導電保護層和絕緣層圍繞凹槽。此晶片封裝結構包含在基底的第二表面上方的晶片。此晶片封裝結構包含在第二焊墊和晶片之間的導電凸塊。
在一些實施例中,此晶片封裝結構更包含:第二佈線基底,其中第一佈線基底在第二佈線基底上方,第二佈線基底包含第二基底和安裝到第二基底的彈性接觸結構,並且彈性接觸結構直接接觸導電保護層。
在一些實施例中,彈性接觸結構是彈性金屬條。
在一些實施例中,彈性接觸結構穿入導電保護層。
在一些實施例中,此晶片封裝結構更包含:在導電保護層和含鎳層之間的金屬間化合物層,其中金屬化合物層包含錫和鎳。
以上概述數個實施例之部件,使得本技術領域中具有通常知識者可以更加理解本發明實施例的面向。本技術領域中具有通常知識者應該理解,他們能以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在 此介紹的實施例相同之目的及/或優點。本技術領域中具有通常知識者也應該理解到,此類等效的結構並未悖離本發明實施例的精神與範圍,且他們能在不違背本發明實施例的精神和範圍下,做各式各樣的改變、取代和調整。
100,270:晶片封裝結構
110,280:佈線基底
122:含鎳層
170:晶片
210,260:導電凸塊
240:底部填充層
250:模製層
282:絕緣層
284:佈線層
286:導電導孔
288:焊墊
C:金屬間化合物層

Claims (10)

  1. 一種晶片封裝結構的形成方法,包含:提供一佈線基底,包括一基底、一第一焊墊、一第二焊墊和一絕緣層,其中該第一焊墊和該第二焊墊分別在該基底的一第一表面和一第二表面上方,該絕緣層在該第一表面上方並部分地覆蓋該第一焊墊,並且該第一焊墊比該第二焊墊寬;在該第一焊墊上方依序形成一含鎳層和一含金層;形成一導電保護層覆蓋該含鎳層上方的該含金層,其中該導電保護層、該含金層和該含鎳層由不同的材料製成,並且該絕緣層的一第一頂表面與該第一焊墊的一第二頂表面之間的一第一距離大於該導電保護層的一第三頂表面與該第二頂表面之間的一第二距離;經由一第一導電凸塊和圍繞該第一導電凸塊的一第一助焊劑層將一晶片接合至該佈線基底,其中該第一導電凸塊在該第二焊墊和該晶片之間並連接該第二焊墊和該晶片;以及在該導電保護層覆蓋該含鎳層的同時,移除該第一助焊劑層。
  2. 如請求項1之晶片封裝結構的形成方法,更包括:在將該晶片接合至該佈線基底之前,回焊該導電保護層,其中該含金層溶解在該導電保護層中,並且在該導電保護層和該含鎳層之間形成一金屬間化合物層。
  3. 如請求項1或2之晶片封裝結構的形成方法,更包括:在形成該含金層於該第一焊墊上方之前,在該含鎳層上方形成一含鈀層,其中該含金層形成在該含鈀層上方。
  4. 如請求項1或2之晶片封裝結構的形成方法,其中該佈線基底更包括在該第一表面上方的一第三焊墊,該含鎳層、該含金層和該導電保護層更形成在該第三焊墊上方,該方法更包括:在移除該第一助焊劑層之後,經由一第二導電凸塊和圍繞該第二導電凸塊的一第二助焊劑層將一裝置接合至該第三焊墊,其中該第二導電凸塊由該第三焊墊上方的該導電保護層部分地形成;以及移除該第二助焊劑層。
  5. 如請求項1或2之晶片封裝結構的形成方法,其中該第一助焊劑層的移除包括使用一除焊溶液以移除該第一助焊劑層,並且該導電保護層將該含鎳層與該除焊溶液隔開。
  6. 一種晶片封裝結構的形成方法,包含:提供一佈線基底,包括一基底、一第一焊墊、一第二焊墊和一絕緣層,其中該第一焊墊和該第二焊墊分別在該基底的一第一表面和一第二表面上方,並且該絕緣層在該第一表面和該第一焊墊上方且具有一開口部分地暴露出該第一焊墊;在該開口中依序形成一含鎳層和一含金層;在該含金層上方形成一導電保護層,其中該導電保護層的一第一孔隙率小於該含金層的一第二孔隙率;在該導電保護層形成於該含金層上方之後,經由一第一導電凸塊將一晶片接合至該佈線基底的該第二焊墊;在將該晶片接合至該第二焊墊之後,在該導電保護層上方形成一導電結構;以及 使該導電結構和該導電保護層回焊,以將該導電結構和該導電保護層熔融並混合在一起,藉此形成一第二導電凸塊。
  7. 如請求項6之晶片封裝結構的形成方法,其中該導電保護層比該第一焊墊上方的該絕緣層薄;及/或該導電保護層比該含金層厚。
  8. 一種晶片封裝結構,包括:一第一佈線基底,包括一基底、一第一焊墊、一第二焊墊和一絕緣層,該第一焊墊和該第二焊墊分別位於該基底的一第一表面和一第二表面上方,該絕緣層在該第一表面上方且部分地覆蓋該第一焊墊,並且該第一焊墊比該第二焊墊寬;一含鎳層,在該第一焊墊上方;一導電保護層,在該含鎳層上方,其中該導電保護層包括錫,並且該第一焊墊上方的該導電保護層和該絕緣層圍繞一凹槽,其中該導電保護層的頂表面低於該絕緣層的頂表面;一晶片,在該基底的該第二表面上方;以及一導電凸塊,在該第二焊墊和該晶片之間。
  9. 如請求項8之晶片封裝結構,更包括:一第二佈線基底,其中該第一佈線基底在該第二佈線基底上方,該第二佈線基底包括一第二基底和安裝到該第二基底的一彈性接觸結構,並且該彈性接觸結構直接接觸該導電保護層。
  10. 如請求項9之晶片封裝結構,其中該彈性接觸結構穿入該導電保護層。
TW109128579A 2019-08-30 2020-08-21 晶片封裝結構及其形成方法 TWI743956B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201962893874P 2019-08-30 2019-08-30
US62/893,874 2019-08-30
US16/893,467 US11335634B2 (en) 2019-08-30 2020-06-05 Chip package structure and method for forming the same
US16/893,467 2020-06-05

Publications (2)

Publication Number Publication Date
TW202109806A TW202109806A (zh) 2021-03-01
TWI743956B true TWI743956B (zh) 2021-10-21

Family

ID=74565008

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109128579A TWI743956B (zh) 2019-08-30 2020-08-21 晶片封裝結構及其形成方法

Country Status (3)

Country Link
US (3) US11335634B2 (zh)
DE (1) DE102020117561A1 (zh)
TW (1) TWI743956B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170005035A1 (en) * 2015-06-30 2017-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked Semiconductor Devices and Methods of Forming Same
TW201717343A (zh) * 2015-11-04 2017-05-16 華亞科技股份有限公司 封裝上封裝構件及其製作方法
TW201919179A (zh) * 2017-11-01 2019-05-16 南韓商三星電機股份有限公司 半導體封裝與連接構件

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6740577B2 (en) * 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
US9460951B2 (en) * 2007-12-03 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer level package integration
US10475759B2 (en) * 2011-10-11 2019-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure having dies with connectors of different sizes
US9153550B2 (en) * 2013-11-14 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design with balanced metal and solder resist density

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170005035A1 (en) * 2015-06-30 2017-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked Semiconductor Devices and Methods of Forming Same
TW201717343A (zh) * 2015-11-04 2017-05-16 華亞科技股份有限公司 封裝上封裝構件及其製作方法
TW201919179A (zh) * 2017-11-01 2019-05-16 南韓商三星電機股份有限公司 半導體封裝與連接構件

Also Published As

Publication number Publication date
US11335634B2 (en) 2022-05-17
US20220270963A1 (en) 2022-08-25
US20240312900A1 (en) 2024-09-19
TW202109806A (zh) 2021-03-01
DE102020117561A1 (de) 2021-03-04
US12002746B2 (en) 2024-06-04
US20210066181A1 (en) 2021-03-04

Similar Documents

Publication Publication Date Title
US7060601B2 (en) Packaging substrates for integrated circuits and soldering methods
TWI656581B (zh) 使用具有微柱的半導體晶粒來形成直接晶片接合平面柵格陣列封裝之半導體裝置及方法
US9589938B2 (en) Semiconductor device including an embedded surface mount device and method of forming the same
US7241675B2 (en) Attachment of integrated circuit structures and other substrates to substrates with vias
US20220384377A1 (en) Semiconductor structure and method of manufacturing the same
US9431325B2 (en) Semiconductor packaging structure
TWI821644B (zh) 晶片封裝結構及其形成方法
TW201733419A (zh) 電子零件之製造方法及電子零件之製造裝置
KR102210802B1 (ko) 반도체 장치 및 그 제조 방법
CN112447530A (zh) 芯片封装结构及其形成方法
TWI743956B (zh) 晶片封裝結構及其形成方法
KR101758999B1 (ko) 반도체 디바이스 및 그 제조 방법
TW202306069A (zh) 電子封裝件及其製法