CN106653848B - 半导体器件结构的结构和形成方法 - Google Patents

半导体器件结构的结构和形成方法 Download PDF

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CN106653848B
CN106653848B CN201610749911.3A CN201610749911A CN106653848B CN 106653848 B CN106653848 B CN 106653848B CN 201610749911 A CN201610749911 A CN 201610749911A CN 106653848 B CN106653848 B CN 106653848B
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semiconductor device
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dielectric
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CN106653848A (zh
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张哲诚
林志翰
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明的实施例提供了半导体器件结构的结构和形成方法。半导体器件结构包括位于半导体衬底上方的鳍结构和覆盖鳍结构的一部分的栅极堆叠件。栅极堆叠件包括栅极介电层、功函数层和位于功函数层上方的导电填料。半导体器件结构还包括覆盖鳍结构的介电层。介电层与导电填料直接接触。

Description

半导体器件结构的结构和形成方法
技术领域
本发明涉及半导体领域，更具体地涉及半导体器件结构的结构和形成方法。
背景技术
半导体集成电路(IC)工业已经经历了快速发展。在IC材料和设计中的技术进步已经产生了数代IC。每一代都比上一代具有更小和更复杂的电路。
在IC演进过程中，功能密度(即，每芯片面积中的互连器件的数量) 通常都在增加，同时几何尺寸(即，可使用制造工艺创建的最小组件(或线))减小。这种规模缩小工艺通常通过增加产量效率和降低相关成本来提供益处。
然而，这些进步已经增大了处理和制造IC的复杂度。由于部件尺寸的不断减小，制造工艺继续变得更加难以实施。因此，形成尺寸越来越小的可靠的半导体器件是个挑战。
发明内容
本发明的实施例提供了一种半导体器件结构，包括：鳍结构，位于半导体衬底上方；栅极堆叠件，覆盖所述鳍结构的一部分，其中，所述栅极堆叠件包括栅极介电层、功函数层和位于所述功函数层上方的导电填料；以及介电层，覆盖所述鳍结构，其中，所述介电层与所述导电填料直接接触。
本发明的实施例还提供了一种半导体器件结构，包括：鳍结构，位于半导体衬底上方；栅极堆叠件，覆盖所述鳍结构的一部分，其中，所述栅极堆叠件包括栅极介电层、功函数层和位于所述功函数层上方的导电填料；以及介电层，覆盖所述鳍结构并且围绕所述栅极堆叠件，其中，所述介电层与所述功函数层之间的最短距离大于所述介电层与所述导电填料之间的最短距离。
本发明的实施例还提供了一种用于形成半导体器件结构的方法，包括：在半导体衬底上方形成伪栅极堆叠件；形成介电层以围绕所述伪栅极堆叠件；去除所述伪栅极堆叠件以形成由所述介电层围绕的凹槽；在所述凹槽的侧壁和底部上方形成栅极介电层和功函数层；去除所述功函数层的位于所述介电层的侧壁上的部分；在去除所述功函数层的位于所述介电层的侧壁上的部分之后，形成导电填料以填充所述凹槽。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1A至图1D是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的透视图。
图2A至图2F是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的截面图。
图3是根据一些实施例的半导体器件结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成附加的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…下方”、“在…下”、“下部”、“在…上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
描述了本发明的一些实施例。图1A至图1D是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的透视图。图2A至图2F是根据一些实施例的用于形成半导体器件结构的工艺的各个阶段的截面图。在一些实施例中，图2A至图2F的一些截面图对应于图1A至图1D中沿线I-I截取的截面图。在图1A至图1D或图2A至图2F中所描述的阶段之前、期间和/或之后可以提供附加的操作。对于不同的实施例，可以替代或消除所述的一些阶段。附加的部件可以添加至半导体器件结构。对于不同的实施例，可以替代或消除以下所描述的一些部件。
如图1A和2A所示，根据一些实施例，包括鳍结构120的一个或多个鳍结构形成在半导体衬底100上方。在一些实施例中，半导体衬底100是诸如半导体晶圆的块状半导体衬底。例如，半导体衬底100是硅晶圆。半导体衬底100可以包括硅或诸如锗的另一元素半导体材料。在一些其他实施例中，半导体衬底100包括化合物半导体。化合物半导体可以包括砷化镓、碳化硅、砷化铟、磷化铟、另一合适的材料或它们的组合。
在一些实施例中，半导体衬底100包括绝缘体上半导体(SOI)衬底。可以使用注氧隔离(SIMOX)工艺、晶圆接合工艺、另一适用的方法或它们的组合来制造SOI衬底。
在一些实施例中，在半导体衬底100中形成多个凹槽(或沟槽)。结果，包括鳍结构120的多个鳍结构形成在凹槽之间。为了简便，仅示出一个鳍结构(鳍结构120)。在一些实施例中，使用一个或多个光刻和蚀刻工艺以形成凹槽。
如图1A和2A所示，根据一些实施例，在凹槽中形成隔离部件130以围绕鳍结构120的下部。在一些实施例中，隔离部件130连续围绕鳍结构 120的下部。在一些实施例中，隔离部件130围绕形成在半导体衬底100 上的其他鳍结构的下部。隔离部件130用于限定和电隔离形成在半导体衬底100中和/或上方的各个器件元件。在一些实施例中，隔离部件130包括浅沟槽隔离(STI)部件、硅的局部氧化(LOCOS)部件、其他合适的隔离部件或它们的组合。
在一些实施例中，每个隔离部件130都具有多层结构。在一些实施例中，隔离部件130由介电材料制成。介电材料可以包括氧化硅、氮化硅、氮氧化硅、掺杂氟的硅酸盐玻璃(FSG)、低K介电材料、另一合适的材料或它们的组合。在一些实施例中，形成STI衬垫(未示出)以减少半导体衬底100与隔离部件130之间的界面处的晶体缺陷。也可以使用STI衬垫以减少鳍结构与隔离部件130之间的界面处的晶体缺陷。
在一些实施例中，在半导体衬底100上方沉积介电材料层。介电材料层覆盖包括鳍结构120的鳍结构并且填充鳍结构之间的凹槽。在一些实施例中，实施平坦化工艺以减薄介电材料层。例如，减薄介电材料层直到暴露鳍结构120。平坦化工艺可以包括化学机械抛光(CMP)工艺、研磨工艺、干抛光工艺、蚀刻工艺、另一适用的工艺或它们的组合。之后，回蚀刻介电材料层至鳍结构120的顶部下方。结果，形成隔离部件130。如图 1A和图2A所示，根据一些实施例，包括鳍结构120的鳍结构从隔离部件 130的顶面突出。
如图1B和2B所示，根据一些实施例，包括栅极介电层140和栅电极 150的伪栅极堆叠件形成在鳍结构120和半导体衬底100上方。伪栅极堆叠件覆盖鳍结构120的一部分。在一些实施例中，伪栅极堆叠件覆盖包括鳍结构120的多个鳍结构的一部分。
在一些实施例中，栅极介电层140由以下材料制成：氧化硅、氮化硅、氮氧化硅、具有高介电常数(高K)的介电材料、另一合适的介电材料或它们的组合。高K介电材料的实例包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金、氧化硅铪、氮氧化硅铪、氧化钽铪、氧化钛铪、氧化锆铪、另一合适的高K材料或它们的组合。在一些实施例中，栅极介电层140是随后将被去除的伪栅极介电层。在一些其他实施例中，不形成栅极介电层 140。
在一些实施例中，使用化学汽相沉积(CVD)工艺、原子层沉积(ALD) 工艺、热氧化工艺、物理汽相沉积(PVD)工艺、另一适用的工艺或它们的组合在隔离部件130和鳍结构120上方沉积栅极介电层140。
之后，如图1B和图2B所示，根据一些实施例，栅电极150形成在栅极介电层140上方以覆盖鳍结构120的一部分。在一些实施例中，栅电极 150是将被金属栅电极替代的伪栅电极。在一些实施例中，栅电极150由多晶硅制成。
在一些实施例中，栅电极层沉积在栅极介电层140上方。可以使用CVD 工艺或另一适用的工艺沉积栅电极层。在一些实施例中，栅电极层由多晶硅制成。之后，根据一些实施例，在栅电极层上方形成图案化的硬掩模层 (未示出)。图案化的硬掩模层用于将栅电极层图案化为包括栅电极150 的一个或多个栅电极。一个或多个蚀刻工艺可以用于通过图案化的硬掩模层的开口蚀刻栅电极层从而形成伪栅极堆叠件。
之后，如图1B所示，根据一些实施例，在栅电极150的侧壁上方形成间隔件元件160。间隔件元件160可以用于帮助随后的源极/漏极部件的形成。在一些实施例中，间隔件元件160包括一个或多个层。在一些实施例中，间隔件元件160由介电材料制成。介电材料可以包括氮化硅、氧化硅、氮氧化硅、碳化硅、另一合适的材料或它们的组合。
在一些实施例中，使用CVD工艺、PVD工艺、旋涂工艺、另一适用的工艺或它们的组合在伪栅极堆叠件上方沉积间隔件材料层。之后，使用诸如各向异性刻蚀工艺的蚀刻工艺部分地去除间隔件材料层。结果，如图 1B所示，位于伪栅极堆叠件的侧壁上的间隔件材料层的剩余部分形成间隔件元件160。在一些实施例中，去除栅极介电层140的未被栅电极150覆盖的部分之后，形成间隔件元件160。在一些实施例中，在形成间隔件元件160的蚀刻工艺期间，未被栅电极150覆盖的栅极介电层140和间隔件材料层一起被去除。
之后，如图1B所示，根据一些实施例，在鳍结构120上形成源极/漏极部件170。在一些实施例中，例如，使用蚀刻工艺部分地去除未被栅电极150和间隔件元件160覆盖的鳍结构120以形成凹槽。之后，在凹槽中形成源极/漏极部件170。在一些实施例中，源极/漏极部件170是使用外延生长工艺形成的外延生长部件。在一些实施例中，源极/漏极部件170从凹槽突出。在一些实施例中，源极/漏极部件170也用作应力源，应力源可以对源极/漏极部件170之间的沟道区施加应变或应力。可以相应地提高载流子迁移率。
然后，如图1B和2B所示，根据一些实施例，形成介电层180以围绕伪栅极堆叠件和源极/漏极部件170。为了更好地理解本发明，图1B中的介电层180用虚线示出，从而使得被介电层180覆盖的元件可见。在一些实施例中，沉积介电材料层以覆盖源极/漏极部件170、间隔件元件160和栅电极150。
在一些实施例中，介电材料层由氧化硅、氮氧化硅、硼硅酸盐玻璃 (BSG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、掺杂氟的硅酸盐玻璃(FSG)、低k材料、多孔介电材料、另一合适的材料或它们的组合制成。在一些实施例中，使用CVD工艺、ALD工艺、旋涂工艺、喷涂工艺、另一适用的工艺或它们的组合沉积介电材料层。
之后，可以使用平坦化工艺部分地去除介电材料层。可以部分地去除介电材料层直到暴露栅电极150。结果，形成介电层180。在一些实施例中，平坦化工艺包括CMP工艺、研磨工艺、干抛光工艺、蚀刻工艺、另一适用的工艺或它们的组合。
如图1C和2C所示，根据一些实施例，去除栅电极150和栅极介电层 140以形成凹槽210。凹槽210由介电层180围绕并且定位在间隔件元件 160之间。凹槽210暴露鳍结构120。可以使用一种或多个蚀刻工艺以形成凹槽210。在一些实施例中，栅极介电层140的直接位于间隔件元件160 下方的部分保持不被去除。
如图2D中所示，根据一些实施例，栅极介电层192沉积在介电层180 以及凹槽210的侧壁和底部上方。在一些实施例中，栅极介电层192共形地覆盖鳍结构120以及凹槽210的侧壁和底部。
在一些实施例中，栅极介电层192和位于间隔件元件160下方的栅极介电层140由不同的材料制成。在一些实施例中，栅极介电层192由高K 介电材料制成。高K介电材料可以包括氧化铪、氧化锆、氧化铝、二氧化铪-氧化铝合金、氧化硅铪、氮氧化硅铪、氧化钽铪、氧化钛铪、氧化锆铪、另一合适的高K材料或它们的组合。在一些实施例中，使用ALD工艺、 CVD工艺、另一适用的工艺或它们的组合沉积栅极介电层192。
之后，如图2D所示，根据一些实施例，在栅极介电层192上方沉积功函数层194。在一些实施例中，功函数层194共形地覆盖鳍结构120。功函数层194用于为晶体管提供期望的功函数以增强器件性能，诸如改进的阈值电压。在一些实施例中，功函数层194是能够提供适合于器件的功函数值(诸如等于或小于约4.5eV)的n型金属层。在一些实施例中，功函数层 194是能够提供适合于器件的功函数值(诸如等于或大于约4.8eV)的p型金属层。
n型金属层可以包括金属、金属碳化物、金属氮化物或它们的组合。例如，n型金属层包括氮化钛、钽、氮化钽、其他合适的材料或它们的组合。p型金属层可以包括金属、金属碳化物、金属氮化物、其他合适的材料或它们的组合。例如，p型金属包括氮化钽、氮化钨、钛、氮化钛、其他合适的材料或它们的组合。
功函数层194也可以由铪、锆、钛、钽、铝、金属碳化物(如，碳化铪、碳化锆、碳化钛、碳化铝)、铝化合物、钌、钯、铂、钴、镍、导电金属氧化物或它们的组合制成。可以微调整功函数层194的厚度和/或组分以调节功函数等级。例如，氮化钛层可以用作p-型金属层或n-型金属层，这取决于氮化钛层的厚度和/或组分。
在一些实施例中，功函数层194是多个子层的堆叠件。在一些实施例中，势垒层(未示出)形成在栅极介电层192与功函数层194之间。势垒层可以由氮化钛、氮化钽、另一合适的材料或它们的组合制成。在一些实施例中，在随后的导电填料形成之前，在功函数层194上方形成阻挡层(未示出)。阻挡层可以由氮化钽、氮化钛、另一合适的材料或它们的组合制成。在一些实施例中，使用CVD工艺、电镀工艺、PVD工艺、无电镀工艺、另一适用的工艺或它们的组合沉积功函数层194、势垒层和阻挡层。
如图2D所示，在形成栅极介电层192和功函数层194之后，凹槽210 的一部分缩小以形成具有宽度W1的间隙211。在一些实施例中，宽度W1较小。结果，随后的导电填料的形成可能难以实施。导电填料可能不能完全填充间隙211。可能不利地影响半导体器件结构的性能和可靠性。
如图2E所示，根据一些实施例，扩大间隙211以有助于随后的导电填料的形成。如图2E所示，在一些实施例中，去除功函数层194的在介电层 180的侧壁179上的部分。因此，扩大间隙211。如图2E所示，在一些实施例中，还去除栅极介电层192的在介电层180的侧壁179上的部分。进一步扩大间隙211。如图2E所示，扩大间隙211以具有比宽度W1大的宽度W2。在一些实施例中，宽度W2在从约0.5nm至约50nm的范围内。如图2E所示，在一些实施例中，在部分地去除功函数层194和栅极介电层 192之后，暴露介电层180的侧壁179。
在一些实施例中，图案化的掩模层(未示出)形成在图2E中示出的结构上方。在一些实施例中，图案化的掩模层是具有开口的图案化的光刻胶层，该开口暴露功函数层194和栅极介电层192的位于介电层180的侧壁 179上的部分。之后，使用一种或多种蚀刻工艺以部分地去除功函数层194 和栅极介电层192。例如，使用第一蚀刻工艺以去除功函数层194的暴露部分。之后，使用第二蚀刻工艺以去除栅极介电层192的暴露部分。
如图1D和2F所示，根据一些实施例，沉积导电填料196以填充凹槽 210。结果，形成包括栅极介电层192、功函数层194和导电填料196的栅极堆叠件198(或金属栅极堆叠件)。在一些实施例中，导电填料196由金属材料制成。金属材料可以包括钨、铝、铜、另一合适的材料或它们的组合。
在一些实施例中，在介电层180上方沉积导电材料层以填充凹槽210。可以使用CVD工艺、电镀工艺、PVD工艺、无电镀工艺、另一适用的工艺或它们的组合来沉积导电材料层。由于去除介电层180的侧壁179上的栅极介电层192和功函数层194，间隙211变得更大并且更容易被导电材料层完全填充。基本没有空隙形成在填充凹槽210的导电材料层中。因此改善了半导体器件结构的质量。
之后，实施平坦化工艺以去除栅极介电层192、功函数层194和导电材料层的位于凹槽210外部的部分。导电材料层的剩余的部分形成导电填料196。结果，如图1D和图2F所示，形成栅极堆叠件198。在一些实施例中，在平坦工艺之后，介电层180、导电填料196、栅极介电层192和功函数层194的顶面基本共面。
如图1D所示，间隔件元件160形成在栅极堆叠件198的侧壁上。在一些实施例中，间隔件元件160与栅极介电层192直接接触。在一些实施例中，间隔件元件160与导电填料196直接接触。在一些实施例中，功函数层194通过导电填料196和/或间隔件元件160与介电层180分离。
如图2F所示，在一些实施例中，功函数层194和栅极介电层192分别具有侧边194S1和192S1。在一些实施例中，侧边194S1和192S1位于栅极堆叠件198的顶部与底部之间。在一些实施例中，导电填料196覆盖侧边 194S1和/或192S1。在一些实施例中，导电填料196与侧边194S1和/或192S1直接接触。如图2F所示，在一些实施例中，导电填料196具有定位在介电层180与功函数层194之间的部分197。
如图1D所示，栅极介电层192具有位于栅极堆叠件198的顶部处的侧边192S2。功函数层194具有位于栅极堆叠件198的顶部处的侧边194S2。在一些实施例中，导电填料196覆盖侧边194S2和/或192S2。在一些实施例中，导电填料196与侧边194S2和/或192S2直接接触。
如图1D和2F所示，根据一些实施例，导电填料196和间隔件元件160 一起围绕功函数层194和栅极介电层192。在一些实施例中，功函数层194 和栅极介电层192由于导电填料196和间隔件元件160而不与介电层180 直接接触。
如图1D所示，介电层180围绕栅极堆叠件198。距离d1位于介电层 180与功函数层194之间。在一些实施例中，距离d1是介电层180与功函数层194之间的最短距离。在一些实施例中，距离d1大于介电层180与导电填料196之间的最短距离。在图1D或图2F所示的实施例中，介电层180 与导电填料196直接接触。介电层180与导电填料196之间的最短距离等于零，这小于介电层180与功函数层194之间的最短距离(诸如距离d1)。
如图1D所示，距离d3位于功函数层194与一个间隔件元件160之间。在一些实施例中，距离d3是功函数层194与一个间隔件元件160之间的最短距离。在一些实施例中，介电层180与功函数层194之间的最短距离(诸如距离d1)大于功函数层194与一个间隔件元件160之间的最短距离(诸如距离d3)。
可以对本发明的实施例作出许多变化和/或修改。在图1A至图1D和/或图2A至图2F所示的实施例中，完全去除介电层180的侧壁179上的栅极介电层192和功函数层194以有助于导电填料196的形成。然而，本发明的实施例并不限于此。在一些其他实施例中，不完全去除但是部分去除介电层180的侧壁179 上的栅极介电层192和功函数层194。在部分地去除侧壁179上的栅极介电层192和功函数层194之后，还扩大间隙211。导电填料196的形成仍然变得容易。
图3是根据一些实施例的半导体器件结构的截面图。在一些实施例中，去除介电层180的侧壁179上的功函数层194。不去除或仅部分地去除侧壁179上的栅极介电层192。栅极介电层192保持在侧壁179上。在这些情况中，栅极介电层192将导电填料196与介电层180分离。距离d2位于导电填料196与介电层180之间。在一些实施例中，距离d2是导电填料196 与介电层180之间的最短距离。在一些实施例中，介电层180与导电填料 196之间的最短距离(诸如距离d2)小于介电层180与功函数层194之间的最短距离。
本发明的实施例利用金属栅极堆叠件替代了半导体器件结构的伪栅极堆叠件，金属栅极堆叠件包括栅极介电层、功函数层和导电填料。在伪栅极堆叠件被替代之前，形成介电层以围绕伪栅极堆叠件。之后，去除伪栅极以在介电层中形成凹槽。在凹槽的侧壁和底部上方形成栅极介电层和功函数层。从介电层的侧壁去除功函数层和/或栅极介电层的一部分以扩大凹槽中的间隙。因此，随后在凹槽中形成导电填料变得容易实施。半导体器件结构的性能和可靠性显著提高。
根据一些实施例，提供了一种半导体器件结构。半导体器件结构包括位于半导体衬底上方的鳍结构和覆盖鳍结构的一部分的栅极堆叠件。栅极堆叠件包括栅极介电层、功函数层和位于功函数层上方的导电填料。半导体器件结构还包括覆盖鳍结构的介电层。介电层与导电填料直接接触。
根据一些实施例，提供了一种半导体器件结构。半导体器件结构包括位于半导体衬底上方的鳍结构和覆盖鳍结构的一部分的栅极堆叠件。栅极堆叠件包括栅极介电层、功函数层和位于功函数层上方的导电填料。半导体器件结构还包括覆盖鳍结构和围绕栅极堆叠件的介电层。介电层与功函数层之间的最短距离大于介电层与导电填料之间的最短距离。
根据一些实施例，提供了用于形成半导体器件结构的方法。方法包括：在半导体衬底上方形成伪栅极堆叠件以及形成介电层以围绕伪栅极堆叠件。方法还包括：去除伪栅极堆叠件以形成由介电层围绕的凹槽并且在凹槽的侧壁和底部上方形成栅极介电层和功函数层。方法还包括：去除功函数层的位于介电层的侧壁上的部分。另外，方法包括：在去除功函数层的位于介电层的侧壁上的部分之后，形成导电填料以填充凹槽。
本发明的实施例提供了一种半导体器件结构，包括：鳍结构，位于半导体衬底上方；栅极堆叠件，覆盖所述鳍结构的一部分，其中，所述栅极堆叠件包括栅极介电层、功函数层和位于所述功函数层上方的导电填料；以及介电层，覆盖所述鳍结构，其中，所述介电层与所述导电填料直接接触。
根据本发明的一个实施例，半导体器件结构还包括：间隔件元件，位于所述栅极堆叠件的侧壁上，其中，所述间隔件元件与所述栅极介电层直接接触。
根据本发明的一个实施例，其中，所述间隔件元件与所述导电填料直接接触。
根据本发明的一个实施例，其中，所述功函数层通过所述导电填料或所述间隔件元件与所述介电层分离。
根据本发明的一个实施例，其中，所述功函数层具有位于所述栅极堆叠件的顶部与底部之间的侧边。
根据本发明的一个实施例，其中，所述导电填料覆盖所述功函数层的侧边。
根据本发明的一个实施例，其中，所述导电填料与所述功函数层的侧边直接接触。
根据本发明的一个实施例，其中，所述介电层围绕所述栅极堆叠件，所述介电层与所述功函数层之间的最短距离大于所述介电层与所述导电填料之间的最短距离。
根据本发明的一个实施例，其中，所述功函数层和所述栅极介电层不与所述介电层直接接触。
根据本发明的一个实施例，其中，所述导电填料的一部分位于所述介电层与所述功函数层之间。
本发明的实施例还提供了一种半导体器件结构，包括：鳍结构，位于半导体衬底上方；栅极堆叠件，覆盖所述鳍结构的一部分，其中，所述栅极堆叠件包括栅极介电层、功函数层和位于所述功函数层上方的导电填料；以及介电层，覆盖所述鳍结构并且围绕所述栅极堆叠件，其中，所述介电层与所述功函数层之间的最短距离大于所述介电层与所述导电填料之间的最短距离。
根据本发明的一个实施例，其中，所述功函数层具有位于所述栅极堆叠件的顶部与底部之间的侧边，并且所述导电填料覆盖所述功函数层的侧边。
根据本发明的一个实施例，半导体器件结构还包括：间隔件元件，位于所述栅极堆叠件的侧壁上，其中，所述功函数层与所述介电层之间的最短距离大于所述功函数层与所述间隔件元件之间的最短距离。
根据本发明的一个实施例，其中，所述导电填料与所述间隔件元件直接接触。
根据本发明的一个实施例，其中，所述功函数层具有位于所述栅极堆叠件的顶部处的侧边，并且所述导电填料覆盖所述功函数层的侧边。
本发明的实施例还提供了一种用于形成半导体器件结构的方法，包括：在半导体衬底上方形成伪栅极堆叠件；形成介电层以围绕所述伪栅极堆叠件；去除所述伪栅极堆叠件以形成由所述介电层围绕的凹槽；在所述凹槽的侧壁和底部上方形成栅极介电层和功函数层；去除所述功函数层的位于所述介电层的侧壁上的部分；在去除所述功函数层的位于所述介电层的侧壁上的部分之后，形成导电填料以填充所述凹槽。
根据本发明的一个实施例，方法还包括在形成所述伪栅极堆叠件之前，在所述半导体衬底上方形成鳍结构。
根据本发明的一个实施例，方法还包括：去除所述栅极介电层的位于所述介电层的侧壁上的部分。
根据本发明的一个实施例，其中，部分地去除所述功函数层和所述栅极介电层之后，在所述凹槽中暴露所述介电层的侧壁。
根据本发明的一个实施例，方法还包括：实施平坦化工艺，从而使得所述介电层、所述导电填料、所述栅极介电层和所述功函数层的顶面共面。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体器件结构，包括：
鳍结构，位于半导体衬底上方；
隔离部件，邻近所述鳍结构；
栅极堆叠件，覆盖所述鳍结构的一部分，其中，所述栅极堆叠件包括栅极介电层、功函数层和位于所述功函数层上方的导电填料，其中，所述导电填料覆盖所述功函数层的侧边；以及
介电层，覆盖所述鳍结构，其中，所述介电层与所述导电填料直接接触，
其中，所述功函数层终止在所述鳍结构和所述介电层之间的隔离部件上方。
2.根据权利要求1所述的半导体器件结构，还包括：间隔件元件，位于所述栅极堆叠件的侧壁上，其中，所述间隔件元件与所述栅极介电层直接接触。
3.根据权利要求2所述的半导体器件结构，其中，所述间隔件元件与所述导电填料直接接触。
4.根据权利要求2所述的半导体器件结构，其中，所述功函数层通过所述导电填料或所述间隔件元件与所述介电层分离。
5.根据权利要求1所述的半导体器件结构，其中，所述功函数层具有位于所述栅极堆叠件的顶部与底部之间的侧边。
6.根据权利要求5所述的半导体器件结构，其中，所述导电填料覆盖所述功函数层的侧边。
7.根据权利要求5所述的半导体器件结构，其中，所述导电填料与所述功函数层的侧边直接接触。
8.根据权利要求1所述的半导体器件结构，其中，所述介电层围绕所述栅极堆叠件，所述介电层与所述功函数层之间的最短距离大于所述介电层与所述导电填料之间的最短距离。
9.根据权利要求1所述的半导体器件结构，其中，所述功函数层和所述栅极介电层不与所述介电层直接接触。
10.根据权利要求1所述的半导体器件结构，其中，所述导电填料的一部分位于所述介电层与所述功函数层之间。
11.一种半导体器件结构，包括：
鳍结构，位于半导体衬底上方；
栅极堆叠件，覆盖所述鳍结构的一部分，其中，所述栅极堆叠件包括栅极介电层、功函数层和位于所述功函数层上方的导电填料；以及
介电层，覆盖所述鳍结构并且围绕所述栅极堆叠件，其中，所述介电层与所述功函数层之间的最短距离大于所述介电层与所述导电填料之间的最短距离，并且其中，所述导电填料覆盖所述功函数层的侧边。
12.根据权利要求11所述的半导体器件结构，其中，所述功函数层具有位于所述栅极堆叠件的顶部与底部之间的侧边。
13.根据权利要求11所述的半导体器件结构，还包括：间隔件元件，位于所述栅极堆叠件的侧壁上，其中，所述功函数层与所述介电层之间的最短距离大于所述功函数层与所述间隔件元件之间的最短距离。
14.根据权利要求13所述的半导体器件结构，其中，所述导电填料与所述间隔件元件直接接触。
15.根据权利要求11所述的半导体器件结构，其中，所述功函数层具有位于所述栅极堆叠件的顶部处的侧边。
16.一种用于形成半导体器件结构的方法，包括：
在半导体衬底上方形成伪栅极堆叠件；
形成介电层以围绕所述伪栅极堆叠件；
去除所述伪栅极堆叠件以形成由所述介电层围绕的凹槽；
在所述凹槽的侧壁和底部上方形成栅极介电层和功函数层；
去除所述功函数层的位于所述介电层的侧壁上的部分；
在去除所述功函数层的位于所述介电层的侧壁上的部分之后，形成导电填料以填充所述凹槽。
17.根据权利要求16所述的用于形成半导体器件结构的方法，还包括在形成所述伪栅极堆叠件之前，在所述半导体衬底上方形成鳍结构。
18.根据权利要求16所述的用于形成半导体器件结构的方法，还包括：去除所述栅极介电层的位于所述介电层的侧壁上的部分。
19.根据权利要求18所述的用于形成半导体器件结构的方法，其中，部分地去除所述功函数层和所述栅极介电层之后，在所述凹槽中暴露所述介电层的侧壁。
20.根据权利要求16所述的用于形成半导体器件结构的方法，还包括：实施平坦化工艺，从而使得所述介电层、所述导电填料、所述栅极介电层和所述功函数层的顶面共面。
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US20190348330A1 (en) 2019-11-14
CN106653848A (zh) 2017-05-10
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US9673331B2 (en) 2017-06-06
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US20170236939A1 (en) 2017-08-17
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