CN103325832A - 具有金属栅极应激源的finfet - Google Patents

具有金属栅极应激源的finfet Download PDF

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CN103325832A
CN103325832A CN2013100078980A CN201310007898A CN103325832A CN 103325832 A CN103325832 A CN 103325832A CN 2013100078980 A CN2013100078980 A CN 2013100078980A CN 201310007898 A CN201310007898 A CN 201310007898A CN 103325832 A CN103325832 A CN 103325832A
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stressor
grid
fin
sidewall
layer
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CN103325832B (zh
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巫凯雄
奧野泰利
简珮珊
曾伟雄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

提供用于鳍式场效晶体管(FinFET)器件的栅极应激源。栅极应激源包括底面、第一应激源侧壁、以及第二应激源侧壁。在栅极层的第一部分上形成底面。栅极层设置在浅沟槽隔离(STI)区域上。在栅极层的第二部分上形成第一应激源侧壁。栅极层的第二部分设置在鳍的侧壁上。在栅极层的第三部分上形成第二应激源侧壁。栅极层的第三部分设置在与鳍间隔开的结构的侧壁上。第一应激源侧壁和第二应激源侧壁没有超过鳍的高度。

Description

具有金属栅极应激源的FINFET
技术领域
本发明一般地涉及半导体技术领域，更具体地来说，涉及场效应晶体管。
背景技术
半导体器件用在诸如计算机、手机等的大量电子装置中。半导体器件包括集成电路，通过在半导体晶圆上沉积多种类型的薄膜材料，以及图案化薄膜材料以形成集成电路来在半导体晶圆上形成集成电路。集成电路包括诸如金属氧化物半导体(MOS)晶体管的场效应晶体管(FET)。
半导体工业目标之一是继续缩减独立FET的尺寸并提高其速度。为了实现这些目标，在32nm以下的晶体管节点中使用鳍式FET(FinFET)或多栅极晶体管。例如，FinFET不仅提高了区域密度，并且提高沟道的栅极控制。
近年来，已经利用替换栅极工艺构造FinFET。在这种工艺期间，FinFET最初设置有多晶硅栅极，这样能够更好地经受紧接处理操作的更为苛刻的处理条件。此后，在稍后的处理阶段中，当处理条件不太苛刻时，从FinFET结构去除多晶硅栅极并且通过持久的金属栅极代替。
已知替换栅极工艺还带来了限制，从而随着技术提升、集成水平提高以及部件尺寸变小而引起了更多的关注。
发明内容
为了解决现有技术中所存在的缺陷，根据本发明的一方面，提供了一种用于鳍式场效晶体管(FinFET)器件的栅极应激源，包括：底面，形成在栅极层的第一部分上，所述栅极层设置在浅沟槽隔离(STI)区域上方；第一应激源侧壁，形成在所述栅极层的第二部分上，所述栅极层的第二部分设置在鳍的侧壁上；以及第二应激源侧壁，形成在所述栅极层的第三部分上，所述栅极层的第三部分设置在与所述鳍间隔开的结构的结构侧壁上，所述第一应激源侧壁与所述第二应激源侧壁没有超过所述鳍的高度。
在该栅极应激源中，所述底面与所述第一应激源侧壁和所述第二应激源侧壁由金属形成。
在该栅极应激源中，所述底面、所述第一应激源侧壁和第二应激源侧壁中的一个或多个被配置为对所述鳍的晶体管沟道施加应力。
在该栅极应激源中，所述底面、所述第一应激源侧壁和所述第二应激源侧壁中的一个或多个被配置成对所述鳍的晶体管沟道提供拉伸应力。
在该栅极应激源中，所述底面、所述第一应激源侧壁和所述第二应激源侧壁中的一个或多个被配置成对所述鳍的晶体管沟道提供压缩应力。
在该栅极应激源中，所述结构是第二鳍。
在该栅极应激源中，所述结构是层间介电层。
在该栅极应激源中，所述底面与所述第一应激源和所述第二应激源侧壁由金属形成。
根据本发明的另一方面，提供了一种鳍式场效晶体管(FinFET)器件，包括：鳍，提供晶体管沟道；结构，通过浅沟槽隔离(STI)区域与所述鳍间隔开；栅极层，形成在所述结构、所述STI区域、所述鳍上方；以及栅极应激源，形成在所述栅极层中设置在所述结构与所述鳍之间的所述STI区域上的第一部分上方，并且形成在所述栅极层中设置在所述鳍的侧壁与所述结构的侧壁上的第二部分上方。
在该器件中，所述栅极应激源包含金属。
在该器件中，所述栅极应激源被配置成对所述鳍的晶体管沟道施加应力。
在该器件中，所述栅极应激源被配置成向所述鳍的晶体管沟道施加拉伸应力。
在该器件中，所述栅极应激源被配置成向所述鳍的晶体管沟道施加压缩应力。
在该器件中，所述栅极应激源包括水平定向的底面之间的垂直定向的侧壁。
在该器件中，所述栅极应激源的侧壁没有超过所述鳍的高度。
在该器件中，所述结构是第二鳍与层间介电层中的一个。
在该器件中，所述第二鳍通过所述STI区域与所述鳍间隔开，所述第二鳍相对于所述结构在所述鳍的相对侧上，并且第二栅极应激源形成在所述鳍与所述第二鳍之间。
根据本发明的又一方面，提供了一种形成用于鳍式场效晶体管(FinFET)器件的栅极应激源的方法，包括：在栅极层的第一部分上形成底面，所述栅极层设置在浅沟槽隔离(STI)区域上方；在所述栅极层的第二部分上形成第一应激源侧壁，所述栅极层的第二部分设置在鳍的侧壁上；以及在所述栅极层的第三部分上形成第二应激源侧壁，所述栅极层的第三部分设置在与所述鳍间隔开的结构的侧壁上，所述第一应激源侧壁与所述第二应激源侧壁没有超过所述鳍的高度。
该方法还包括利用原子层沉积工艺形成所述底面、所述第一应激源侧壁以及所述第二应激源侧壁，以对晶体管沟道提供拉伸应力。
该方法还包括利用物理汽相沉积工艺形成所述底面、所述第一应激源侧壁以及所述第二应激源侧壁，以对晶体管沟道提供压缩应力。
附图说明
为更完整地理解本发明，以及其优点，现在将结合附图所进行的以下描述作为参考：
图1是示出在半导体鳍上所形成的牺牲栅极的部分截面的透视三维图；
图2是通常沿着图1的线2-2所截取的牺牲栅极结构的截面图；
图3至图4是示出对于图2所示的结构实施随后的处理操作以形成并去除替换金属栅极的截面图；
图5a/5b至10a/10b是示出采用处理操作以产生金属栅极应激源的实施例的截面图；
图11a至11b是示出使用处理操作以在图10b的栅极应激源上方形成功函金属的实施例的截面图。
图12是允许侧壁合并在一起的图10b的栅极应激源的实施例的截面图；以及
图13是形成图10b的栅极应激源的方法的实施例。
除非另外说明，否则不同附图中的相应数字和符号通常指的是相应部件。绘制示图以清楚地示出实施例的有关方面，但没有必要按比例绘图。
具体实施方式
下面详细描述本优选实施例的制造和使用。然而，应该理解，本公开内容提供了许多可以在各种具体环境中实现的可应用的发明原理。讨论的具体实施例仅是说明性的，不限于本公开内容的范围。
将结合具体上下文中的优选实施例描述本公开内容，即，FinFET金属氧化物半导体(MOS)。然而，本发明还可应用于其它集成电路、电子结构等。
图1是示出在半导体鳍上方形成的牺牲栅极的部分截面的透视三维图。利用已知技术在衬底12上方形成半导体鳍4。半导体鳍4可以由硅、硅锗、锗或其它合适的半导体材料形成。半导体鳍4包括相对侧面6和顶部8，并且设置在STI(浅沟槽隔离)结构10之间。半导体鳍4包括可能从大约5nm到大约50nm变化的宽度16。高度14可以在大约5nm到大约50nm的范围内。半导体鳍4的总高度，即，顶部8与半导体鳍4和衬底12之间的界面之间的距离可以是大约60nm到大约90nm，但是在其它实施例中，可以使用各种其它尺寸。各种合适的衬底可以用作衬底12。
沿着半导体鳍4的顶部8和侧面6限定晶体管沟道22(又名栅极沟道)，且其在源极S和漏极D区域之间延伸。利用晶体管沟道22沿着半导体鳍4可以形成诸如FinFET晶体管的晶体管。牺牲栅极20在图1中示出，并且可以由耐用且热稳定的但易于移动的多晶硅或其它非金属材料形成。可以使用形成图1所示的结构的各种已知的方法中的任一种。牺牲栅极20包括宽度26和高度24，宽度26基本用作晶体管沟道22的沟道长度。根据各种示例性实施例，高度24可以在大约75nm至120nm的范围内变动，并且在一个优选实施例中，可以是大约90nm，并且在一个示例性实施例中，宽度26可以是大约22nm，但是在其它示例性实施例中，可以在大约5nm到大约50nm的范围内变动。牺牲栅极20沿着半导体鳍4的侧面6和顶部8延伸，并且还延伸横向穿过相对侧面6。尽管在图1中不可见，但是优选地，硬掩模可以形成在牺牲栅极20下方以及形成晶体管沟道22的侧面6和顶部8的表面上方，即，牺牲栅极20与半导体鳍4之间的界面处(参见图2)。
图2是通常沿着图1的线2-2所截取的截面图且仅示出了图1所示的结构的上部。图2示出设置在半导体鳍4的顶部8的牺牲栅极20。图2还示出了任选的硬掩模34，在形成牺牲栅极20之前，利用常规方法来形成该硬掩模。在其它示例性实施例中，可以不使用硬掩模34。尽管如参照图1所示，由于截取的截面，仅示出了牺牲栅极20位于图2的半导体鳍4的顶部8上方，但是应当理解，如图1所示，牺牲栅极20延伸进入附图平面之中和延伸出附图平面，以及沿着并穿过对应的相对侧面6。
然后，可以使用均匀或其它沉积操作以在图2所示的结构上方形成介电层，并且该沉积工艺之后可以进行平坦化工艺以制造图3所示的结构。层间介电层32可以是用作ILD、层间介电层或ND、金属间介电层、半导体领域中公知的合适的任意各种合适的电介质。在沉积层间介电层32之前，可以形成可选隔离件，可以通过虚线来表示可选隔离件38。可以在可选隔离件38的形成中使用常规方法和材料。在平坦化之后，顶面36通常是平面，并且包括层间介电层32和牺牲栅极20的共面的上表面。
图4示出在使用去除操作之后的图3的结构(没有可选隔离件38)。去除操作顺序去除牺牲栅极20和硬掩模34，从而在层间介电层32中形成开口40。可以使用各种操作选择性去除牺牲栅极20和硬掩模34以形成开口40而不损坏下面的晶体管沟道22。在各种示例性实施例中，可以使用湿化学蚀刻操作，也可以使用RIE(反应离子蚀刻)操作，或可以使用各种其它合适的蚀刻操作。去除牺牲栅极20之后，如图4所示，在硬掩模34处停止蚀刻以避免损坏半导体鳍4的晶体管沟道22的表面，然后去除硬掩模34以暴露半导体鳍4的顶部8的晶体管沟道22的表面部分，以及还暴露沿着半导体鳍4的侧面6的部分晶体管沟道22。通过层间介电层32在其侧面上限定牺牲栅极20先前所占用的层间介电层32中的开口40，并且下面具有通过形成晶体管沟道22的半导体鳍4的表面。
现在参照图5a至图5b，提供类似于图1的结构的上部的X切面和Y切面的截面图。如图5a所示，X切面所示的结构包括开口40和层间介电层32(类似于图4的结构)。然而，为说明X切面的目的，还示出了源极S和漏极D区域，STI结构10、以及鳍4的更多部分。此外，为说明图5b的Y切面，横向穿过X切面，包括投影到STI结构10上的2个鳍4。
如图5a所示，从附图的左侧前进至右侧，在层间介电层32的顶面上方、沿着层间介电层32的侧壁44、在晶体管沟道22上的鳍4的顶面8上方、以及再次沿着侧壁44和在层间介电层32的顶面上方形成栅极层42。如图5b所示，从附图的左侧前进至右侧，在层间介电层32的顶面上方、在STI区域10的顶面上方、沿着鳍4的侧壁44、在晶体管沟道22上的鳍4的顶面8上方、再次沿着鳍4的侧壁44、在STI区域10的顶面上方、沿着相邻状物4的侧壁44等形成栅极层42。
在图5a-5b中，在实施例中，栅极层42共同表示界面氧化层、高k值介电层、以及金属层。可以利用原子层沉积(ALD)工艺、物理汽相沉积(PVD)工艺、化学氧化工艺、低压化学汽相沉积(LPCVD)工艺、或其它合适的方法来沉积界面氧化层。例如，通过ALD工艺或其它合适的方法沉积高k介电层。
可以使用各种材料以形成栅极层42的介电层部分，例如氧化铪(HfO2)、氧化锆(ZrO2)、或具有期望高介电常数k(即，高于二氧化硅(SiO2)的介电常数)的其它合适的栅极介电材料。可以使用各种合适的厚度，并且结合器件速度和应用来选择。
在栅极层42形成之后，如图6a-6b所示，在栅极层42上方形成栅极应激源层46(又名改性层)。在实施例中，栅极应激源层46由利用ALD工艺沉积的氮化钛(TiN)形成，以向晶体管沟道22添加张力。在实施例中，栅极应激源层46由利用PVD工艺以压缩晶体管沟道22而沉积的氮化钛(TiN)形成。在实施例中，如图6A-6b所示，栅极应激源层46可以是共形的。在另一实施例中，栅极应激源层46不必是共形的。在一个实施例中，栅极应激源层46可以由掺杂材料(例如，p-掺杂材料)形成。在一个实施例中，例如，栅极应激源层46由介电材料形成以控制鳍4的高度。
在形成栅极应激源层46之后，如图7a-7b所示，在栅极应激源层46上方形成旋涂玻璃(SOG)层48。可以利用N或P型图案化方案形成来SOG层48。如图8a-8b所示，使用干蚀刻方法去除SOG层48的上部而未损坏下面的栅极应激源层46。
如图8a-8b所示，SOG层48的剩余部分通常位于相邻鳍4之间或1个鳍4和层间介电层32之间。在实施例中，例如，SOG层48的剩余部分设置在鳍4的顶面8、鳍4上的栅极层42的顶面、或鳍4上的栅极应激源层46的顶面下方。在另一实施例中，SOG层48的剩余部分具有与鳍4的顶面8、鳍4上的栅极层42的顶面、或鳍4上的栅极应激源层46的顶面相同或基本相同的高度。
现在参照图9a-9b，在已经蚀刻掉SOG层48的上部之后，通过湿蚀刻工艺去除栅极应激源层46的上部，从而留下栅极应激源50(又名栅极调节器)。如图10b所示，可以在层间介电层32与相邻鳍4之间形成1个栅极应激源50。可以在相邻鳍4之间形成另一个栅极应激源50。如图所示，栅极应激源50通常包括在水平定向的底面54的相对两端的垂直取向的侧壁52。栅极应激源50的侧壁52通常接合栅极层42设置在鳍4和/或层间介电层32的侧壁44上方的部分。此外，在实施例中，栅极应激源50的底面54通常接合栅极层42设置在STI区域10的顶面上的部分。
栅极应激源50的侧壁52的高度可以通过湿蚀刻工艺精确控制。虽然将图9b的栅极应激源50描述为在侧壁52和底面54之间具有90度的角，但是本领域的技术人员应该意识到且应该理解，侧壁52与底面54之间的过渡是渐进的。事实上，在实际应用中，栅极应激源50可以具有微圆的内角。
在实施例中，如图9b所示，栅极应激源50的侧壁52的顶面与SOG层48的剩余部分的顶面通常是共面的。换句话说，栅极应激源50的侧壁52与SOG层48的剩余部分具有大致相同的高度。
通过使晶体管沟道22处于张力中，沟道NMOS(即，ID FET)的性能可以提升。通过压缩晶体管沟道22，PMOS沟道可以增强。在任一种情况下，栅极应激源50通常提高FinFET结构中的载流子迁移率。
现在参照图10a-10b，在去除栅极应激源层48的上部以及形成栅极应激源50之后，通过额外的图案化和干蚀刻工艺去除SOG层48的剩余部分。如图10b所示，栅极应激源50在干蚀刻工艺之后保持完整无缺。在实施例中，可以利用高度选择的湿蚀刻工艺。在实施例中，可以使用氮化钽(TaN)作为湿蚀刻工艺期间的蚀刻停止层。
现在参照图11a-11b，在实施例中，添加功函金属56以提高功函和/或改变器件的阈值电压。如图11a-11b所示，在栅极层42和栅极应激源50上方形成功函金属56。在实施例中，功函金属56是TiN、TaN、或氮化钛铝(TiAlN)。可以利用ALD、PVD、CVD、或其它合适的工艺来沉积功函金属56。在实施例中，可以在具有第一掺杂(P或N)的一个鳍4上方或周围沉积功函56，而保护具有相对掺杂(N或P)的相邻鳍4。此后，在相对鳍4上方或周围沉积功函金属56，而保护先前通过功函金属56覆盖的最初的鳍4。
在设置功函金属56之后，在功函金属56上方沉积铝58或其它适合的金属。可以利用ALD、PVD、或其它合适的工艺沉积铝58。在功函金属56上方形成铝58之后，可以实施化学机械抛光(CMP)工艺以提供通常具有平滑或平坦顶面的图11a至11b的结构。
现在参照图12，在实施例中，可以继续形成栅极应激源50的工艺(参见图6a-6b)直到栅极应激源50的相对侧壁52(参见图11b)合并在一起。如图所示，这在相邻的鳍4之间或ILD 32与1个鳍4之间形成更厚层的栅极应激源50(相对于图6a-6b的更薄的栅极应激源50)。在某些情况下，当限制相邻的鳍4之间的空间时，栅极应激源50的侧壁52合并。
本领域的技术人员应该理解，本文所公开的栅极应激源50提供大量优点。例如，栅极应激源50提高沟道22的性能，并且允许调节Fin结构上多个阈值电压。此外，在栅极应激源50和任何下层是电介质的实施例中，可以实现精确的鳍高度控制。
现在参照图13，示出形成栅极应激源50的方法60。在框62中，在栅极层42的第一部分上形成底面，该栅极层设置在STI区域10上方。在框64中，在栅极层42的第二部分上形成第一应激源侧壁50。栅极层42的第二部分设置在鳍4的侧壁44上。在框66中，在栅极层42的第三部分上形成第二应激源侧壁50。栅极层42的第三部分设置在与鳍4间隔开的结构(例如，层间介电层32、相邻的鳍4等)的结构侧壁上。在实施例中，第一应激源侧壁与第二应激源侧壁没有超过鳍4的高度14(图1)。
提供了一种用于鳍式场效晶体管(FinFET)器件的栅极应激源。栅极应激源包括：在栅极层的第一部分上形成的底面，栅极层设置在浅沟槽隔离(STI)区域上；在栅极层的第二部分上形成的第一应激源侧壁，栅极层的第二部分设置在鳍的侧壁上；在栅极层的第三部分上形成的第二应激源侧壁，栅极层的第三部分设置在与鳍间隔开的结构的结构侧壁上，第一应激源侧壁与第二应激源侧壁没有超过鳍的高度。
提供了一种鳍式场效晶体管(FinFET)器件。该器件包括：设置晶体管沟道的鳍，通过浅沟槽隔离(STI)区域与鳍间隔开的结构，在该结构、STI区域、鳍上方形成的栅极层，在栅极层设置在该结构与鳍之间的STI区域上的的第一部分上方形成的栅极应激源，并且栅极层沉积在鳍侧壁和该结构侧壁上的第二部分上方形成栅极应激源。
提供了一种用于鳍式场效晶体管(FinFET)器件的栅极应激源的形成方法。该方法包括在栅极层的第一部分上形成底面，栅极层设置在浅沟槽隔离(STI)区域上；在栅极层的第二部分上形成第一应激源侧壁，栅极层的第二部分设置在鳍的侧壁上；以及在栅极层的第三部分上形成第二应激源侧壁，栅极层的第三部分设置在与鳍间隔开的结构的侧壁上，第一应激源侧壁与第二应激源侧壁没有超过鳍的高度。
虽然本公开内容提供了说明性的实施例，但是该描述不旨在理解为限制意义。参考描述，说明性实施例和其它实施例的各种修改和组合对于本领域的技术人员是显而易见。因此所附权利要求包括任何这种修改或实施例。

Claims (10)

1.一种用于鳍式场效晶体管(FinFET)器件的栅极应激源，包括：
底面，形成在栅极层的第一部分上，所述栅极层设置在浅沟槽隔离(STI)区域上方；
第一应激源侧壁，形成在所述栅极层的第二部分上，所述栅极层的第二部分设置在鳍的侧壁上；以及
第二应激源侧壁，形成在所述栅极层的第三部分上，所述栅极层的第三部分设置在与所述鳍间隔开的结构的结构侧壁上，所述第一应激源侧壁与所述第二应激源侧壁没有超过所述鳍的高度。
2.根据权利要求1所述的栅极应激源，其中，所述底面与所述第一应激源侧壁和所述第二应激源侧壁由金属形成。
3.根据权利要求1所述的栅极应激源，其中，所述底面、所述第一应激源侧壁和第二应激源侧壁中的一个或多个被配置为对所述鳍的晶体管沟道施加应力。
4.根据权利要求1所述的栅极应激源，其中，所述底面、所述第一应激源侧壁和所述第二应激源侧壁中的一个或多个被配置成对所述鳍的晶体管沟道提供拉伸应力。
5.根据权利要求1所述的栅极应激源，其中，所述底面、所述第一应激源侧壁和所述第二应激源侧壁中的一个或多个被配置成对所述鳍的晶体管沟道提供压缩应力。
6.根据权利要求1所述的栅极应激源，其中，所述结构是第二鳍。
7.根据权利要求1所述的栅极应激源，其中，所述结构是层间介电层。
8.一种鳍式场效晶体管(FinFET)器件，包括：
鳍，提供晶体管沟道；
结构，通过浅沟槽隔离(STI)区域与所述鳍间隔开；
栅极层，形成在所述结构、所述STI区域、所述鳍上方；以及
栅极应激源，形成在所述栅极层中设置在所述结构与所述鳍之间的所述STI区域上的第一部分上方，并且形成在所述栅极层中设置在所述鳍的侧壁与所述结构的侧壁上的第二部分上方。
9.根据权利要求8所述的器件，其中，所述栅极应激源的侧壁没有超过所述鳍的高度。
10.一种形成用于鳍式场效晶体管(FinFET)器件的栅极应激源的方法，包括：
在栅极层的第一部分上形成底面，所述栅极层设置在浅沟槽隔离(STI)区域上方；
在所述栅极层的第二部分上形成第一应激源侧壁，所述栅极层的第二部分设置在鳍的侧壁上；以及
在所述栅极层的第三部分上形成第二应激源侧壁，所述栅极层的第三部分设置在与所述鳍间隔开的结构的侧壁上，所述第一应激源侧壁与所述第二应激源侧壁没有超过所述鳍的高度。
CN201310007898.0A 2012-03-20 2013-01-09 具有金属栅极应激源的finfet Expired - Fee Related CN103325832B (zh)

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US8872284B2 (en) 2014-10-28
US20150056774A1 (en) 2015-02-26
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