FR3093590B1 - Procédé de fabrication d’un élément capacitif, et circuit intégré correspondant. - Google Patents
Procédé de fabrication d’un élément capacitif, et circuit intégré correspondant. Download PDFInfo
- Publication number
- FR3093590B1 FR3093590B1 FR1902278A FR1902278A FR3093590B1 FR 3093590 B1 FR3093590 B1 FR 3093590B1 FR 1902278 A FR1902278 A FR 1902278A FR 1902278 A FR1902278 A FR 1902278A FR 3093590 B1 FR3093590 B1 FR 3093590B1
- Authority
- FR
- France
- Prior art keywords
- capacitive element
- integrated circuit
- conductive region
- manufacturing
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 6
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/87—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/86—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions
- H01L28/88—Electrodes with an enlarged surface, e.g. formed by texturisation having horizontal extensions made by patterning layers, e.g. by etching conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Le circuit intégré (CI) comprend un substrat semiconducteur (SUB), et un élément capacitif (CTR) situé dans une région active (ACT) du substrat (SUB) et sur une face avant (FA) du substrat (SUB). L’élément capacitif (CTR) comporte une première électrode (E1) et une deuxième électrode (E2). La première électrode (E1) comporte une première région conductrice (P1) et la région active (ACT), la deuxième électrode (E2) comporte une deuxième région conductrice (P2) et une région monolithique conductrice (P0) ayant une partie recouvrant une surface de ladite face avant (FA) et au moins une partie s’étendant dans la région active (ACT) perpendiculairement à ladite face avant (FA), la première région conductrice (P1) étant située entre la région monolithique conductrice (P0) et la deuxième région conductrice (P2). Figure pour l’abrégé : Fig 8
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1902278A FR3093590B1 (fr) | 2019-03-06 | 2019-03-06 | Procédé de fabrication d’un élément capacitif, et circuit intégré correspondant. |
US16/803,226 US11164875B2 (en) | 2019-03-06 | 2020-02-27 | Method for manufacturing a capacitive element having electrical coupling the first electrode to the active region |
US17/493,226 US11637106B2 (en) | 2019-03-06 | 2021-10-04 | Capacitive element comprising a monolithic conductive region having one part covering a front surface of a substrate and at least one part extending into an active region perpendicularly to the front surface |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1902278A FR3093590B1 (fr) | 2019-03-06 | 2019-03-06 | Procédé de fabrication d’un élément capacitif, et circuit intégré correspondant. |
FR1902278 | 2019-03-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3093590A1 FR3093590A1 (fr) | 2020-09-11 |
FR3093590B1 true FR3093590B1 (fr) | 2023-08-25 |
Family
ID=68281483
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1902278A Active FR3093590B1 (fr) | 2019-03-06 | 2019-03-06 | Procédé de fabrication d’un élément capacitif, et circuit intégré correspondant. |
Country Status (2)
Country | Link |
---|---|
US (2) | US11164875B2 (fr) |
FR (1) | FR3093590B1 (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3108206B1 (fr) * | 2020-03-16 | 2022-04-01 | St Microelectronics Rousset | Elément capacitif intégré et procédé de fabrication correspondant |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7239005B2 (en) * | 2003-07-18 | 2007-07-03 | Yamaha Corporation | Semiconductor device with bypass capacitor |
US9178080B2 (en) * | 2012-11-26 | 2015-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Deep trench structure for high density capacitor |
FR3070535A1 (fr) * | 2017-08-28 | 2019-03-01 | Stmicroelectronics (Crolles 2) Sas | Circuit integre avec element capacitif a structure verticale, et son procede de fabrication |
US11201205B2 (en) * | 2019-07-31 | 2021-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect layout for semiconductor device |
-
2019
- 2019-03-06 FR FR1902278A patent/FR3093590B1/fr active Active
-
2020
- 2020-02-27 US US16/803,226 patent/US11164875B2/en active Active
-
2021
- 2021-10-04 US US17/493,226 patent/US11637106B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US11164875B2 (en) | 2021-11-02 |
US11637106B2 (en) | 2023-04-25 |
US20200286896A1 (en) | 2020-09-10 |
FR3093590A1 (fr) | 2020-09-11 |
US20220028863A1 (en) | 2022-01-27 |
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Effective date: 20200911 |
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