WO2021232891A1 - 一种晶圆级芯片结构、多芯片堆叠互连结构及制备方法 - Google Patents

一种晶圆级芯片结构、多芯片堆叠互连结构及制备方法 Download PDF

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WO2021232891A1
WO2021232891A1 PCT/CN2021/079317 CN2021079317W WO2021232891A1 WO 2021232891 A1 WO2021232891 A1 WO 2021232891A1 CN 2021079317 W CN2021079317 W CN 2021079317W WO 2021232891 A1 WO2021232891 A1 WO 2021232891A1
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wafer
chip
chip structure
level
layer
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PCT/CN2021/079317
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English (en)
French (fr)
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曹立强
严阳阳
孙鹏
陈天放
戴风伟
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上海先方半导体有限公司
华进半导体封装先导技术研发中心有限公司
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Priority to US17/908,118 priority Critical patent/US20230091513A1/en
Publication of WO2021232891A1 publication Critical patent/WO2021232891A1/zh

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    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
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    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/384—Bump effects
    • H01L2924/3841—Solder bridging

Definitions

  • This application relates to the technical field of semiconductor packaging, and in particular to a wafer-level chip structure, a multi-chip stack interconnection structure and a preparation method.
  • the electrical signal transmission path between the upper and lower stacked chip layers is: the RDL of the upper chip layer, the upper chip layer Buried vertical interconnection (TSV), bonding micro bumps between the upper and lower chips, UBM of the lower chip, buried vertical interconnect (TSV) of the lower chip, and RDL of the lower chip layer.
  • TSV Thin Silicon Via
  • the impedance of the transmission line is constantly changing, and the change and fluctuation of the impedance will have a significant impact on the signal transmission quality, such as the reduction of the eye pattern opening of the high bit rate signal, the increase of transmission noise, and even the signal Distortion etc.
  • the HBM module structure implemented by vertical stacking of multi-layer DRAM has increasingly become the mainstream solution.
  • the TSV outcropping area on the back of the DRAM stack layer is directly interconnected with UBM (Under bumping metallization).
  • UBM Under bumping metallization
  • the present application provides a wafer-level chip structure, a multi-chip stack interconnection structure, and a manufacturing method, which overcomes the continuous changes in signal transmission path impedance during 3D chip packaging or wafer-level packaging in the prior art. Lead to defects that have a significant impact on the quality of signal transmission.
  • the present application provides a wafer-level chip structure, including: a through silicon via through the wafer, the first surface of which includes an active area, a multilayer redistribution line layer, and bumps, and the second surface of which includes : Insulating dielectric layer, and the frustum transition structure connected with the through silicon via.
  • the diameter of the opening at one end of the frustum transition structure is determined according to the size of the through silicon hole connected to it, and the diameter of the opening at the other end is determined according to the size of the bonding bump.
  • an embodiment of the present application provides a wafer-level multi-chip stack interconnection structure, including: a chip bond body, a substrate, and lead-out terminals, the chip bond body is transferred to the first surface of the substrate, and the lead-out terminal Formed on the second surface of the substrate, wherein:
  • the chip bonding body includes a plurality of single wafer-level chips stacked and arranged, and the plurality of single wafer-level chips are directly connected by a bonding layer.
  • the single wafer-level chip includes: a first chip structure and a first chip structure. Two chip structures and at least one third chip structure, the first chip structure and the second chip structure are respectively located at two ends of the chip bonding body, the at least one third chip structure is located in the first chip structure and the second chip structure Between chip structures;
  • the third chip structure is the wafer-level chip structure described in the first aspect.
  • the first chip structure includes a silicon through connection structure that does not penetrate the wafer completely, the first surface of which includes an active area, a multilayer redistribution line layer, and bumps, and the second surface is Wafer surface
  • the second chip structure includes: through-silicon vias through the wafer, the first surface of which includes: active regions, multilayer redistribution line layers and bumps, and the second surface of which includes a plurality of through-silicon vias. Wafer surface.
  • the first surface of the first chip structure, the second chip structure, and the third chip structure all include: a non-conductive adhesive film layer covering the bumps, and the thickness of the non-conductive adhesive film layer is greater than The height of the bump;
  • the bonding layer includes: bump connections between single wafer-level chips and a non-conductive adhesive film layer covering the bump connections.
  • the wafer-level multi-chip stack interconnection structure further includes:
  • the plastic encapsulation layer is based on the substrate-level encapsulation of the chip bond.
  • an embodiment of the present application provides a method for manufacturing a wafer-level chip structure, including the following steps:
  • an active area On the first surface of the wafer, an active area, a through silicon via, a multi-layer redistribution line layer and a bump are sequentially prepared;
  • the barrier layer, the seed layer and the under-bump metallization layer are prepared in sequence to form the wafer-level chip structure.
  • an embodiment of the present application provides a method for fabricating a wafer-level multi-chip stacked interconnection structure, which includes the following steps:
  • an active area On the first surface of the wafer, an active area, a through silicon via, a multi-layer redistribution line layer and a bump are sequentially prepared to form a first chip structure;
  • the second surface of the wafer is thinned and polished until all the through silicon vias are exposed to form the second chip structure;
  • a third chip structure is formed
  • Leading terminals are prepared on the second surface of the substrate to form a wafer-level multi-chip stack interconnection structure.
  • the first chip structure and the second chip structure when preparing the first chip structure and the second chip structure, after the steps of sequentially preparing active regions, through silicon vias, multi-layer redistribution lines and bumps on the first surface of the wafer, further Including: preparing a non-conductive adhesive film layer to cover the bumps, the thickness of the non-conductive adhesive film layer being greater than the height of the bumps;
  • the method further includes: preparing a non-conductive adhesive film layer to cover the bumps, and the thickness of the non-conductive adhesive film layer is greater than the height of the bumps.
  • the method further includes: preparing a plastic encapsulation layer, and comparing the second chip structure, the at least one first chip structure The three-chip structure and the first chip structure are subjected to substrate-level plastic packaging based on the chip bonding body formed by bump connection bonding and stacking.
  • the method further includes: cutting the wafer-level multi-chip stack interconnection structure to form a single wafer-level chip structure.
  • a frustum-type impedance transition structure is introduced between the TSV outcropping area on the back of the wafer and the UBM, so that impedance matching between TSV and UBM is achieved, and the impedance mutation caused by sudden changes is improved.
  • the number of photomasks is not increased, but only one step of photolithography and one step of reactive ion etching are added on the basis of the original process. The technological process is not complicated.
  • the wafer-level multi-chip stacking interconnection structure and preparation method provided by this application, stack and bond single wafer-level chips of different structures, and introduce the frustum-type impedance transition structure into the transition area of different chip bonding to improve
  • the introduction of a non-conductive adhesive film layer in the bonding layer can improve the bridging problem between different bumps during stacking and bonding of single wafer-level chips.
  • FIG. 1 is a schematic diagram of a specific example of a wafer-level chip structure provided by an embodiment of the application;
  • FIG. 2 is a flowchart of a specific example of a method for manufacturing a wafer-level chip structure provided by an embodiment of the application;
  • FIG. 3 is a schematic structural diagram of sequentially preparing active regions, through silicon vias, multilayer redistribution line layers, and bumps on the first surface of a wafer according to an embodiment of the application;
  • FIG. 4 is a schematic diagram of a structure in which the second surface of the wafer is thinned and polished until all the through silicon vias are exposed according to an embodiment of the application;
  • FIG. 5 is a schematic structural diagram of a through-silicon via provided by an embodiment of the application that is convex relative to the second surface of the wafer as a whole;
  • FIG. 6 is a schematic diagram of the second surface of the wafer provided by the embodiment of the application to realize the deposition of the insulating dielectric layer and the preparation of the etching mask layer and the etching of the truncated cone-shaped blind hole;
  • FIG. 7 is a schematic diagram of a wafer-level multi-chip stacked interconnection structure provided by an embodiment of the application.
  • FIG. 8 is a schematic diagram of forming a non-conductive adhesive film layer on the first surface of the third chip structure according to an embodiment of the application;
  • FIG. 9 is a schematic diagram of a bonding layer provided by an embodiment of the application.
  • Figure 10 is a schematic diagram of a plastic encapsulation layer provided by an embodiment of the application.
  • FIG. 11 is a flowchart of a specific example of a method for fabricating a wafer-level multi-chip stacked interconnection structure provided by an embodiment of the application;
  • FIG. 12 is a flowchart of another specific example of a manufacturing method of a wafer-level multi-chip stacked interconnect structure provided by an embodiment of the application;
  • FIG. 13 is a flowchart of another specific example of a method for fabricating a wafer-level multi-chip stacked interconnection structure provided by an embodiment of the application.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection. Connected or integrally connected; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of the two components, it can be a wireless connection, or it can be a wired connection connect.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal connection of the two components, it can be a wireless connection, or it can be a wired connection connect.
  • the embodiment of the present application provides a wafer-level chip structure, as shown in FIG. 1, comprising: a through silicon via 1 penetrating the wafer, the first surface of which includes: an active area 2, a multilayer redistribution line layer 3, and a convex Point 4, the second surface includes: an insulating dielectric layer 5, and a truncated cone transition structure 6 connected with a through silicon hole.
  • the material filled in the TSV 1 can be copper
  • the bump 4 can be a tin ball
  • the diameter of the opening at one end of the frustum transition structure 6 is determined according to the size of the TSV connected to it
  • the diameter of the opening at the other end is according to The bond bump size is determined.
  • the frustum transition structure is realized based on the inductively coupled plasma etching process of SF 6 /CF 4 /CHF 3 /O 2 /Ar and other process gases, and the height is about 2-6um (the SiO 2 deposition thickness and film stress limit: the greater the thickness, the more the crystal The greater the warpage of the circle, the greater the risk of film peeling), the size of the opening under the frustum and the TSV connected to it are the same or slightly larger (the lithography engraving accuracy and the frustum opening diameter/slope limit), the transition of the frustum
  • the diameter of the upper opening of the structure is determined according to the size of the bonding bump (in fact, the opening on the frustum is the same as the diameter of the bonding UBM, and the bonding UBM and the bonding micro bumps are paired, generally designed to have the same diameter, but also can be designed The UBM diameter is slightly larger), the slope of the frustum can be optimized by adjusting the SiO 2 RIE
  • the embodiment of the application also provides a method for preparing the above-mentioned wafer-level chip structure, as shown in FIG. 2, including:
  • Step 11 Prepare active regions, through silicon vias, multi-layer redistribution line layers and bumps in sequence on the first surface of the wafer; the preparation process of this step is the existing mature preparation technology, which is not limited here. The structure is shown in Figure 3.
  • Step 12 Perform thinning and polishing on the second surface of the wafer until all TSVs are exposed; the preparation process of this step is the existing mature preparation technology, which is not limited here, and the formed structure is shown in Figure 4 .
  • Step 13 Use a deep reactive ion etching process to achieve maskless etching on the second surface of the wafer, so that the through-silicon vias are raised relative to the second surface of the wafer as a whole; this step uses a deep reactive ion etching process to The back surface of the wafer is etched without a mask, that is, "etch back", so that the TSV is raised relative to the back of the wafer as a whole, and the resulting structure is shown in Figure 5.
  • Step 14 Realize the deposition of the insulating dielectric layer on the second surface of the wafer, and prepare it by etching the mask layer and the frustum-shaped blind hole etching; this step uses the low-temperature SiOx deposition process to realize the SiOx dielectric layer deposition on the back of the wafer , And sequentially realize the preparation of the etching mask layer and the "frustum" type blind hole etching through the photolithography process, and the formed structure is shown in FIG. 6.
  • Step 15 On the second surface of the wafer, prepare the barrier layer, the seed layer and the under-bump metallization layer in sequence to form the wafer-level chip structure.
  • barrier/seed layer (barrier layer, seed layer) deposition is completed in sequence on the back of the wafer, and the UBM electroplating mask is prepared by the photolithography process to realize the UBM electroplating preparation.
  • the electroplating mask layer is removed by wet stripping, and then, by wet etching, the seed layer/barrier layer is removed sequentially.
  • ENIG surface treatment is performed on the UBM surface. After ENIG surface treatment, Ni (typically 2-3um in thickness) and Au (typically 50nm in thickness) are deposited sequentially on the UBM copper. The function of the Ni layer is to prevent the copper wire or copper pad metal copper and metal tin from being reflowed when the solder ball is reflowed. The formation of alloys leads to reliability failure problems.
  • a frustum-shaped impedance transition structure is introduced between the TSV outcropping area on the back of the wafer and the UBM, so that impedance matching between TSV and UBM is achieved, and the impedance mutation caused by sudden changes is improved.
  • the number of photomasks is not increased, but only one step of photolithography and one step of reactive ion etching are added on the basis of the original process. The technological process is not complicated.
  • the embodiment of the present application provides a wafer-level multi-chip stacked interconnection structure, as shown in FIG. 7, comprising: a chip bond body 7, a substrate 8 and lead-out terminals 9, the chip bond body 7 being transferred to the substrate 8 On the first surface of the substrate, the lead-out terminal 9 is formed on the second surface of the substrate, wherein
  • the chip bonding body 7 includes a plurality of single wafer-level chips arranged in a stack, and the plurality of single wafer-level chips are directly connected by a bonding layer, and the single wafer-level chip includes: a first chip structure 11, A second chip structure 12 and at least one third chip structure 13, the first chip structure 11 and the second chip structure 12 are respectively located at two ends of the chip bond body 7, the at least one third chip structure 13, It is located between the first chip structure 11 and the second chip structure 12; the third chip structure 13 is the wafer-level chip structure described in Embodiment 1. As shown in FIG. 7, the chip bonding body 7 includes the third chip structure 13 as an example, but it is not limited to this.
  • the first chip structure 11, as shown in FIG. 3, includes: a through silicon via that does not completely penetrate the wafer, and its first surface includes: an active area, a multilayer redistribution line layer, and bumps,
  • the second surface is the wafer surface.
  • the second chip structure 12 includes a through silicon via through the wafer, and the first surface of the second chip structure 12 includes an active area, a multilayer redistribution line layer, and bumps.
  • the second surface is a wafer surface containing a plurality of through silicon vias.
  • the first surface of the first chip structure, the second chip structure, and the third chip structure all include: a non-conductive adhesive film layer 10 covering the bumps, and the thickness of the non-conductive adhesive film layer Greater than the height of the bump.
  • a non-conductive adhesive film Non-Conductive-Film, NCF
  • Hitachi-AK400 Series is formed on the first surface of the third chip structure.
  • the bonding layer 111 includes: bump connections between single wafer-level chips and a non-conductive adhesive film layer covering the bump connections.
  • a non-conductive adhesive film layer By providing a non-conductive adhesive film layer, the bridging problem between different bumps during stack bonding of single wafer-level chips can be improved.
  • it further includes: a plastic encapsulation layer 112, which covers the chip bonding body based on the substrate level.
  • the stacked multi-layer chips are plastic-encapsulated through the plastic encapsulation layer to realize the protection of the chips.
  • the embodiment of the present application also provides a method for preparing the above-mentioned wafer-level multi-chip stacked interconnection structure, as shown in FIG. 11, including:
  • Step S21 preparing active regions, through silicon vias, multi-layer redistribution line layers and bumps in sequence on the first surface of the wafer to form a first chip structure.
  • Step S22 On the basis of the first chip structure, the second surface of the wafer is thinned and polished until all the through silicon vias are exposed to form the second chip structure.
  • Step S23 According to the method for preparing a wafer-level chip structure described in Embodiment 1, a third chip structure is formed. Specifically, on the basis of the second chip structure, a deep reactive ion etching process is used to achieve maskless etching on the second surface of the wafer, so that the through-silicon vias are raised relative to the second surface of the wafer as a whole; The second surface of the circle realizes the deposition of the insulating dielectric layer, and is prepared by etching the mask layer and the frustum-shaped blind hole etching; on the second surface of the wafer, the barrier layer, the seed layer and the under-bump metallization layer are prepared in sequence , Form the third chip structure.
  • Step S24 sequentially stack the second chip structure, the at least one third chip structure, and the first chip structure on the first surface of the substrate based on bump connection bonding.
  • a frustum-type impedance transition structure is introduced between the TSV outcropping area on the back of the wafer of the third chip structure and the UBM to achieve impedance matching between TSV and UBM, and the transition area of each chip bonding is introduced into the frustum-shaped transition area.
  • the impedance transition structure improves the signal distortion caused by the sudden change in impedance.
  • Step S25 preparing lead terminals on the second surface of the substrate to form a wafer-level multi-chip stack interconnection structure.
  • the lead-out terminals in this embodiment may be solder balls, which are used to lead out the signals of the interconnection structure.
  • the method when preparing the first chip structure and the second chip structure, an active area, a through silicon via, a multi-layer redistribution line layer, and a bump are sequentially prepared on the first surface of the wafer.
  • the method further includes: preparing a non-conductive adhesive film layer to cover the bumps, and the thickness of the non-conductive adhesive film layer is greater than the height of the bumps.
  • the method further includes: preparing a non-conductive adhesive film layer to cover the bumps, and the thickness of the non-conductive adhesive film layer is greater than the height of the bumps.
  • Each chip is heated and pressurized during bonding, after the non-conductive adhesive film layer is melted into liquid, the chips are electrically connected through bumps to prevent the bump bonding from bridging caused by metal splash, making the bond The combined effect is better.
  • the method further includes:
  • Step S241 Prepare a plastic encapsulation layer, and perform substrate-level plastic encapsulation on the second chip structure, the at least one third chip structure, and the chip bonding body formed by the bump connection bonding and stacking of the first chip structure to form the structure shown in FIG. 10.
  • the method further includes:
  • Step S26 cutting the wafer-level multi-chip stack interconnection structure to form a single wafer-level chip structure.
  • the wafer-level multi-chip stacked interconnection structure and preparation method provided in the present application, stack and bond single wafer-level chips of different structures, and introduce the frustum-type impedance transition structure into the transition area of different chip bonding, which improves the factor
  • the signal distortion problem caused by the sudden change in impedance, the introduction of a non-conductive adhesive film layer in the bonding layer can avoid the bridging problem between different bumps when the single wafer-level chip is stacked and bonded.

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Abstract

本申请公开了一种晶圆级芯片结构、多芯片堆叠互连结构及制备方法，其中晶圆级芯片结构，包括：贯穿晶圆的硅通孔，其第一表面包括：有源区、多层再分布线层以及凸点，其第二表面包括：绝缘介质层，以及与硅通孔相连接的锥台过渡结构。本申请实施例在晶圆背面TSV露头区域与UBM之间引入锥台型阻抗过渡结构，使TSV与UBM之间实现阻抗匹配，改善了因阻抗突变引起的信号畸变问题，和传统方案相比，为了实现本方案的锥台型过渡结构，并未增加光罩数量，而仅在原有工艺基础上，增加一步光刻工艺以及一步反应离子刻蚀工艺，工艺流程并不复杂。

Description

一种晶圆级芯片结构、多芯片堆叠互连结构及制备方法 技术领域
本申请涉及半导体封装技术领域，具体涉及一种晶圆级芯片结构、多芯片堆叠互连结构及制备方法。
背景技术
近年来，在利用TSV(Through Silicon Via，硅通孔)以及微凸点进行多层芯片3D堆叠应用中，上下堆叠芯片层之间的电信号传输路径为：上层芯片层的RDL、上层芯片层内埋垂直互连(TSV)、上下层芯片间键合微凸点、下层芯片UBM、下层芯片内埋垂直互连(TSV)和下层芯片层的RDL。在信号传输路径上，传输线路阻抗在发生不断变化，而阻抗的变化和波动，将会对信号传输质量产生显著影响，如高比特率信号眼图张开幅度降低、传输噪声增大，甚至信号畸变等。
目前，随着高性能计算、AI、5G等应用对存储带宽的要求越来越高，采用多层DRAM垂直堆叠实现的HBM模组结构，越来越成为主流解决方案。但是，在目前该领域主流供应商提供的解决方案中，均采用DRAM堆叠层的背面TSV露头区域直接和UBM(Under bumping metallization，凸点下金属化层)互连的形式，考虑到TSV直径约6um，而UBM直径约20～30um，两者之间直接互连，阻抗呈现出明显的突变。另外，随着TSV直径越来越小，而UBM受限于共晶凸点直径和节距(相邻凸点中心对中心之间的距离)缩小的困难，两者之间的阻抗失配将越来越大，将显著影响高比特率信号传输质量。
申请内容
因此，本申请提供一种晶圆级芯片结构、多芯片堆叠互连结构及制备方法，克服现有技术中的在3D芯片封装或晶圆级封装时，信号在传输路径阻抗在发生不断变化，导致对信号传输质量产生显著影响的缺陷。
第一方面，本申请提供一种晶圆级芯片结构，包括：贯穿晶圆的硅通孔，其第一表面包括：有源区、多层再分布线层以及凸点，其第二表面包 括：绝缘介质层，以及与硅通孔相连接的锥台过渡结构。
在一实施例中，所述锥台过渡结构一端开口直径根据与之相连的硅通孔尺寸确定，另一端开口直径根据键合凸点尺寸确定。
第二方面，本申请实施例提供一种晶圆级多芯片堆叠互连结构，包括：芯片键合体、基板及引出端子，所述芯片键合体转接于所述基板的第一表面，引出端子形成于所述基板的第二表面，其中，
芯片键合体，包括堆叠设置的多个单体晶圆级芯片，多个单体晶圆级芯片直接通过键合层连接，所述单体晶圆级芯片包括：一个第一芯片结构、一个第二芯片结构及至少一个第三芯片结构，所述第一芯片结构和第二芯片结构分别位于所述芯片键合体的两端，所述至少一个第三芯片结构，位于第一芯片结构和第二芯片结构之间；
所述第三芯片结构为第一方面所述的晶圆级芯片结构。
在一实施例中，所述第一芯片结构，包括：未完全贯穿晶圆的硅通连接结构，其第一表面包括：有源区、多层再分布线层以及凸点，第二表面为晶圆面；
所述第二芯片结构，包括：贯穿晶圆的硅通孔，其第一表面包括：有源区、多层再分布线层以及凸点，其第二表面为包含多个硅通孔连接的晶圆面。
在一实施例中，第一芯片结构、第二芯片结构及第三芯片结构的第一表面均包括：非导电胶膜层，包覆所述凸点，所述非导电胶膜层的厚度大于所述凸点的高度；
所述键合层包括：单体晶圆级芯片之间的凸点连接及包覆所述凸点连接的非导电胶膜层。
在一实施例中，所述晶圆级多芯片堆叠互连结构还包括：
塑封层，基于基板级的包覆所述芯片键合体。
第三方面，本申请实施例提供一种晶圆级芯片结构的制备方法，包括如下步骤：
在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层及凸点；
对晶圆第二表面进行减薄抛光处理，直至所有硅通孔均露出；
利用深反应离子刻蚀工艺，在晶圆第二表面实现无掩膜刻蚀，使硅通孔相对于晶圆第二表面整体凸起；
在晶圆第二表面实现绝缘介质层沉积，并通过刻蚀掩膜层制备以及锥台型盲孔刻蚀；
在晶圆第二表面，依次进行阻挡层、种子层及凸点下金属化层的制备，形成所述晶圆级芯片结构。
第四方面，本申请实施例提供一种晶圆级多芯片堆叠互连结构的制备方法，包括如下步骤：
在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层及凸点，形成第一芯片结构；
在第一芯片结构的基础上，对晶圆第二表面进行减薄抛光处理，直至所有硅通孔均露出，形成第二芯片结构；
根据第三方面所述的晶圆级芯片结构的制备方法，形成第三芯片结构；
在基板第一表面依次将第二芯片结构、至少一个第三芯片结构、第一芯片结构基于凸点连接键合堆叠；
在基板第二表面制备引出端子，形成晶圆级多芯片堆叠互连结构。
在一实施例中，在制备第一芯片结构及第二芯片结构时，在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层及凸点的步骤之后，还包括：制备非导电胶膜层，包覆所述凸点，所述非导电胶膜层的厚度大于所述凸点的高度；
形成第三芯片结构的步骤之后，还包括：制备非导电胶膜层，包覆所述凸点，所述非导电胶膜层的厚度大于所述凸点的高度。
在一实施例中，将第二芯片结构、至少一个第三芯片结构、第一芯片结构基于凸点连接键合堆叠的步骤之后，还包括：制备塑封层，对第二芯片结构、至少一个第三芯片结构、第一芯片结构基于凸点连接键合堆叠形成的芯片键合体进行基板级塑封。
在一实施例中，所述在基板第二表面制备引出端子的步骤之后，还包括：对晶圆级多芯片堆叠互连结构进行切割，形成单颗晶圆级芯片结构。
1、本申请提供的晶圆级芯片结构及制备方法，在晶圆背面TSV露头区 域与UBM之间引入锥台型阻抗过渡结构，使TSV与UBM之间实现阻抗匹配，改善了因阻抗突变引起的信号畸变问题，和传统方案相比，为了实现本方案的锥台型过渡结构，并未增加光罩数量，而仅在原有工艺基础上，增加一步光刻工艺以及一步反应离子刻蚀工艺，工艺流程并不复杂。
2、本申请提供的晶圆级多芯片堆叠互连结构及制备方法，将不同结构的单体晶圆级芯片进行堆叠键合，不同芯片键合的过渡区域引入锥台型阻抗过渡结构，改善了因阻抗突变引起的信号畸变问题，键合层引入了非导电胶膜层可以改善单体晶圆级芯片在堆叠键合时不同凸点之间的桥接问题。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的晶圆级芯片结构的一个具体示例的示意图；
图2为本申请实施例提供的晶圆级芯片结构的制备方法的一个具体示例的流程图；
图3为本申请实施例提供的在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层及凸点的结构示意图；
图4为本申请实施例提供的对晶圆第二表面进行减薄抛光处理，直至所有硅通孔均露出的结构示意图；
图5为本申请实施例提供的硅通孔相对于晶圆第二表面整体凸起的结构示意图；
图6为本申请实施例提供的晶圆第二表面实现绝缘介质层沉积，并通过刻蚀掩膜层制备以及锥台型盲孔刻蚀的示意图；
图7为本申请实施例提供的晶圆级多芯片堆叠互连结构的示意图；
图8为本申请实施例提供的在第三芯片结构的第一表面形成非导电胶膜层的示意图；
图9为本申请实施例提供的键合层的示意图；
图10为本申请实施例提供的塑封层的示意图；
图11为本申请实施例提供的晶圆级多芯片堆叠互连结构的制备方法一个具体示例的流程图；
图12为本申请实施例提供的晶圆级多芯片堆叠互连结构的制备方法另一个具体示例的流程图；
图13为本申请实施例提供的晶圆级多芯片堆叠互连结构的制备方法另一个具体示例的流程图。
具体实施方式
下面将结合附图对本申请的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，还可以是两个元件内部的连通，可以是无线连接，也可以是有线连接。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
此外，下面所描述的本申请不同实施方式中所涉及的技术特征只要彼此之间未构成冲突就可以相互结合。
实施例1
本申请实施例提供一种晶圆级芯片结构，如图1所示，包括：贯穿晶圆的硅通孔1，其第一表面包括：有源区2、多层再分布线层3以及凸点4，其第二表面包括：绝缘介质层5，以及与硅通孔相连接的锥台过渡结构6。
本申请实施例中，硅通孔1内填充的材质可以为铜，凸点4可以为锡球，锥台过渡结构6一端开口直径根据与之相连的硅通孔尺寸确定，另一端开口直径根据键合凸点尺寸确定。锥台过渡结构基于SF 6/CF 4/CHF 3/O 2/Ar等工艺气体的电感耦合等离子刻蚀工艺实现，高度约2～6um(SiO 2沉积厚度和薄膜应力限制：厚度越大，晶圆翘曲越大，薄膜peeling的风险越大)，锥 台下开口和与之相连的TSV尺寸相同或略有增大(光刻套刻精度与锥台开口直径/坡度限制)，锥台过渡结构的上开口直径则根据键合凸点尺寸确定(实际上，锥台上开口与键合UBM直径一致，而键合UBM和键合微凸点配对使用，一般设计为同一直径，也可设计为UBM直径略大)，锥台坡度则可以通过调整SiO 2RIE刻蚀工艺参数进行优化，调控范围较大。锥台过渡结构刻蚀完成后，通过电镀工艺实现锥台结构内完全铜填充，工艺成熟，难度较小。
本申请实施例还提供上述晶圆级芯片结构的制备方法，如图2所示，包括：
步骤11:在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层及凸点；该步骤的制备过程为现有的成熟制备技术，在此不做限制，形成的结构如图3所示。
步骤12:对晶圆第二表面进行减薄抛光处理，直至所有硅通孔均露出；该步骤的制备过程为现有的成熟制备技术，在此不做限制，形成的结构如图4所示。
步骤13:利用深反应离子刻蚀工艺，在晶圆第二表面实现无掩膜刻蚀，使硅通孔相对于晶圆第二表面整体凸起；该步骤利用深反应离子刻蚀工艺，在晶圆背面实现无掩膜刻蚀，即“回刻”，使TSV相对于晶圆背面整体凸起，形成的结构如图5所示。
步骤14:在晶圆第二表面实现绝缘介质层沉积，并通过刻蚀掩膜层制备以及锥台型盲孔刻蚀；该步骤利用低温SiOx沉积工艺，在晶圆背面实现SiOx绝缘介质层沉积，并顺序通过光刻工艺实现刻蚀掩膜层制备以及“锥台”型盲孔刻蚀，形成的结构如图6所示。
步骤15:在晶圆第二表面，依次进行阻挡层、种子层及凸点下金属化层的制备，形成所述晶圆级芯片结构。该步骤在晶圆背面，顺序完成Barrier/seed layer(阻挡层、种子层)沉积，利用光刻工艺制备UBM电镀掩膜后，实现UBM电镀制备。随后，利用湿法去胶实现电镀掩膜层去除，再之后，利用湿法腐蚀，顺序实现种子层/阻挡层去除。最后，对UBM表面进行ENIG表面处理。ENIG表面处理后，UBM铜上顺序沉积了Ni(厚度一般2-3um)和Au(厚度一般50nm)，Ni层的作用是防止锡球回流时将铜导线或者铜焊盘的金属铜与金属锡形成合金，导致可靠性失效问题。
本申请实施例提供的晶圆级芯片结构及制备方法，在晶圆背面TSV露 头区域与UBM之间引入锥台型阻抗过渡结构，使TSV与UBM之间实现阻抗匹配，改善了因阻抗突变引起的信号畸变问题，和传统方案相比，为了实现本方案的锥台型过渡结构，并未增加光罩数量，而仅在原有工艺基础上，增加一步光刻工艺以及一步反应离子刻蚀工艺，工艺流程并不复杂。
实施例2
本申请实施例提供一种晶圆级多芯片堆叠互连结构，如图7所示，包括：芯片键合体7、基板8及引出端子9，所述芯片键合体7转接于所述基板8的第一表面，引出端子9形成于所述基板的第二表面，其中，
芯片键合体7，包括堆叠设置的多个单体晶圆级芯片，多个单体晶圆级芯片直接通过键合层连接，所述单体晶圆级芯片包括：一个第一芯片结构11、一个第二芯片结构12及至少一个第三芯片结构13，所述第一芯片结构11和第二芯片结构12分别位于所述芯片键合体7的两端，所述至少一个第三芯片结构13，位于第一芯片结构11和第二芯片结构12之间；其中的第三芯片结构13为实施例1中所述的晶圆级芯片结构。如图7的是以芯片键合体7包含第三芯片结构13为例，但不以此为限。
在一实施例中，第一芯片结构11，如图3所示，包括：未完全贯穿晶圆的硅通孔，其第一表面包括：有源区、多层再分布线层以及凸点，第二表面为晶圆面。
在一实施例中，第二芯片结构12，如图4所示，包括：贯穿晶圆的硅通孔，其第一表面包括：有源区、多层再分布线层以及凸点，其第二表面为包含多个硅通孔的晶圆面。
在一实施例中，第一芯片结构、第二芯片结构及第三芯片结构的第一表面均包括：非导电胶膜层10，包覆所述凸点，所述非导电胶膜层的厚度大于所述凸点的高度。如图8所示以第三芯片结构为例，第三芯片结构的第一表面形成非导电胶膜层(Non-Conductive-Film，NCF)，例如Hitachi-AK400 Series。
如图9所示，所述键合层111包括：单体晶圆级芯片之间的凸点连接及包覆所述凸点连接的非导电胶膜层。通过设置非导电胶膜层可以改善单体晶圆级芯片在堆叠键合时不同凸点之间的桥接问题。
在一实施例中，如图10所示，还包括：塑封层112，基于基板级的包覆所述芯片键合体。通过塑封层将堆叠的多层芯片进行塑封，实现对芯片 的保护。
相应的本申请实施例还提供上述晶圆级多芯片堆叠互连结构的制备方法，如图11所示，包括：
步骤S21：在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层及凸点，形成第一芯片结构。
步骤S22：在第一芯片结构的基础上，对晶圆第二表面进行减薄抛光处理，直至所有硅通孔均露出，形成第二芯片结构。
步骤S23：根据实施1中所述的晶圆级芯片结构的制备方法，形成第三芯片结构。具体的是在第二芯片结构的基础上，利用深反应离子刻蚀工艺，在晶圆第二表面实现无掩膜刻蚀，使硅通孔相对于晶圆第二表面整体凸起；在晶圆第二表面实现绝缘介质层沉积，并通过刻蚀掩膜层制备以及锥台型盲孔刻蚀；在晶圆第二表面，依次进行阻挡层、种子层及凸点下金属化层的制备，形成第三芯片结构。
步骤S24：在基板第一表面依次将第二芯片结构、至少一个第三芯片结构、第一芯片结构基于凸点连接键合堆叠。本申请实施例，在第三芯片结构的晶圆背面TSV露头区域与UBM之间引入锥台型阻抗过渡结构，使TSV与UBM之间实现阻抗匹配，各个芯片键合的过渡区域引入锥台型阻抗过渡结构，改善了因阻抗突变引起的信号畸变问题。
步骤S25：在基板第二表面制备引出端子，形成晶圆级多芯片堆叠互连结构。本实施例中的引出端子可以为焊球，用于将互联结构的信号引出。
在一实施例中，如图12所示，在制备第一芯片结构及第二芯片结构时，在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层、凸点的步骤之后，还包括：制备非导电胶膜层，包覆所述凸点，所述非导电胶膜层的厚度大于所述凸点的高度。形成第三芯片结构的步骤之后，还包括：制备非导电胶膜层，包覆所述凸点，所述非导电胶膜层的厚度大于所述凸点的高度。各个芯片在键合时通过加热和加压的形式，使得非导电胶膜层融化为液体后，芯片之间通过凸点进行电气连接，防止凸点键合因为金属飞溅产生的桥接情况，使得键合效果更好。
如图13所示，将第二芯片结构、至少一个第三芯片结构、第一芯片结构基于凸点连接键合堆叠的步骤之后，还包括：
步骤S241：制备塑封层，对第二芯片结构、至少一个第三芯片结构、 第一芯片结构基于凸点连接键合堆叠形成的芯片键合体进行基板级塑封，形成如图10所示的结构。
在基板第二表面制备引出端子的步骤之后，还包括：
步骤S26：对晶圆级多芯片堆叠互连结构进行切割，形成单颗晶圆级芯片结构。
本申请提供的晶圆级多芯片堆叠互连结构及制备方法，将不同结构的单体晶圆级芯片进行堆叠键合，不同芯片键合的过渡区域引入锥台型阻抗过渡结构，改善了因阻抗突变引起的信号畸变问题，键合层引入了非导电胶膜层可以避免单体晶圆级芯片在堆叠键合时不同凸点之间的桥接问题。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请的保护范围之中。

Claims (11)

  1. 一种晶圆级芯片结构，其特征在于，包括：贯穿晶圆的硅通孔，其第一表面包括：有源区、多层再分布线层以及凸点，其第二表面包括：电镀掩膜层绝缘介质层，以及与硅通孔相连接的锥台过渡结构。
  2. 根据权利要求1所述的晶圆级芯片结构，其特征在于，所述锥台过渡结构一端开口直径根据与之相连的硅通孔尺寸确定，另一端开口直径根据键合凸点尺寸确定。
  3. 一种晶圆级多芯片堆叠互连结构，其特征在于，包括：芯片键合体、基板及引出端子，所述芯片键合体转接于所述基板的第一表面，引出端子形成于所述基板的第二表面，其中，
    芯片键合体，包括堆叠设置的多个单体晶圆级芯片，多个单体晶圆级芯片直接通过键合层连接，所述单体晶圆级芯片包括：一个第一芯片结构、一个第二芯片结构及至少一个第三芯片结构，所述第一芯片结构和第二芯片结构分别位于所述芯片键合体的两端，所述至少一个第三芯片结构，位于第一芯片结构和第二芯片结构之间；
    所述第三芯片结构为权利要求1或2所述的晶圆级芯片结构。
  4. 根据权利要求3所述的晶圆级多芯片堆叠互连结构，其特征在于，所述第一芯片结构，包括：未完全贯穿晶圆的硅通孔，其第一表面包括：有源区、多层再分布线层以及凸点，第二表面为晶圆面；
    所述第二芯片结构，包括：贯穿晶圆的硅通孔，其第一表面包括：有源区、多层再分布线层以及凸点，其第二表面为包含多个硅通孔连接的晶圆面。
  5. 根据权利要求4所述的晶圆级多芯片堆叠互连结构，其特征在于，
    第一芯片结构、第二芯片结构及第三芯片结构的第一表面均包括：非导电胶膜层，包覆所述凸点，所述非导电胶膜层的厚度大于所述凸点的高度；
    所述键合层包括：单体晶圆级芯片之间的凸点连接及包覆所述凸点连接的非导电胶膜层。
  6. 根据权利要求3-5任一所述的晶圆级多芯片堆叠互连结构，其特征在于，还包括：
    塑封层，基于基板级的包覆所述芯片键合体。
  7. 一种晶圆级芯片结构的制备方法，其特征在于，包括如下步骤：
    在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层及凸点；
    对晶圆第二表面进行减薄抛光处理，直至所有硅通孔均露出；
    利用深反应离子刻蚀工艺，在晶圆第二表面实现无掩膜刻蚀，使硅通孔相对于晶圆第二表面整体凸起；
    在晶圆第二表面实现绝缘介质层沉积，并通过刻蚀掩膜层制备以及锥台型盲孔刻蚀；
    在晶圆第二表面，依次进行阻挡层、种子层及凸点下金属化层的制备，形成所述晶圆级芯片结构。
  8. 一种晶圆级多芯片堆叠互连结构的制备方法，其特征在于，包括如下步骤：
    在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层及凸点，形成第一芯片结构；
    在第一芯片结构的基础上，对晶圆第二表面进行减薄抛光处理，直至所有硅通孔均露出，形成第二芯片结构；
    根据权利要求7所述的晶圆级芯片结构的制备方法，形成第三芯片结构；
    在基板第一表面依次将第二芯片结构、至少一个第三芯片结构、第一芯片结构基于凸点连接键合堆叠；
    在基板第二表面制备引出端子，形成晶圆级多芯片堆叠互连结构。
  9. 根据权利要求8所述的晶圆级多芯片堆叠互连结构的制备方法，其特征在于，在制备第一芯片结构及第二芯片结构时，在晶圆的第一表面依次制备有源区、硅通孔、多层再分布线层及凸点的步骤之后，还包括：制备非导电胶膜层，包覆所述凸点，所述非导电胶膜层的厚度大于所述凸点的高度；
    形成第三芯片结构的步骤之后，还包括：制备非导电胶膜层，包覆所述凸点，所述非导电胶膜层的厚度大于所述凸点的高度。
  10. 根据权利要求8或9任一所述的晶圆级多芯片堆叠互连结构的制备方法，其特征在于，将第二芯片结构、至少一个第三芯片结构、第一芯片 结构基于凸点连接键合堆叠的步骤之后，还包括：
    制备塑封层，对第二芯片结构、至少一个第三芯片结构、第一芯片结构基于凸点连接键合堆叠形成的芯片键合体进行基板级塑封。
  11. 根据权利要求10所述的晶圆级多芯片堆叠互连结构的制备方法，其特征在于，所述在基板第二表面制备引出端子的步骤之后，还包括：
    对晶圆级多芯片堆叠互连结构进行切割，形成单颗晶圆级芯片结构。
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