CN111799227A - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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Publication number
CN111799227A
CN111799227A CN202010242219.8A CN202010242219A CN111799227A CN 111799227 A CN111799227 A CN 111799227A CN 202010242219 A CN202010242219 A CN 202010242219A CN 111799227 A CN111799227 A CN 111799227A
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die
redistribution structure
conductive
active device
conductive pillars
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CN111799227B (zh
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余振华
郭鸿毅
刘重希
蔡豪益
谢政杰
于宗源
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

公开了封装的半导体器件及其形成方法，该封装的半导体器件包括附接至再分布结构的第一管芯、附接至第一管芯的第二管芯以及围绕第一管芯和第二管芯的模塑料。在实施例中，方法包括在第一再分布结构上方形成电耦接至第一再分布结构的第一导电柱；将第一管芯附接至第一再分布结构，第一管芯包括第二导电柱；在邻近第二导电柱的位置将第二管芯附接至第一管芯；用密封剂密封第一导电柱、第一管芯和第二管芯；在密封剂、第一导电柱、第一管芯和第二管芯上方形成第二再分布结构；并且将第三管芯接合至第一再分布结构。

Description

半导体器件及其形成方法
技术领域
本发明的实施例涉及半导体器件及其形成方法。
背景技术
半导体器件用于各种电子应用中，诸如例如，个人计算机、手机、数码相机和其他电子设备。通常，通过在半导体衬底上方顺序沉积绝缘层或介电层、导电层和半导体材料层，并且使用光刻图案化各个材料层，以在其上形成电路组件和元件来制造半导体器件。
半导体行业通过不断减小最小部件尺寸来持续改进各个电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度，这允许将更多组件集成到给定区域中。但是，随着最小部件尺寸的减小，出现了应该解决的其他问题。
发明内容
本发明的一些实施例提供了一种形成半导体器件的方法，包括：在第一再分布结构上方形成电耦接至所述第一再分布结构的第一导电柱；将第一管芯附接至所述第一再分布结构，所述第一管芯包括第二导电柱；在邻近所述第二导电柱的位置将第二管芯附接至所述第一管芯；用密封剂密封所述第一导电柱、所述第一管芯和所述第二管芯；在所述密封剂、所述第一导电柱、所述第一管芯和所述第二管芯上方形成第二再分布结构；以及将第三管芯接合至所述第一再分布结构。
本发明的另一些实施例提供了一种半导体器件，包括：第一器件，接合至第一再分布结构的第一侧；第二器件，附接至所述第一再分布结构的与所述第一侧相对的第二侧；第三器件，附接至所述第二器件；模塑料，围绕所述第二器件和所述第三器件；以及第二再分布结构，位于所述第二器件、所述第三器件和所述模塑料上方，其中，所述第一器件和所述第二器件使用所述第二再分布结构电耦接至所述第三器件。
本发明的又一些实施例提供了一种半导体器件，包括：第一管芯，附接至第一再分布结构；第一模塑料，位于所述第一再分布结构上方并且围绕所述第一管芯；第一通孔，延伸穿过所述第一模塑料；第二再分布结构，位于所述第一管芯、所述第一模塑料和所述第一通孔上方；第二管芯，附接至所述第二再分布结构；第二模塑料，位于所述第二再分布结构上方并且围绕所述第二管芯；以及第二通孔和第三通孔，延伸穿过所述第二模塑料，所述第二通孔电耦接至所述第一通孔，所述第二通孔包括具有圆形截面的通孔，所述第三通孔电耦接至所述第一管芯，所述第三通孔包括具有椭圆形截面的通孔。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图14示出了根据一些实施例的在用于形成封装的半导体器件的工艺期间的中间步骤的截面图。
图15至图20示出了根据一些实施例的在用于形成封装的半导体器件的工艺期间的中间步骤的截面图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作出相应的解释。
各个实施例提供了改进的管芯堆叠结构以及包括该管芯堆叠结构的封装的半导体器件。可以通过在背侧再分布结构上形成第一导电柱来形成管芯堆叠结构；将包括第二导电柱的第一有源器件管芯附接至背侧再分布结构；以及将第二有源器件管芯附接至第一有源器件管芯。可以在第一导电柱、第二导电柱和第二有源器件管芯上方形成前侧再分布结构，并且封装组件可以附接至背侧再分布结构。使用该方法允许第一有源器件管芯、第二有源器件管芯和封装组件以最小的面积互连在封装的半导体器件中。而且，可以通过单个模制步骤和单个研磨步骤同时在第一有源器件管芯和第二有源器件管芯周围形成模塑料。任何一个第一和第二导电柱可以是椭圆形或圆形的，以减小封装的半导体器件中的应力。
图1至图14是根据一些实施例的在封装的半导体器件200的制造期间的中间阶段的截面图。图1示出了根据一些实施例的有源器件管芯50A。有源器件管芯50A将在后续工艺期间封装以形成集成电路封装件。在实施例中，有源器件管芯50A可以是片上系统(SoC)。在另外的实施例中，有源器件管芯50A可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、应用处理器(AP)、微控制器等)、存储器管芯(例如，动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯、高带宽存储器(HBM)管芯等)、输入/输出(I/O)界面管芯、电源管理管芯(例如，电源管理集成电路(PMIC)管芯等)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯等)、前端管芯(例如，模拟前端(AFE)管芯等)等或它们的组合。在顶视图中，有源器件管芯50A可以具有从约9mm至约12mm的长度和在从约9mm至约12mm的宽度。
有源器件管芯50A可以形成在晶圆中，该晶圆可以包括在后续步骤中分割以形成多个有源器件管芯的不同的器件区域。可以根据适用的制造工艺来处理有源器件管芯50A以形成集成电路。例如，有源器件管芯50A包括半导体衬底52，诸如掺杂或未掺杂的硅或绝缘体上半导体(SOI)衬底的有源层。半导体衬底52可以包括其他半导体材料，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。也可以使用其他衬底，诸如多层或梯度衬底。半导体衬底52具有有源表面(例如，在图1中面向上的表面)，有时被称为前侧；以及无源表面(例如，在图1中面向下的表面)，有时被称为背侧。
器件54可以形成在半导体衬底52的前侧处。器件54可以是有源器件(例如，晶体管、二极管等)、电容器、电阻器等。在半导体衬底52的前侧上方形成层间电介质(ILD)56。ILD 56围绕并且可以覆盖器件54。ILD56可以包括由诸如磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)、未掺杂硅酸盐玻璃(USG)等的材料形成的一个或多个介电层。
导电插塞58延伸穿过ILD 56，以电和物理地耦接器件54。例如，当器件54是晶体管时，导电插塞58可以耦接晶体管的栅极和源极/漏极区域。导电插塞58可以由钨、钴、镍、铜、银、金、铝等或它们的组合形成。在ILD 56和导电插塞58上方包括互连结构60。互连结构60将器件54互连以形成集成电路。互连结构60可以由，例如，ILD 56上的介电层中的金属化图案形成。金属化图案包括形成在一个或多个低k介电层中的金属线和通孔。互连结构60的金属化图案通过导电插塞58电耦接至器件54。
有源器件管芯50A还包括制成至外部连接的焊盘62，诸如铝焊盘。焊盘62位于有源器件管芯50A的有源侧上，诸如位于互连结构60中和/或上。一个或多个钝化膜64位于有源器件管芯50A上，诸如位于互连结构60和焊盘62的部分上。开口穿过钝化膜64延伸到焊盘62。管芯连接件66，诸如导电柱(例如，由诸如铜的金属形成)，延伸穿过钝化膜64中的开口，并且物理和电耦接至相应的焊盘62。管芯连接件66可以通过例如镀等形成。管芯连接件66将有源器件管芯50A的相应集成电路电耦接。
可选地，可以在焊盘62上设置焊料区域(例如，焊球或焊料凸块)。焊球可以用于对有源器件管芯50A实施芯片探针(CP)测试。可以对有源器件管芯50A实施CP测试，以确定有源器件管芯50A是否是已知良好管芯(KGD)。因此，仅封装经受后续工艺的为KGD的有源器件管芯50A，并且不封装未通过CP测试的管芯。在测试之后，可以在随后的工艺步骤中去除焊料区域。
介电层68可以位于有源器件管芯50A的前侧上，诸如位于钝化膜64和管芯连接件66上。介电层68横向密封管芯连接件66，并且介电层68与有源器件管芯50A横向共末端。最初，介电层68可以掩埋管芯连接件66，从而使得介电层68的最上表面在管芯连接件66的最上表面之上。在焊料区域设置在管芯连接件66上的一些实施例中，介电层68也可以掩埋焊料区域。可选地，可以在形成介电层68之前去除焊料区域。
介电层68可以是聚合物，诸如PBO、聚酰亚胺、BCB等；氮化物，诸如氮化硅等；氧化物，诸如氧化硅、PSG、BSG、BPSG等；等，或它们的组合。介电层68可以例如通过旋涂、层压、CVD等形成。在一些实施例中，在有源器件管芯50A的形成期间，管芯连接件66通过介电层68暴露。在一些实施例中，管芯连接件66保持掩埋并且在后续工艺期间暴露，以用于封装有源器件管芯50A。暴露管芯连接件66可以去除管芯连接件66上可能存在的任何焊料区域。
在一些实施例中，有源器件管芯50A是包括多个半导体衬底52的堆叠器件。例如，有源器件管芯50A可以是包括多个存储器管芯的存储器器件，诸如混合存储立方体(HMC)模块、高带宽存储(HBM)模块等。在这样的实施例中，有源器件管芯50A包括通过衬底通孔(TSV)互连的多个半导体衬底52。每个半导体衬底52可以具有互连结构60。
图2至图4示出了在用于形成有源器件管芯50B的工艺期间的中间步骤的截面图。有源器件管芯50B可以与图1所示的有源器件管芯50A相同或相似，其中有源器件管芯50B包括代替管芯连接件66的导电柱70(图4所示)。在实施例中，有源器件管芯50B可以是宽输入/输出(WIO)存储器管芯。在本文的讨论中，除非另有说明，否则相同或相似的参考标号是指通过相同或相似的方法使用相同或相似的材料形成的相同或相似的组件，因此可以不重复细节。
在图2中，在分割之前，在同一半导体衬底52上提供两个有源器件管芯50B，该半导体衬底52可以是晶圆。尽管在每个有源器件管芯50B中示出了两个焊盘62，但是可以存在任何数量的焊盘62。在焊盘62上方形成一个或多个钝化膜64，并且在钝化膜64上方形成介电层68。可以图案化介电层68和钝化膜64以形成暴露部分焊盘62的开口72。可以通过可接受的工艺来实施图案化，诸如当介电层68是光敏材料时通过将介电层68暴露于光或通过使用例如各向异性蚀刻的蚀刻。在其中介电层68是光敏材料的实施例中，可以在暴露于光之后显影介电层68。
在图3中，导电柱70形成在开口72中并且在介电层68之上延伸。作为实例，可以通过首先在介电层68以及由开口72暴露的钝化膜64和焊盘62的部分上方形成晶种层来形成导电柱70。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于导电柱70。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过诸如电镀或化学镀等的镀形成。导电材料可以包括金属，诸如铜、钛、钨、铝等。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺，诸如使用氧等离子体等的工艺来去除光刻胶。一旦去除光刻胶，则使用诸如湿或干蚀刻的可接受的蚀刻工艺去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成导电柱70。
图3进一步示出了导电柱70的截面图。如图3所示，导电柱70可具有圆形截面形状或椭圆形截面形状。一些导电柱70可以具有圆形截面形状，而其他导电柱70可以具有椭圆形截面形状。诸如正方形、矩形、多边形等的其他截面形状也可以是可能的。在其中导电柱70具有圆形截面形状的实施例中，导电柱70可以具有在从约15μm至约40μm的直径D1，诸如约20μm。在其中导电柱70具有椭圆形截面形状的实施例中，导电柱70在顶视图中的长度L1可以在从约20μm至约50μm，诸如约35μm，并且导电柱70在顶视图中的宽度W1可以在从约15μm至约40μm，诸如约25μm。导电柱70的在介电层68之上延伸的部分可以具有在从约100μm至约120μm的高度H1，它可以大于随后放置在有源器件管芯50B(例如，图9所示的有源器件管芯50A)上方的管芯的高度。
在图4中，减薄半导体衬底52并且分割有源器件管芯50B。可以使用机械研磨或化学机械抛光(CMP)工艺，由此利用化学蚀刻剂和研磨剂来反应并且研磨掉半导体衬底52，直至半导体衬底52达到期望的厚度来减薄半导体衬底。可以使用切割工艺分割有源器件管芯50B，切割工艺诸如锯切、激光钻孔等。有源器件管芯50B可以沿着划线区域74(如图3所示)分割。在顶视图中，有源器件管芯50B的每个可以具有在从约9mm至约12mm的长度和在从约7mm至约12mm的宽度。在一些实施例中，有源器件管芯50B的前侧可以放置在带上，其中导电柱70在减薄和分割之前延伸至带。带可以具有大于导电柱70的高度的厚度，从而使得导电柱70由带围绕。该带可以包括聚合物材料、粘合材料等。
在图5中，提供了载体衬底102，并且释放层104形成在载体衬底102上。载体衬底102可以是玻璃载体衬底、陶瓷载体衬底等。载体衬底102可以是晶圆，从而使得可以在载体衬底102上同时形成多个封装件。
释放层104可以由基于聚合物的材料形成，其可以与载体衬底102一起从将在后续步骤中形成的上面结构去除。在一些实施例中，释放层104是基于环氧的热释放材料，其在加热时会失去其粘合性，诸如光热转换(LTHC)释放涂层。在其他实施例中，释放层104可以是紫外(UV)胶，当暴露于UV光时其失去粘合性。释放层104可以以液体形式分配并且固化，可以是层压在载体衬底102上的层压膜等。释放层104的顶面可以是水平的并且可以具有高度的平面度。
在图6中，可以在释放层104上形成背侧再分布结构106。在所示的实施例中，背侧再分布结构106包括介电层108、金属化图案110(有时称为再分布层或再分布线)和介电层112。背侧再分布结构106是可选的。在一些实施例中，代替背侧再分布结构106，在释放层104上形成没有金属化图案的介电层。
介电层108可以形成在释放层104上。介电层108的底面可以与释放层104的顶面接触。在一些实施例中，介电层108由聚合物形成，诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等。在其他实施例中，介电层108由氮化物，诸如氮化硅；氧化物，诸如氮化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂磷硅酸盐玻璃(BPSG)等；等形成。介电层108可以通过任何可接受的沉积工艺形成，诸如旋涂、化学汽相沉积(CVD)、层压等或它们的组合。
金属化图案110可以形成在介电层108上。作为实例，可以通过首先在介电层108上方形成晶种层来形成金属化图案110。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如物理汽相沉积(PVD)等形成晶种层。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案110。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过诸如电镀或化学镀等的镀形成。导电材料可以包括金属，诸如铜、钛、钨、铝等。然后去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等的工艺。一旦去除光刻胶，则使用诸如湿或干蚀刻的可接受的蚀刻工艺去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成金属化图案110。
介电层112可以形成在金属化图案110和介电层108上。在一些实施例中，介电层112由聚合物形成，该聚合物可以是光敏材料，诸如PBO、聚酰亚胺、BCB等，其可以使用光刻掩模图案化。在其他实施例中，介电层112由氮化物，诸如氮化硅；氧化物，诸如氧化硅、PSG、BSG、BPSG；等形成。介电层112可以通过旋涂、层压、CVD等或它们的组合来形成。可以图案化介电层112以形成暴露部分金属化图案110的开口114。可以通过可接受的工艺来实施图案化，诸如当介电层112是光敏材料时通过将介电层112暴露于光或通过使用例如各向异性蚀刻的蚀刻。在其中介电层112是光敏材料的实施例中，可以在曝光之后显影介电层112。
应当理解，背侧再分布结构106可以包括任何数量的介电层和金属化图案。如果要形成更多的介电层和金属化图案，则可以重复以上步骤和工艺。金属化图案可以包括导线和导电通孔。可以在金属化图案的形成期间通过在下面的介电层的开口中形成晶种层和金属化图案的导电材料来形成导电通孔。导电通孔可以互连并且电耦接金属化图案的各个导线。
在图7中，导电柱116形成在开口114(如图6所示)中，并且在背侧再分布结构106的最顶部介电层(例如，图6所示实施例中的介电层112)之上延伸。导电柱116可以用于将背侧再分布结构106与随后形成的前侧再分布结构(例如，图11所示的前侧再分布结构128)电耦接。在一些实施例中，至少一些导电柱可以不电耦接至背侧再分布结构106和前侧再分布结构128，并且可以用于散热。作为实例，可以通过首先在背侧再分布结构106上方(例如，在介电层112和金属化图案110的由开口114暴露的部分上)形成晶种层来形成导电柱116。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在特定实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于导电柱116。图案化形成穿过光刻胶的开口以暴露晶种层。在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过诸如电镀或化学镀等的镀形成。导电材料可以包括金属，诸如铜、钛、钨、铝等。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等工艺。一旦去除光刻胶，则使用诸如湿或干蚀刻的可接受的蚀刻工艺去除晶种层的暴露部分。晶种层的剩余部分和导电材料形成导电柱116。
图7还示出了导电柱116的截面。如图7所示，导电柱116可具有圆形截面形状或椭圆形截面形状。一些导电柱116可以具有圆形截面形状，而其他导电柱116可以具有椭圆形截面形状。诸如正方形、矩形、多边形等的其他截面形状也可以是可能的。在其中导电柱116具有圆形截面形状的实施例中，导电柱116可以具有在从约40μm至约150μm的直径D2，诸如约50μm或约90μm。在其中导电柱116具有椭圆形截面形状的实施例中，导电柱116在顶视图中的长度L2可以在从约40μm至约150μm，诸如约60μm，并且导电柱116在顶视图中的宽度W2可以在从约20μm至约130μm，诸如约30μm。导电柱116可以具有在从约80μm至约250μm的间距，诸如约200μm。
在一些实施例中，导电柱116可以用于将随后附接的有源器件管芯(例如，图9所示的有源器件管芯50A)和随后附接的封装组件(例如，图14所示的封装组件150)电耦接至随后附接的有源器件管芯(例如，图8所示的有源器件管芯50B)。在实施例中，电耦接至封装组件150的导电柱116可以是椭圆形的并且可以具有在从约80μm至约250μm的间距，并且电耦接至有源器件管芯50A的导电柱116可以是圆形的，并且可以具有在从约80μm至约250μm的间距。使用椭圆形导电柱116和圆形导电柱116可以通过应力再分布来减小应力，并且可以减小随后完成的器件中的缺陷。
在图8中，有源器件管芯50B通过粘合剂118粘附至介电层112。可以使用拾取和放置机械等将有源器件管芯50B放置在背侧再分布结构上方。粘合剂118位于有源器件管芯50B的背侧上，并且将有源器件管芯50B粘附至背侧再分布结构106，诸如至介电层112。粘合剂118可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂118可以施加到有源器件管芯50B的背侧，或者可以施加在载体衬底102上的介电层112的表面上方。例如，可以在分割有源器件管芯50B之前，将粘合剂118施加到有源器件管芯50B的背侧。如图8所示，在将有源器件管芯50B附接至背侧再分布结构106之后，导电柱116的顶面可以与导电柱70的顶面齐平。
在图9中，有源器件管芯50A通过粘合剂120粘附至有源器件管芯50B。可以使用拾取和放置机械等将有源器件管芯50A放置在有源器件管芯50B上方。粘合剂120位于有源器件管芯50A的背侧上，并且将有源器件管芯50A粘附至有源器件管芯50B，诸如粘附至介电层68。粘合剂120可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂120可以施加到有源器件管芯50A的背侧。例如，可以在分割有源器件管芯50B之前将粘合剂120施加到有源器件管芯50B的背侧。如图9所示，在实施例中，在将有源器件管芯50A附接至有源器件管芯50B之后，有源器件管芯50A的顶面(包括管芯连接件66和介电层68的顶面)可以与导电柱70和导电柱116的顶面齐平。在另外的实施例中，在将有源器件管芯50A附接至有源器件管芯50B之后，管芯连接件66、介电层68、导电柱70和导电柱116的顶面可以彼此不齐平。
图9还示出了通过粘合剂124粘附至介电层112的伪管芯122。在将有源器件管芯50A粘附至有源器件管芯50B和伪管芯122之前，将伪管芯122粘附至背侧再分布结构106。伪管芯122是可选的，并且可以包括或可以不包括。例如，如图9所示，有源器件管芯50A可以放置在有源器件50B上方，从而使得至少一部分有源器件管芯50A悬于背侧再分布结构106上方，而在其间没有插入有源器件管芯50B。可以根据有源器件管芯50B的尺寸、有源器件管芯50A的尺寸、突出量以及粘合剂120的强度将伪管芯122包括在有源器件管芯50A和背侧再分布结构106之间，以确保有源器件管芯50A是水平的并且不会倾斜。在一些实施例中，当伪管芯的宽度W3与突出部的距离D3的比率小于约2/3或小于约1/2时，可以包括伪管芯122。在其中包括伪管芯122的实施例中，在将有源器件管芯50A粘附至有源器件管芯50B和伪管芯122之前，将伪管芯122粘附至背侧再分布结构106。
可以使用拾取和放置机械等将伪管芯122放置在背侧再分布结构上方。粘合剂124位于伪管芯122的背侧上，并且将伪管芯122粘附至背侧再分布结构106，诸如粘附至介电层112。粘合剂124可以是任何合适的粘合剂、环氧树脂、管芯附接膜(DAF)等。粘合剂124可以施加到伪管芯122的背侧，或者可以施加在载体衬底102上的介电层112的表面上方。如图8所示，在将伪管芯122附接至背侧再分布结构106之后，伪管芯122的顶面可以与有源器件管芯50B的介电层68的顶面齐平。
伪管芯122不具有电功能，并且不电连接到背侧再分布结构106、有源器件管芯50A或有源器件管芯50B。伪管芯122可以由导电材料形成，诸如金属或金属合金、半导体材料、介电材料等。在一些实施例中，伪管芯122可以由硅、玻璃、石英、铜、碳化硅(SiC)等形成。
在图10中，密封剂126形成在背侧再分布结构106上方并且围绕有源器件管芯50A、有源器件管芯50B、伪管芯122和导电柱116。密封剂126可以是模塑料、环氧树脂等。密封剂126可以通过压缩模塑、传递模塑等施加，并且可以形成在背侧再分布结构106上方，从而使得有源器件管芯50A、有源器件管芯50B、伪管芯122和导电柱116被掩埋或覆盖。密封剂126可以以液体或半液体形式施加并且随后被固化。
进一步在图10中，对密封剂126实施平坦化工艺以暴露导电柱116、导电柱70、管芯连接件66和介电层68。平坦化工艺还可去除导电柱116、导电柱70、管芯连接件66和/或介电层68的材料。在一些实施例中，在平坦化工艺之前，导电柱116、导电柱70、管芯连接件66和介电层68的顶面可以彼此不齐平，并且可以利用平坦化工艺来使导电柱116、导电柱70、管芯连接件66和介电层68的顶面彼此平齐。平坦化工艺可以是，例如，CMP工艺、研磨工艺、回蚀工艺等。在一些实施例中，例如，如果导电柱116、导电柱70、管芯连接件66和介电层68已经暴露，则可以省略平坦化工艺。
在图11中，在密封剂126、导电柱116、导电柱70和有源器件管芯50A上方形成前侧再分布结构128。前侧再分布结构128包括介电层130、134、138和142；以及金属化图案132、136和140。金属化图案也可以称为再分布层或再分布线。图11所示的前侧再分布结构128包括三层金属化图案和四层介电层；然而，在前侧再分布结构128中可以包括更多或更少的金属化图案和介电层。如果要形成较少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和工艺。
介电层130沉积在密封剂126、导电柱116、导电柱70和有源器件管芯50A上。在一些实施例中，介电层130由可以使用光刻掩模图案化的光敏材料形成，诸如PBO、聚酰亚胺、BCB等。介电层130可以通过旋涂、层压、CVD等或它们的组合来形成。然后，图案化介电层130。图案化形成开口，该开口暴露导电柱116、导电柱70和管芯连接件66的部分。图案化可以通过可接受的工艺进行，诸如当介电层130是光敏材料时，通过使介电层130暴露于光或通过使用例如各向异性蚀刻的蚀刻。如果介电层130是光敏材料，则介电层130可以在曝光之后显影。
然后形成金属化图案132。金属化图案132包括位于介电层130的主表面上并且沿着介电层130的主表面延伸的线部分(也称为导线)。金属化图案132还包括延伸穿过介电层130的通孔部分(也称为导电通孔)，以物理和电耦接导电柱116、有源器件管芯50B的导电柱70和有源器件管芯50A的管芯连接件66。作为实例，可以通过首先在介电层130上方以及在延伸穿过介电层130的开口中形成晶种层来形成金属化图案132。在一些实施例中，晶种层是金属层，其可以是单层或包括由不同材料形成的多个子层的复合层。在一些实施例中，晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。然后在晶种层上形成光刻胶并且图案化光刻胶。光刻胶可以通过旋涂等形成，并且可以暴露于光以用于图案化。光刻胶的图案对应于金属化图案132。图案化形成穿过光刻胶的开口以暴露晶种层。然后在光刻胶的开口中和晶种层的暴露部分上形成导电材料。导电材料可以通过诸如电镀或化学镀等的镀形成。导电材料可以包括金属，如铜、钛、钨、铝等。导电材料和下面的晶种层的部分的组合形成金属化图案132。去除光刻胶和晶种层的其上未形成导电材料的部分。可以通过可接受的灰化或剥离工艺去除光刻胶，诸如使用氧等离子体等。一旦去除光刻胶，则使用诸如湿或干蚀刻的可接受的蚀刻工艺去除晶种层的暴露部分。
介电层134沉积在金属化图案132和介电层130上。介电层134可以以与介电层130相似的方式形成，并且可以由与介电层130的材料相似的材料形成。
然后形成金属化图案136。金属化图案136包括位于介电层134的主表面上并且沿着介电层134的主表面延伸的线部分。金属化图案136还包括延伸穿过介电层134的通孔部分以物理和电耦接金属化图案132。金属化图案136可以以与金属化图案132相似的方式形成，并且可以由与金属化图案132的材料相似的材料形成。
介电层138沉积在金属化图案136和介电层134上。介电层138可以以与介电层130相似的方式形成，并且可以由与介电层130的材料相似的材料形成。
然后形成金属化图案140。金属化图案140包括位于介电层138的主表面上并且沿着介电层138的主表面延伸的线部分。金属化图案140还包括延伸穿过介电层138的通孔部分以物理和电耦接金属化图案136。金属化图案140可以以与金属化图案132相似的方式形成，并且可以由与金属化图案132的材料相似的材料形成。金属化图案140是前侧再分布结构128的最顶部金属化图案。因此，前侧再分布结构128的所有中间金属化图案(例如，金属化图案132和136)设置在金属化图案140和密封剂126、导电柱116、有源器件管芯50B的导电柱70以及有源器件管芯50A的管芯连接件66之间。
介电层142沉积在金属化图案140和介电层138上。介电层142可以以与介电层130相似的方式形成，并且可以由与介电层130相似的材料形成。介电层142是前侧再分布结构128的最顶部介电层。因此，前侧再分布结构128的所有金属化图案(例如，金属化图案132、136和140)设置在介电层142和密封剂126、导电柱116、有源器件管芯50B的导电柱70以及有源器件管芯50A的管芯连接件66之间。此外，前侧再分布结构128的所有中间介电层(例如，介电层130、134、138)设置在介电层142和密封剂126、导电柱116、有源器件管芯50B的导电柱70以及有源器件管芯50A的管芯连接件66之间。
在图12中，UBM 144形成用于至前侧再分布结构128的外部连接。UBM 144在介电层142的主表面上并且沿着介电层142的主表面延伸有凸起部分，并且具有延伸穿过介电层142的通孔部分，以物理和电耦接至金属化图案140。因此，UBM 144电耦接至导电柱116、有源器件管芯50A和有源器件管芯50B。UBM 144可以由与金属化图案132相同的材料形成。在一些实施例中，UBM 144可以具有与金属化图案132、136和140不同的尺寸。
进一步在图12中，在UBM 144上形成导电连接件146。导电连接件146可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学钯浸金技术(ENEPIG)形成的凸块等。导电连接件146可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，通过首先通过蒸发、电镀、印刷、焊料转移、球放置等形成焊料层来形成导电连接件146。一旦在结构上形成焊料层，则可以实施回流以将材料成形为所需的凸块形状。在另一实施例中，导电连接件146包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。
在图13中，将图12的结构翻转，将载体衬底102从背侧再分布结构106(例如，介电层108)脱离，并且在介电层108中形成开口148。根据一些实施例，脱离包括将诸如激光或UV光的光投射在释放层104上，使得释放层104在光的热量下分解，并且可以去除载体衬底102。然后将结构翻转。在一些实施例中，该结构可以放置在带(未单独示出)上。开口148形成为穿过介电层108以暴露部分金属化图案110。开口148可以例如使用激光钻孔、蚀刻等形成。
在图14中，封装组件150接合至背侧再分布结构106以形成封装的半导体器件200。在一些实施例中，封装组件150可以是存储器管芯(例如，动态随机存取存储器(DRAM)管芯、低功耗双倍数据速率同步动态随机存取存储器(LPDDR)管芯、静态随机存取存储器(SRAM)管芯、高带宽存储器(HBM)管芯等)。在其他实施例中，封装组件150可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、应用处理器(AP)、微控制器等)、输入/输出(I/O)界面管芯、电源管理管芯(例如，电源管理集成电路(PMIC)管芯等)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯等)、前端管芯(例如，模拟前端(AFE)管芯等)等或它们的组合。
可以使用导电连接件152将封装组件150接合至背侧再分布结构106。导电连接件152可以形成在开口148中，可以设置在封装组件150上，或者它们的组合。导电连接件152可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件152可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，通过首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等的方法形成焊料层来形成导电连接件152。一旦在结构上形成焊料层，则可以实施回流以将材料成形为所需的凸块形状。可以使用拾取和放置机械等将封装组件150放置在背侧再分布结构106上方。一旦放置封装组件150，则可以回流导电连接件152以将封装组件150接合至背侧再分布结构106。
通过在有源器件50B中形成导电柱70、有源器件50B和有源器件50A可以在两个平面上附接至背侧再分布结构106，从而需要覆盖区。而且，仅需要单个模制和研磨步骤来形成密封有源器件50B和有源器件50A的密封剂126。在封装的半导体器件200中包括背侧再分布结构106和前侧再分布结构128允许有源器件管芯50B(例如，WIO存储器管芯)和封装组件150(例如，LPDDR管芯或DRAM管芯)利用不同的输入/输出焊盘位置与有源器件管芯50A(例如，SoC)集成在一起，因此在用于集成在封装的半导体器件200中的管芯的选择上提供了灵活性。导电柱116与背侧再分布结构106和前侧再分布结构128之间的铜至铜界面减小了导电柱116的电阻，从而减小了封装的半导体器件200的RC延迟并且改进了信号完整性。此外，包括椭圆形和圆形导电柱116和70减小了封装的半导体器件200中的应力。
图15至图20是根据一些实施例的在制造封装的半导体器件300中的中间阶段的截面图。与在图1至图14中使用的参考标号相同的图15至图20中使用的参考标号表示使用相似工艺形成的相同或相似的层和/或结构。因此，可以使用与以上参考图1至图14所讨论的那些相同或相似的材料和方法来形成具有相同参考标号的层和结构，并且将不再重复。在图15中，提供了载体衬底102，在载体衬底102上形成释放层104，并且在释放层104上形成背侧再分布结构106。导电柱115和导电柱117形成为在背侧再分布结构106的最顶部介电层(例如，图15所示实施例中的介电层112)之上延伸并且穿过介电层112以接触金属化图案110。导电柱115和导电柱117可以以与导电柱116相似的方式形成，并且可以由与导电柱116的材料相似的材料形成。
有源器件管芯50C通过粘合剂119附接至背侧再分布结构106。有源器件管芯50C可以以与有源器件管芯50A相似的方式形成，并且可以由与有源器件管芯50A的材料相似的材料形成。在一些实施例中，有源器件管芯50C可以具有与有源器件管芯50A不同的尺寸。在顶视图中，有源器件管芯50C可以具有在从约9mm至约12mm的长度和在从约7mm至约12mm的宽度。在实施例中，有源器件管芯50C可以是WIO存储器管芯。粘合剂119可以以与粘合剂118相似的方式形成，并且可以由与粘合剂118的材料相似的材料形成。
在一些实施例中，导电柱115可以提供有源器件50C和每个有源器件(例如，图18A中所示的有源器件50D)与封装组件(例如，图20所示的封装组件150)之间的电耦接。导电柱117可以提供散热并且可以或可以不电耦接至任何一个有源器件50C、有源器件50D和封装组件150。导电柱115和/或导电柱117可以具有圆形截面形状或椭圆形截面形状。诸如正方形、矩形、多边形等的其他截面形状也可以是可能的。在其中导电柱115和/或导电柱117具有圆形截面形状的实施例中，导电柱115和/或导电柱117可以具有在从约20μm至约150μm的直径，诸如约30μm或约90μm。在导电柱115和/或导电柱117具有椭圆形截面形状的实施例中，导电柱115和/或导电柱117在顶视图中的长度可以在从约40μm至约160μm，诸如约60μm，并且导电柱115和/或导电柱117在顶视图中的宽度可以在从约30μm至约150μm，诸如约30μm。导电柱115可以具有在从约80μm至约250μm的间距，诸如约150μm。导电柱117可以具有在从约80μm至约250μm的间距，诸如约150μm。
在图16中，密封剂127形成在背侧再分布结构106上方并且围绕有源器件管芯50C、导电柱115和导电柱117。密封剂127可以以与密封剂126相似的方式形成，并且可以由与密封剂126的材料相似的材料形成。可以平坦化密封剂127以暴露导电柱115、导电柱117和有源器件管芯50C的管芯连接件66。平坦化工艺还可以去除有源器件管芯50C的管芯连接件66、介电层68、导电柱115和/或导电柱117的材料。平坦化工艺可以是例如CMP工艺、研磨工艺、回蚀工艺等。在一些实施例中，例如，如果导电柱115、导电柱117和管芯连接件66已经暴露，则可以省略平坦化工艺。
在图17中，在密封剂127、导电柱115、导电柱117和有源器件管芯50C上方形成中间再分布结构170。中间再分布结构170包括介电层172和176；以及金属化图案174。金属化图案也可以称为再分布层或再分布线。图17所示的中间再分布结构170包括一层金属化图案和两层介电层，然而，在中间再分布结构170中可以包括更多或更少的金属化图案和介电层。如果要形成较少的介电层和金属化图案，则可以省略下面讨论的步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复下面讨论的步骤和工艺。
介电层172沉积在密封剂127、导电柱115、导电柱117和有源器件管芯50C上。介电层172可以以与介电层130相似的方式形成，并且可以由与介电层130的材料相似的材料形成。
然后形成金属化图案174。金属化图案174包括位于介电层172的主表面上并且沿着介电层172的主表面延伸的线部分。金属化图案174还包括延伸穿过介电层172的通孔部分，以物理和电耦接导电柱115、导电柱117和管芯连接件66。金属化图案174可以以与金属化图案132相似的方式形成，并且可以由与金属化图案132的材料相似的材料形成。
介电层176沉积在金属化图案174和介电层172上。介电层176可以以与介电层130相似的方式形成，并且可以由与介电层130的材料相似的材料形成。可以形成穿过介电层176的开口178，以暴露部分金属化图案174。开口178可以例如使用激光钻孔、蚀刻等形成。
在图18A中，导电柱121和导电柱125形成为在中间再分布结构170的最顶部介电层(例如，图17所示实施例中的介电层176)之上延伸并且穿过介电层176以接触金属化图案174。导电柱121和导电柱125可以以与导电柱116相似的方式形成，并且可以由与导电柱116的材料相似的材料形成。
有源器件管芯50D通过粘合剂123附接至中间再分布结构170。有源器件管芯50D可以以与有源器件管芯50A相似的方式形成，并且可以由与有源器件管芯50A的材料相似的材料形成。在一些实施例中，有源器件管芯50D可以具有与有源器件管芯50C不同的尺寸。在顶视图中，有源器件管芯50D可以具有在从约9mm至约12mm的长度和在从约7mm至约12mm的宽度。在实施例中，有源器件管芯50D可以是SoC。粘合剂123可以以与粘合剂118相似的方式形成，并且可以由与粘合剂118的材料相似的材料形成。
图18B示出图18A的结构的一部分的截面图，该结构包括位于第一区域133中的导电柱121、位于第二区域135中的导电柱125以及有源器件管芯50D。在顶视图中，第一区域133中的导电柱121和第二区域中的导电柱125的图案可以连续为使得第一区域133中的导电柱121环绕第二区域135，并且第二区域135中的导电柱125环绕有源器件管芯50D。第二区域135中的每单位面积的导电柱125的分布可以大于第一区域133中的每单位面积的导电柱121的分布。例如，第一区域133中每单位面积的导电柱121的分布可以在从约20pillars/mm2至约80pillars/mm2，诸如约49pillars/mm2，而第二区域135中每单位面积的导电柱125的分布可以在从约200pillars/mm2至约800pillars/mm2，诸如约625pillars/mm2。如图18B所示，第一区域133中的导电柱121可以具有圆形截面形状，而第二区域135可以包括具有圆形截面形状的导电柱125a以及具有椭圆形截面形状的导电柱125b。在顶视图中，导电柱125a和导电柱125b的图案可以连续为使得具有椭圆形截面形状的导电柱125b环绕具有圆形截面形状的导电柱125a。导电柱121可以具有在从约50μm至约120μm的直径D4，诸如约90μm。在另一实施例中，导电柱121具有在从约25μm至约35μm的直径D4。导电柱125a可以具有在从约20μm至约50μm的直径D5，诸如约30μm。在顶视图中，导电柱125b的长度L4可以在从约35μm至约55μm，诸如约45μm。并且在顶视图中，导电柱125b的宽度W3可以在从约20μm至约35μm，诸如约25μm。在另一实施例中，导电柱125b可以具有在从约25μm至约50μm的长度L4和在从约25μm至约37μm的宽度W3。
第一区域133中的导电柱121可以包括为通过中间再分布结构170和前侧再分布结构128在随后接合的封装组件(例如，图20中所示的封装组件150)和有源器件管芯50D之间提供互连。第二区域中的导电柱125可以包括为通过中间再分布结构170和前侧再分布结构128在有源器件管芯50C和有源器件管芯50D之间提供互连。分别可以基于要在封装组件150和有源器件管芯50D之间以及在有源器件管芯50C和有源器件管芯50D之间发送的信号(例如，电源信号、数据信号等)的类型来选择第一区域133中的导电柱121和第二区域135中的导电柱125的分布、形状和尺寸。包括椭圆形导电柱125b和圆形导电柱125a两者可以扩大用于形成器件的工艺窗口，从而需要较少的控制，这简化了工艺并且增加了器件产量。包括椭圆形导电柱125b和圆形导电柱125a两者也可以减小完成的器件中的应力。
在图19中，密封剂129形成在中间再分布结构170上方并且围绕有源器件管芯50D、导电柱121和导电柱125。密封剂129可以以与密封剂126相似的方式形成，并且可以由与密封剂126的材料相似的材料形成。可以平坦化密封剂129以暴露导电柱121、导电柱125和有源器件管芯50D的管芯连接件66。平坦化工艺还可以去除有源器件管芯50D的管芯连接件66、介电层68、导电柱121和/或导电柱125的材料。平坦化工艺可以是例如CMP工艺、研磨工艺、回蚀工艺等。在一些实施例中，例如，如果导电柱121、导电柱125和管芯连接件66已经暴露，则可以省略平坦化工艺。
进一步在图19中，在密封剂129、导电柱121、导电柱125和有源器件管芯50D上方形成前侧再分布结构128。前侧再分布结构128包括介电层130、134、138和142；以及金属化图案132、136和140。金属化图案也可以称为再分布层或再分布线。图19所示的前侧再分布结构128包括三层金属化图案和四层介电层；但是，前侧再分布结构128中可以包含更多或更少的金属化图案和介电层。如果要形成较少的介电层和金属化图案，则可以省略以上步骤和工艺。如果要形成更多的介电层和金属化图案，则可以重复以上步骤和工艺。
UBM 144形成为用于至前侧再分布结构128的外部连接。UBM 144在介电层142的主表面上并且沿着介电层142的主表面延伸有凸起部分，并且具有延伸穿过介电层142的通孔部分，以物理和电耦接至金属化图案140。因此，UBM 144电耦接至导电柱121、导电柱125、导电柱115、导电柱117、有源器件管芯50C和有源器件管芯50D。UBM 144可以由与金属化图案132相同的材料形成。在一些实施例中，UBM 144可以具有与金属化图案132、136和140不同的尺寸。
在UBM 144上形成导电连接件146。导电连接件146可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件146可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，导电连接件146通过首先通过蒸发、电镀、印刷、焊料转移、球放置等形成焊料层而形成。一旦在结构上形成焊料层，则可以实施回流以将材料成形为所需的凸块形状。在另一实施例中，导电连接件146包括通过溅射、印刷、电镀、化学镀、CVD等形成的金属柱(诸如铜柱)。金属柱可以是无焊料的并且具有基本垂直的侧壁。在一些实施例中，在金属柱的顶部上形成金属覆盖层。金属覆盖层可以包括镍、锡、锡铅、金、银、钯、铟、镍-钯-金、镍-金等或它们的组合，并且可以通过镀工艺形成。
在图20中，将图19的结构翻转，载体衬底102从背侧再分布结构106(例如，介电层108)脱离，在介电层108中形成开口(未单独示出)，并且通过导电连接件152将封装组件150接合至背侧再分布结构，以形成封装的半导体器件300。根据一些实施例，脱离包括将诸如激光或UV光投射在释放层104上使得释放层104在光的热量下分解，并且可以去除载体衬底102。然后将结构翻转。在一些实施例中，该结构可以放置在带(未单独示出)上。开口形成为穿过介电层108以暴露部分金属化图案110。可以例如使用激光钻孔、蚀刻等形成开口。
然后，将封装组件150接合至背侧再分布结构106。在一些实施例中，封装组件150可以是存储器管芯(例如，动态随机存取存储器(DRAM)管芯、低功耗双倍数据速率同步动态随机存取存储器(LPDDR)管芯、静态随机存取存储器(SRAM)管芯、高带宽存储器(HBM)管芯等)。在其他实施例中，封装组件150可以是逻辑管芯(例如，中央处理单元(CPU)、图形处理单元(GPU)、片上系统(SoC)、应用处理器(AP)、微控制器等)、输入/输出(I/O)界面管芯、电源管理管芯(例如，电源管理集成电路(PMIC)管芯等)、射频(RF)管芯、传感器管芯、微机电系统(MEMS)管芯、信号处理管芯(例如，数字信号处理(DSP)管芯等)、前端管芯(例如，模拟前端(AFE)管芯等)或它们的组合。
使用导电连接件152将封装组件150接合至背侧再分布结构106。导电连接件152可以形成在介电层108中的开口中，可以设置在封装组件150上，或者可以是它们的组合。导电连接件152可以是球栅阵列(BGA)连接件、焊球、金属柱、可控塌陷芯片连接(C4)凸块、微凸块、化学镀镍-化学镀钯浸金技术(ENEPIG)形成的凸块等。导电连接件152可以包括导电材料，诸如焊料、铜、铝、金、镍、银、钯、锡等或它们的组合。在一些实施例中，通过首先通过诸如蒸发、电镀、印刷、焊料转移、球放置等的方法形成焊料层来形成导电连接件152。一旦在结构上形成焊料层，则可以实施回流以将材料成形为所需的凸块形状。可以使用拾取和放置机械等将封装组件150放置在背侧再分布结构106上方。一旦放置封装组件150，则可以回流导电连接件152以将封装组件150接合至背侧再分布结构106。
在封装的半导体器件300中包括背侧再分布结构106、中间再分布结构170和前侧再分布结构128允许有源器件管芯50C(例如，WIO存储器管芯)和封装组件150(例如，LPDDR管芯或DRAM管芯)利用不同的输入/输出焊盘位置与有源器件管芯50D(例如，SoC)集成在一起，因此在用于集成在封装的半导体器件300中的管芯的选择上提供了灵活性。导电柱117提供改进了的散热。导电柱115和背侧再分布结构106以及中间再分布结构170之间以及导电柱121/导电柱125和中间再分布结构170和前侧再分布结构128之间的铜至铜界面，减小了导电柱115、导电柱121和导电柱125的电阻，减小了封装的半导体器件300的RC延迟并且改进了信号的完整性。此外，包括椭圆形和圆形导电柱115、117、121和/或125减小了封装的半导体器件300中的应力。
根据实施例，方法包括在第一再分布结构上方形成电耦接至第一再分布结构的第一导电柱；将第一管芯附接至第一再分布结构，第一管芯包括第二导电柱；在邻近第二导电柱的位置，将第二管芯附接至第一管芯；用密封剂密封第一导电柱、第一管芯和第二管芯；在密封剂、第一导电柱、第一管芯和第二管芯上方形成第二再分布结构；以及将第三管芯接合至第一再分布结构。在实施例中，使用第一粘合剂将第一管芯附接至再分布结构，并且使用第二粘合剂将第二管芯附接至第一管芯。在实施例中，方法还包括将伪管芯附接至第一再分布结构，将第二管芯附接至第一管芯还包括将第二管芯附接至伪管芯。在实施例中，方法还包括形成第一管芯，形成第一管芯包括在半导体衬底上方形成第二导电柱；将半导体衬底和导电柱附接至带，该带围绕第二导电柱；减薄与第二导电柱相对的半导体衬底的背侧；以及分割第一管芯。在实施例中，方法还包括平坦化密封剂，从而使得密封剂、第一导电柱、第二导电柱和第二管芯的顶面彼此齐平。在实施例中，第一管芯、第二管芯和密封剂设置在第一再分布结构的第一侧上，并且第三管芯设置在第一再分布结构的与第一侧相对的第二侧上。
根据另一实施例，器件包括接合至第一再分布结构的第一侧的第一器件；附接至第一再分布结构的与第一侧相对的第二侧的第二器件；附接至第二器件的第三器件；围绕第二器件和第三器件的模塑料；以及位于第二器件、第三器件和模塑料上方的第二再分布结构，第一器件和第二器件使用第二再分布结构电耦接至第三器件。在实施例中，第一器件包括动态随机存取存储器(DRAM)器件，第二器件包括宽输入/输出(WIO)存储器器件，并且第三器件包括片上系统(SoC)。在实施例中，第一器件包括低功耗双倍数据速率同步动态随机存取存储器(LPDDR)器件，第二器件包括宽输入/输出(WIO)存储器器件，并且第三器件包括片上系统(SoC)。在实施例中，器件还包括延伸穿过模塑料的第一导电柱，第一导电柱电耦接至第一再分布结构和第二再分布结构，第一器件通过第一导电柱电耦接至第三器件。在实施例中，器件还包括延伸穿过模塑料的第二导电柱，第二导电柱电耦接至第二器件和第二再分布结构，第二器件通过第二导电柱电耦接至第三器件。在实施例中，器件还包括设置在第三器件和第一再分布结构之间的伪管芯，伪管芯包括硅。
根据又一实施例，器件包括附接至第一再分布结构的第一管芯；位于第一再分布结构上方并且围绕第一管芯的第一模塑料；延伸穿过第一模塑料的第一通孔；位于第一管芯、第一模塑料和第一通孔上方的第二再分布结构；附接至第二再分布结构的第二管芯；位于第二再分布结构上方并且围绕第二管芯的第二模塑料；以及延伸穿过第二模塑料的第二通孔和第三通孔，第二通孔电耦接至第一通孔，第二通孔包括具有圆形截面的通孔，第三通孔电耦接至第一管芯，第三通孔包括具有椭圆形截面的通孔。在实施例中，第三通孔每单位面积的分布大于第二通孔每单位面积的分布。在实施例中，第二通孔在顶视图中具有在从50μm至120μm的直径，第三通孔在顶视图中具有在从20μm至35μm的宽度，并且第三通孔在顶视图中具有在从35μm至50μm的长度。在实施例中，器件还包括与第一管芯相对地接合至第一再分布结构的第三管芯，第三管芯电耦接至第一通孔。在实施例中，器件还包括位于第二通孔、第三通孔、第二管芯和第二模塑料上方的第三再分布结构，第二通孔和第三通孔使用第三再分布结构电耦接至第二管芯。在实施例中，第三管芯包括低功率双倍数据速率同步动态随机存取存储器(LPDDR)管芯，第一管芯包括宽输入/输出(WIO)存储器管芯，并且第三管芯包括片上系统(SoC)。在实施例中，第三管芯使用焊料接合而接合至第一再分布结构，第一管芯使用第一粘合剂附接至第一再分布结构，并且第二管芯使用第二粘合剂附接至第二再分布结构。在实施例中，器件还包括延伸穿过第一模塑料的第四通孔，第四通孔与第一管芯和第二管芯电隔离。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种形成半导体器件的方法，包括：
在第一再分布结构上方形成电耦接至所述第一再分布结构的第一导电柱；
将第一管芯附接至所述第一再分布结构，所述第一管芯包括第二导电柱；
在邻近所述第二导电柱的位置将第二管芯附接至所述第一管芯；
用密封剂密封所述第一导电柱、所述第一管芯和所述第二管芯；
在所述密封剂、所述第一导电柱、所述第一管芯和所述第二管芯上方形成第二再分布结构；以及
将第三管芯接合至所述第一再分布结构。
2.根据权利要求1所述的方法，其中，使用第一粘合剂将所述第一管芯附接至所述再分布结构，并且其中，使用第二粘合剂将所述第二管芯附接至所述第一管芯。
3.根据权利要求1所述的方法，还包括，将伪管芯附接至所述第一再分布结构，其中，将所述第二管芯附接至所述第一管芯还包括将所述第二管芯附接至所述伪管芯。
4.根据权利要求1所述的方法，还包括，形成所述第一管芯，其中，形成所述第一管芯包括：
在半导体衬底上方形成所述第二导电柱；
将所述半导体衬底和所述第二导电柱附接至带上，所述带围绕所述第二导电柱；
减薄与所述第二导电柱相对的所述半导体衬底的背侧；以及
分割所述第一管芯。
5.根据权利要求1所述的方法，还包括：平坦化所述密封剂，从而使得所述密封剂、所述第一导电柱、所述第二导电柱和所述第二管芯的顶面彼此齐平。
6.根据权利要求1所述的方法，其中，所述第一管芯、所述第二管芯和所述密封剂设置在所述第一再分布结构的第一侧上，并且所述第三管芯设置在所述第一再分布结构的与所述第一侧相对的第二侧上。
7.一种半导体器件，包括：
第一器件，接合至第一再分布结构的第一侧；
第二器件，附接至所述第一再分布结构的与所述第一侧相对的第二侧；
第三器件，附接至所述第二器件；
模塑料，围绕所述第二器件和所述第三器件；以及
第二再分布结构，位于所述第二器件、所述第三器件和所述模塑料上方，其中，所述第一器件和所述第二器件使用所述第二再分布结构电耦接至所述第三器件。
8.根据权利要求7所述的半导体器件，其中，所述第一器件包括动态随机存取存储器(DRAM)器件，其中，所述第二器件包括宽输入/输出(WIO)存储器器件，并且其中，所述第三器件包括片上系统(SoC)。
9.根据权利要求7所述的半导体器件，其中，所述第一器件包括低功率双倍数据速率同步动态随机存取存储器(LPDDR)器件，其中，所述第二器件包括宽输入/输出(WIO)存储器器件，并且其中，所述第三器件包括片上系统(SoC)。
10.一种半导体器件，包括：
第一管芯，附接至第一再分布结构；
第一模塑料，位于所述第一再分布结构上方并且围绕所述第一管芯；
第一通孔，延伸穿过所述第一模塑料；
第二再分布结构，位于所述第一管芯、所述第一模塑料和所述第一通孔上方；
第二管芯，附接至所述第二再分布结构；
第二模塑料，位于所述第二再分布结构上方并且围绕所述第二管芯；以及
第二通孔和第三通孔，延伸穿过所述第二模塑料，所述第二通孔电耦接至所述第一通孔，所述第二通孔包括具有圆形截面的通孔，所述第三通孔电耦接至所述第一管芯，所述第三通孔包括具有椭圆形截面的通孔。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113130420A (zh) * 2021-03-19 2021-07-16 南通越亚半导体有限公司 一种嵌埋封装结构及其制造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11094672B2 (en) 2019-09-27 2021-08-17 Intel Corporation Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
US11205630B2 (en) 2019-09-27 2021-12-21 Intel Corporation Vias in composite IC chip structures
US11868047B2 (en) * 2020-09-21 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. Polymer layer in semiconductor device and method of manufacture
CN112420529B (zh) * 2020-11-27 2022-04-01 上海易卜半导体有限公司 封装件及形成封装件的方法
US20220173074A1 (en) 2020-11-27 2022-06-02 Yibu Semiconductor Co., Ltd. Chip Package and Method of Forming Chip Packages
US20220262766A1 (en) * 2021-02-12 2022-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Through-Dielectric Vias for Direct Connection and Method Forming Same
US20220328467A1 (en) * 2021-04-08 2022-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Molded dies in semicondcutor packages and methods of forming same
US11984376B2 (en) * 2021-04-22 2024-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor device including a cooling structure
US20230019333A1 (en) * 2021-07-14 2023-01-19 Qualcomm Incorporated Package comprising stacked integrated devices with overhang
TWI818458B (zh) * 2022-03-04 2023-10-11 矽品精密工業股份有限公司 電子封裝件及其製法

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI234862B (en) * 2004-02-26 2005-06-21 Advanced Semiconductor Eng Chip scale package structure
CN105185762A (zh) * 2014-06-12 2015-12-23 台湾积体电路制造股份有限公司 用于增强封装件的可靠性的焊盘设计
TW201618274A (zh) * 2014-08-12 2016-05-16 英凡薩斯公司 用於整合式超高密度裝置的方法及裝置
CN105895596A (zh) * 2015-02-13 2016-08-24 台湾积体电路制造股份有限公司 通过调整PoP封装件中的开口尺寸来减少裂痕
CN106684048A (zh) * 2015-11-10 2017-05-17 台湾积体电路制造股份有限公司 多堆叠叠层封装结构
US20170207197A1 (en) * 2016-01-19 2017-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
CN107665887A (zh) * 2016-07-29 2018-02-06 台湾积体电路制造股份有限公司 封装结构及其形成方法
US20190006241A1 (en) * 2017-06-30 2019-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for direct forming stressor, semiconductor device having stressor, and method for forming the same
CN109509740A (zh) * 2017-09-15 2019-03-22 台湾积体电路制造股份有限公司 天线结构

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004071947A (ja) 2002-08-08 2004-03-04 Renesas Technology Corp 半導体装置
US20070231970A1 (en) * 2006-03-31 2007-10-04 Tsuyoshi Fukuo Cured mold compound spacer for stacked-die package
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US9443783B2 (en) 2012-06-27 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC stacking device and method of manufacture
US8889484B2 (en) * 2012-10-02 2014-11-18 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for a component package
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
US9508702B2 (en) * 2013-09-27 2016-11-29 Freescale Semiconductor, Inc. 3D device packaging using through-substrate posts
US9508701B2 (en) * 2013-09-27 2016-11-29 Freescale Semiconductor, Inc. 3D device packaging using through-substrate pillars
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9425126B2 (en) 2014-05-29 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structure for chip-on-wafer-on-substrate
US9824990B2 (en) 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same
US9558968B2 (en) 2014-09-11 2017-01-31 Semiconductor Components Industries, Llc Single or multi chip module package and related methods
US20160092383A1 (en) 2014-09-26 2016-03-31 Kuljit S. Bains Common die implementation for memory devices
US9728510B2 (en) * 2015-04-10 2017-08-08 Analog Devices, Inc. Cavity package with composite substrate
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9502397B1 (en) * 2015-04-29 2016-11-22 Deca Technologies, Inc. 3D interconnect component for fully molded packages
US9837378B2 (en) 2015-10-23 2017-12-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Fan-out 3D IC integration structure without substrate and method of making the same
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US20170278825A1 (en) * 2016-03-24 2017-09-28 Freescale Semiconductor, Inc. Apparatus and Methods for Multi-Die Packaging
US9768133B1 (en) 2016-09-22 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US10475770B2 (en) 2017-02-28 2019-11-12 Amkor Technology, Inc. Semiconductor device having stacked dies and stacked pillars and method of manufacturing thereof

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI234862B (en) * 2004-02-26 2005-06-21 Advanced Semiconductor Eng Chip scale package structure
CN105185762A (zh) * 2014-06-12 2015-12-23 台湾积体电路制造股份有限公司 用于增强封装件的可靠性的焊盘设计
TW201618274A (zh) * 2014-08-12 2016-05-16 英凡薩斯公司 用於整合式超高密度裝置的方法及裝置
CN105895596A (zh) * 2015-02-13 2016-08-24 台湾积体电路制造股份有限公司 通过调整PoP封装件中的开口尺寸来减少裂痕
CN106684048A (zh) * 2015-11-10 2017-05-17 台湾积体电路制造股份有限公司 多堆叠叠层封装结构
US20170207197A1 (en) * 2016-01-19 2017-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
CN106981475A (zh) * 2016-01-19 2017-07-25 台湾积体电路制造股份有限公司 器件、封装的半导体器件和半导体器件封装方法
CN107665887A (zh) * 2016-07-29 2018-02-06 台湾积体电路制造股份有限公司 封装结构及其形成方法
US20190006241A1 (en) * 2017-06-30 2019-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for direct forming stressor, semiconductor device having stressor, and method for forming the same
CN109509740A (zh) * 2017-09-15 2019-03-22 台湾积体电路制造股份有限公司 天线结构

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113130420A (zh) * 2021-03-19 2021-07-16 南通越亚半导体有限公司 一种嵌埋封装结构及其制造方法

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