CN103441095A - 半导体集成电路器件的制造方法 - Google Patents
半导体集成电路器件的制造方法 Download PDFInfo
- Publication number
- CN103441095A CN103441095A CN201310099950XA CN201310099950A CN103441095A CN 103441095 A CN103441095 A CN 103441095A CN 201310099950X A CN201310099950X A CN 201310099950XA CN 201310099950 A CN201310099950 A CN 201310099950A CN 103441095 A CN103441095 A CN 103441095A
- Authority
- CN
- China
- Prior art keywords
- hole
- manufacture method
- semiconductor device
- wafer
- perforation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 244
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 179
- 238000000034 method Methods 0.000 claims abstract description 470
- 230000008569 process Effects 0.000 claims abstract description 122
- 239000000758 substrate Substances 0.000 claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 claims description 88
- 239000002184 metal Substances 0.000 claims description 88
- 230000015572 biosynthetic process Effects 0.000 claims description 53
- 238000012360 testing method Methods 0.000 claims description 37
- 230000004888 barrier function Effects 0.000 claims description 33
- 229910021332 silicide Inorganic materials 0.000 claims description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 17
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 230000009467 reduction Effects 0.000 claims description 6
- 238000010894 electron beam technology Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 238000002360 preparation method Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 13
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 61
- 239000010410 layer Substances 0.000 description 50
- 238000000059 patterning Methods 0.000 description 31
- 238000009933 burial Methods 0.000 description 30
- 238000011049 filling Methods 0.000 description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 28
- 229910052802 copper Inorganic materials 0.000 description 28
- 239000010949 copper Substances 0.000 description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 28
- 229920005591 polysilicon Polymers 0.000 description 27
- 239000000377 silicon dioxide Substances 0.000 description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 19
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- 229910052814 silicon oxide Inorganic materials 0.000 description 18
- 230000008901 benefit Effects 0.000 description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 16
- 239000000523 sample Substances 0.000 description 15
- 229910052721 tungsten Inorganic materials 0.000 description 15
- 239000010937 tungsten Substances 0.000 description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 14
- 239000013078 crystal Substances 0.000 description 13
- 238000004380 ashing Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 238000001259 photo etching Methods 0.000 description 10
- 239000007789 gas Substances 0.000 description 9
- 239000011521 glass Substances 0.000 description 9
- 229910052759 nickel Inorganic materials 0.000 description 9
- 229910045601 alloy Inorganic materials 0.000 description 8
- 239000000956 alloy Substances 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 8
- 238000000227 grinding Methods 0.000 description 8
- 238000002513 implantation Methods 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 6
- UPSOBXZLFLJAKK-UHFFFAOYSA-N ozone;tetraethyl silicate Chemical compound [O-][O+]=O.CCO[Si](OCC)(OCC)OCC UPSOBXZLFLJAKK-UHFFFAOYSA-N 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000000149 penetrating effect Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 102000045246 noggin Human genes 0.000 description 2
- 108700007229 noggin Proteins 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910001371 Er alloy Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 241000027294 Fusi Species 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 229910001252 Pd alloy Inorganic materials 0.000 description 1
- 229910001260 Pt alloy Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910000756 V alloy Inorganic materials 0.000 description 1
- 229910000821 Yb alloy Inorganic materials 0.000 description 1
- 229910052769 Ytterbium Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 238000010237 hybrid technique Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 210000003141 lower extremity Anatomy 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05575—Plural external layers
- H01L2224/0558—Plural external layers being stacked
- H01L2224/05583—Three-layer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
- H01L2924/12032—Schottky diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明涉及一种半导体集成电路器件的制造方法。TSV技术已经作为多个半导体芯片的堆叠技术中的一种而得以普及。但是本发明人发现当利用所谓的通孔优先工艺、通孔中间工艺、正通孔通孔最后工艺等形成TSV时,可能会发生由后续工艺中的静电击穿导致的诸如栅击穿的缺陷。为了克服上述问题,本发明提供一种半导体集成电路器件的制造方法,其中通过在半导体衬底中形成孔、在空中形成绝缘构件以及在所得的空中掩埋导电构件且同时利用绝缘构件覆盖除底部之外的孔的部分来形成贯通通孔电极。
Description
相关申请交叉引用
将2012年3月26日申请的日本专利申请No.2012-069669的公开内容,包括说明书、附图和摘要,通过引用整体并入本文。
技术领域
本发明涉及一种半导体集成电路器件(或半导体器件)的制造方法,具体地涉及一种在应用于贯通通孔(through via)技术,即TSV(Through Silicon Via,贯通硅通孔)技术时有效的技术。
背景技术
日本专利特开No.2009-43779(专利文献1)或与其对应的美国专利No.7932602(专利文献2)公开了一种形成钨基贯穿电极的技术,该钨基贯穿电极穿过已经预先掩埋在硅衬底的表面区中的掩埋氧化硅膜和在掩埋氧化硅膜上的金属前绝缘膜并到达其下表面。该文献中公开的TSV技术属于通孔(via)优先工艺,即在金属前绝缘膜形成之后形成贯通通孔的工艺。
日本专利特开No.2010-186870(专利文献3)公开了一种形成贯穿电极的技术,该贯穿电极从硅衬底的背表面侧穿过硅衬底并到达金属焊盘的下表面。该文献中公开的TSV技术属于所谓的“背通孔型通孔最后(back via type via last)”工艺。
[专利文献]
[专利文献1]日本专利特开No.2009-43779
[专利文献2]美国专利No.7932602
[专利文献3]日本专利特开No.2010-186870
发明内容
TSV技术常用作堆叠多个半导体芯片等的技术。但是本发明人已经说明在使用所谓的通孔优先工艺、通孔中间(via middle)工艺、正通孔型通孔最后(front via type via last)工艺等形成TSV时,可能存在由于后续工艺中的静电击穿导致发生诸如栅极击穿的缺陷的可能性。
以下将说明用于克服上述问题的手段。从本文的描述和附图将使本发明的其他问题和新颖特征变得显而易见。
以下将简述本文公开的实施例中的一个典型实施例。
以下是本发明的一个实施例的概述:在半导体集成电路器件的制造方法中,通过在半导体衬底中形成孔、在孔中形成绝缘构件且随后在孔中埋入导电构件作为贯通通孔电极,且同时以绝缘构件覆盖除孔底部之外的孔来形成贯通通孔电极。
以下将简述从本文公开的实施例中的该典型实施例获得的有益效果。
可减小诸如栅极击穿的缺陷发生的可能性。
附图说明
图1是示出用于说明根据本发明的第一实施例(包括变型例)的半导体集成电路器件的制造方法的概要(主要是通孔中间工艺)的晶片上的局部区域的俯视图(在完成贯通通孔电极的掩埋和平坦化时);
图2是对应于图1的X-X’截面的晶片的截面图;
图3是示出根据本发明的第一实施例(包括变型例)的半导体集成电路器件的制造方法中的贯通通孔形成工艺的主要步骤的概要的工艺流程框图;
图4是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(在完成掩埋钨插塞时),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图5是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(图案化贯通通孔形成抗蚀膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图6是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图7是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成第一级布线层间绝缘膜和贯通通孔衬里绝缘膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图8是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(图案化贯通通孔底部绝缘膜以形成抗蚀膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图9是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(移除贯通通孔底部绝缘膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图10是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔阻挡金属膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图11是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋和平坦化贯通通孔主金属电极的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图12是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(图案化第一级布线沟槽以形成抗蚀膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图13是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成第一级布线沟槽的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图14是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成第一级布线阻挡金属膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图15是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋和平坦化贯通通孔电极的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺);
图16是示出整个晶片的截面示意图(在完成FEOL步骤时,即对应于图4的附图),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图17是示出整个晶片的截面示意图(第一级掩埋布线形成步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图18是示出整个晶片的截面示意图(在焊盘上的晶片的探针测试步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图19是示出整个晶片的截面示意图(在凸块上的晶片的探针测试步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图20是示出整个晶片的截面示意图(晶片裁边步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图21是示出整个晶片的截面示意图(玻璃支撑板附接步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图22是示出整个晶片的截面示意图(背面研磨步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图23是示出整个晶片的截面示意图(背面蚀刻步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图24是示出整个晶片的截面示意图(形成背侧绝缘膜和背侧焊盘的步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图25是示出整个晶片的截面示意图(安装在切割带上并移除玻璃支撑板的步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图26是示出整个晶片的截面示意图(划片且管芯键合到另一芯片上的步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图27是示出整个晶片的截面示意图(管芯键合到布线衬底上的步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺;
图28是晶片的芯片区域中的电路示意图,其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的晶片探针测试;
图29是贯通通孔的外周处的晶片的截面示意图,其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的PVC(正电压对比)测试;
图30是贯通通孔的外周处的晶片的截面示意图,其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的NVC(负电压对比)测试;
图31是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1并对应于图9的截面示意图(引入贯通通孔底部重掺杂区的步骤),其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的通孔底部的接触电阻的提升;
图32是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1并对应于图9的截面示意图(引入贯通通孔底部硅化层的步骤),其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的通孔底部的接触电阻的提升;
图33是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1并对应于图15的截面示意图(掩埋并平坦化贯通通孔电极的步骤),其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的通孔底部的接触电阻的提升;
图34是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(在完成最上级掩埋布线形成步骤时),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺);
图35是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(图案化贯通通孔以形成抗蚀膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺);
图36是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺);
图37是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔衬里绝缘膜和贯通通孔阻挡金属膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺);
图38是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋并平坦化贯通通孔电极的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺);
图39是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(最终钝化步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺);
图40是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺);
图41是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔衬里绝缘膜并蚀刻的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺);
图42是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋并平坦化贯通通孔电极的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺);
图43是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成栅绝缘膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺);
图44是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(栅绝缘膜蚀刻步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺);
图45是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(栅电极膜形成步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺);
图46是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(加工栅电极膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺);
图47是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(贯通通孔形成步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺);
图48是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔衬里绝缘膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺);
图49是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(移除贯通通孔底部绝缘膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺);
图50是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔阻挡金属膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺);
图51是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋并平坦化贯通通孔电极的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺);
图52是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成接触孔的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺);
图53是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成金属插塞阻挡金属膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺);
图54是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋并平坦化导电插塞的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。
具体实施方式
[实施例概要]首先将说明本文公开的典型实施例。
1.一种半导体集成电路器件的制造方法,包括以下步骤:(a)制备具有器件主表面和背表面的半导体晶片;(b)从半导体晶片的器件主表面至半导体晶片的半导体表面区形成多个到达其内部的孔;(c)在孔的内表面上形成绝缘膜;以及(d)在步骤(c)之后,在孔中掩埋导电构件,同时利用绝缘膜覆盖除孔底部之外的孔的内表面,且由此形成多个贯通通孔电极。
2.如上述1中所述的半导体集成电路器件的制造方法,还包括步骤:(e)在晶片加工中,将至少一个贯通通孔电极电耦合至栅电极。
3.如上述1或2中所述的半导体集成电路器件的制造方法,其中利用通孔中间工艺形成贯通通孔电极。
4.如上述3中所述的半导体集成电路器件的制造方法,其中在形成第一级布线的步骤中但在不同于掩埋第一级布线的时刻掩埋贯通通孔电极。
5.如上述3中所述的半导体集成电路器件的制造方法,其中在掩埋第一级布线的同时掩埋贯通通孔电极。
6.如上述1或2中所述的半导体集成电路器件的制造方法,其中利用通孔最后工艺形成贯通通孔电极。
7.如上述6中所述的半导体集成电路器件的制造方法,其中在形成除焊盘层之外的最上级布线的步骤期间形成贯通通孔电极。
8.如上述7中所述的半导体集成电路器件的制造方法,其中至少一个贯通通孔电极通过属于焊盘层的布线电耦合至焊盘。
9.如上述1至8中任一项所述的半导体集成电路器件的制造方法,还包括步骤:(f)在步骤(d)之后但在晶片加工期间,对晶片的器件主表面照射电子束以测试贯通通孔电极的导电状态。
10.如上述1、2或9中所述的半导体集成电路器件的制造方法,其中利用通孔优先工艺形成贯通通孔电极。
11.如上述10中所述的半导体集成电路器件的制造方法,其中在栅电极形成步骤中但在不同于形成栅电极膜的时刻执行贯通通孔电极的掩埋。
12.如上述10中所述的半导体集成电路器件的制造方法,其中在栅电极膜形成的同时执行贯通通孔电极的掩埋。
13.如上述10中所述的半导体集成电路器件的制造方法,其中在接触形成步骤中当在不同于形成接触插塞的时刻执行贯通通孔电极的掩埋。
14.如上述10中所述的半导体集成电路器件的制造方法,其中在接触插塞形成的同时执行贯通通孔电极的掩埋。
15.如上述1至14中任一项所述的半导体集成电路器件的制造方法,其中至少在步骤(d)之后,各个贯通通孔电极的下端附近的半导体区具有重掺杂区,其导电类型与其周围的半导体区的导电类型相同并具有高杂质浓度。
16.如上述1至15中任一项所述的半导体集成电路器件的制造方法,其中贯通通孔电极具有阻挡金属结构,其外层为钛膜且内层为氮化钛膜。
17.如上述1至16中任一项所述的半导体集成电路器件的制造方法,其中各个贯通通孔电极的下端及其附近的半导体区之间具有金属硅化物层。
18.如上述1至17中任一项所述的半导体集成电路器件的制造方法,还包括步骤:(g)在步骤(d)之后,从半导体晶片的背表面侧对半导体晶片进行膜减薄处理以暴露半导体晶片的背表面侧上的贯通通孔电极。
19.如上述18中所述的半导体集成电路器件的制造方法,还包括步骤:(h)在步骤(g)之后,贯通通孔电极耦合至另一半导体衬底上提供的凸块电极。
[对本文的说明方式、基本术语以及用途的解释]
1.在本申请中,为方便起见,如果需要则在分成多个部分之后对实施例进行说明。这些部分不彼此独立,除非另外规定,否则,它们每一个可以是单个示例的一部分,或它们中的一个可以是另一的部分细节或另一个的整体或一部分的变型例。原则上,对相似部分不进行重复说明。在实施例中,当涉及构成元件时,除非另外规定、限于理论上的数字或原则上不是从上下文显而易见的情况,否则不是必不可少的。
此外,在本发明中,术语“半导体器件”或“半导体集成电路器件”主要是指集成在半导体芯片(例如单晶硅衬底)等上的各种晶体管(有源元件)单元、具有晶体管单元作为主要部件的器件、电阻器、电容器等以及封装的半导体芯片。各种晶体管的典型示例可以包括以MOSFET(金属氧化物半导体场效应晶体管)为代表的MISFET(金属绝缘体半导体场效应晶体管)。在这种情况下,集成电路构造的典型示例可以包括以具有N沟道型MISFET和P沟道型MISFET组合的CMOS(互补金属氧化物半导体)型集成电路为代表的CMIS(互补金属绝缘体半导体)型集成电路。
现代半导体集成电路器件的晶片加工,即LSI(大规模集成)可通常分成两步。第一步是从装载作为原料的硅晶片至金属前步骤的FEOL(线前端)步骤(包括M1布线层的下边缘和栅极结构之间的层间绝缘膜的形成、接触孔的形成、钨插塞的掩膜等的步骤)。第二步是从M1布线层的形成至在铝基焊盘电极上对于最终钝化膜的焊盘开口的形成的BEOL(线后端)步骤(在晶片级封装工艺中也可包括该工艺)。
2.类似地,在实施例等的说明中,当关于材料、组分等使用“X由A制成”等时,除非具体规定或原则上不能从上下文显而易见,否则主构成元素不排除除A之外的成分。例如,对于成分来说,上述句子是指“X包含A作为主要成分”。例如,显而易见,术语“硅构件”等不仅是指由纯硅制成的构件,还指包含SiGe合金、具有硅作为主要成分或添加剂的另一多元素合金的构件。
类似地,术语“氧化硅膜”、“氧化硅绝缘膜”等不仅是指由相对纯的非掺杂氧化硅(非掺杂二氧化硅)制成的绝缘膜,还指具有氧化硅作为主要成分的其他绝缘膜。氧化硅膜的示例包括杂质掺杂氧化硅基绝缘膜,诸如TEOS基氧化硅,PSG(磷硅酸盐玻璃)以及BPSG(硼磷硅玻璃)膜。此外,热氧化膜、CVD氧化膜、通过应用诸如SOG(旋涂玻璃)和NCS(nano-clustering silica,纳米簇二氧化硅)膜的方法获得的膜也涵盖在氧化硅膜或氧化硅基绝缘膜的范围内。此外,诸如FSG(氟硅酸盐玻璃)、SiOC(碳氧化硅)、碳掺杂氧化硅以及OSG(有机硅酸盐玻璃)膜的低k绝缘膜也涵盖在氧化硅膜或氧化硅基绝缘膜的范围内。而且,通过在类似于上述材料的构件中引入孔而获得的二氧化硅基低k绝缘膜(多孔绝缘膜)也涵盖在氧化硅膜或氧化硅基绝缘膜的范围内。
此外,像氧化硅基绝缘膜这样常用于半导体领域中的硅基绝缘膜是氮化硅基绝缘膜。属于这一类的材料包括SiN、SiCN、SiNH以及SiCNH。除非另外规定,否则本文所用的术语“氮化硅”包括SiN和SiNH。类似地,除非另外规定,本文所用的术语“SiCN”包括SiCN和SiCNH。
顺便提及,SiC的性质类似于SiN,但SiON往往被分类为氧化硅基绝缘膜。
氮化硅膜在SAC(自对准接触)技术中不仅主要用作蚀刻停止膜,即用作CESL(接触蚀刻停止层),而且还在SMT(应力记忆技术)中用作应力施加膜。
同样地,术语“硅化镍”通常是指镍单晶硅化物,但其不仅包括相对纯的镍单晶硅化物,还包括各包含镍单晶硅化物作为主要成分的合金、混合晶体等。而且,硅化物不限于硅化镍,而还可以是常规使用的硅化钴、硅化钛、硅化钨等。对于硅化的金属膜来说,不仅可采用Ni(镍)膜,而且可采用诸如Ni-Pt合金膜(Ni和Pt的合金膜)、Ni-V合金膜(Ni和V的合金膜)、Ni-Pd合金膜(Ni和Pd的合金膜)、Ni-Yb合金膜(Ni和Yb的合金膜)或Ni-Er合金膜(Ni和Er的合金膜)的镍合金膜。注意到包含镍作为其主要金属元素的上述硅化物统称为“镍基硅化物”。
3.类似地,示出形状、位置、属性等的优选示例,但除非具体规定或原则上不能从上下文显而易见,否则形状、位置、属性等不严格限于优选示例。
4.此外,当涉及具体数字或量时,除非具体规定、理论上限于具体数字或量或不能从上下文显而易见,否则数字或量可大于或小于具体数字或量。
5.术语“晶片”是指其上要形成半导体集成电路器件(以及半导体器件或电子器件)的单晶硅晶片,但显然还包括外延晶片以及半导体层和诸如SOI衬底或LCD玻璃衬底的绝缘膜衬底的复合晶片。
6.对于TSV的形成工艺的分类来说,主要在FEOL步骤期间形成TSV的工艺被称为“通孔优先工艺”,主要在BEOL步骤期间形成TSV的工艺被称为“通孔中间工艺”且主要在BEOL步骤之后且堆叠之前形成TSV的工艺被称为“堆叠后工艺”。在本发明中,如下对TSV形成工艺进行分类,其基本上对应于上述的一种。首先,根据TSV的形成时刻,工艺被粗略分成“通孔优先工艺”、“通孔中间工艺”、“通孔最后工艺”以及“堆叠后工艺”。
在通孔优先工艺中,诸如TSV的贯通通孔在第一级布线层间绝缘膜形成之前形成;在通孔中间工艺中,在完成金属前区之后且在除焊盘层之外的最上级布线层完成之前形成贯通通孔;在通孔最后工艺中,在上述工艺后且在堆叠之前形成贯通通孔;且在堆叠后工艺中,在堆叠后形成贯通通孔。
此外,从晶片的表面侧形成的贯通通孔被称为“正通孔”,而从晶片的背侧形成的贯通通孔被称为“背通孔”。
特别在区分晶片减薄前形成的贯通通孔与在晶片减薄后形成的贯通通孔时,前者被称为“贯通通孔在先”或“贯通通孔在先型”。在以下实施例中,主要说明属于“贯通通孔在先正通孔型”的通孔。
此外,采用多晶硅等作为贯通通孔的主要填充构件的通孔优先工艺被称为“通孔优先多晶硅工艺”,而类似于接触孔的采用钨作为填充构件的通孔优先工艺被称为“通孔优先接触工艺”。
7.本文所用的术语“TSV”、“贯通通孔”、“贯通通孔电极”等,是指已被穿透或应被穿透的构件,除非这两者之间应当区分,因为步骤期间以另一名称称谓构件会造成不必要的混淆。显然用于“TSV”、“硅贯通通孔”等的衬底不限于硅基晶片等。
[实施例的详细说明]以下将更具体说明实施例。在所有附图中,相同或相似的构件将由相同或相似的标记或附图编号表示,且原则上将省略重复的说明。
而且,在所有附图中,当影线等会使附图复杂化或与空白部分的区别很明显时,有时甚至在截面图中也省略掉影线。在这点上,即使在从说明书等中显而易见地得知孔在俯视图中明显封闭时,有时可省略背景的轮廓。此外,即使在不是截面图的情况下也可以应用影线,以便清晰示出不是空白部分。
当两者处于交替关系且一者被称为“第一”等且另一者被称为“第二”等时,可基于典型实施例确定对应关系。但是显然当某一构件例如被称为“第一”构件时,其不限于这种选择。
1.根据本发明第一实施例(包括变型例)(主要是图1至3)的半导体集成电路器件的制造方法的概要的说明(主要是通孔中间工艺)
以下具体参考硅基CMIS型半导体集成电路器件(即MOS型半导体集成电路器件)作为示例进行说明。但是显然双极半导体集成电路器件或另一器件也可用作示例。
这部分主要说明通孔中间工艺,其在部分2至6中被采用,但显然本部分可应用至通孔最后工艺或通孔优先工艺。
贯通通孔的深度(例如约50μm且通常处于约10至100μm的范围内)通常比诸如阱(通常为亚微米级)的杂质掺杂区的深度深得多,因此在附图中,除非必要,否则原则上省略杂质掺杂区。此外,栅极外围的结构,诸如侧壁,也从图中省略。
图1是示出晶片上的局部区域(在完成贯通通孔电极的掩埋和平坦化时)的俯视图,用于说明根据本发明的第一实施例(包括变型例)的半导体集成电路器件的制造方法的概要(主要是通孔中间工艺)。图2是对应于图1的X-X’截面图的晶片的截面图。图3是示出根据本发明的第一实施例(包括变型例)的半导体集成电路器件的制造方法中的贯通通孔形成工艺的主要部分的概要的工艺流程框图。将基于上述附图说明根据本发明第一实施例的半导体集成电路器件的制造方法的概要(主要是通孔中间工艺)。
图1示出在根据第一实施例的半导体集成电路器件的制造方法中完成主晶片加工处理时的晶片1的芯片区2的部分(具有贯通通孔及其外围电路的区域)的俯视图。在图1的右侧,呈现出多个基本上圆形的贯通通孔电极9的上端部。另一方面,左侧呈现出多个第一级掩埋布线8。另一部分是第一级布线层间绝缘膜12,其例如由氧化硅基绝缘膜制成。
贯通通孔电极9(其还未成为贯通通孔)由例如铜构件制成的贯通通孔主金属电极9a和例如氮化钛制成的贯通通孔阻挡金属膜9b构成。类似地,第一级掩埋布线8由例如铜构件制成的第一级铜布线膜8a和例如氮化钛制成的第一级布线阻挡金属膜8b构成。
图2中示出图1的X-X’截面。如图2中所示,半导体晶片1(例如具有约700μm的厚度)在半导体衬底部1s(P型单晶硅衬底)的表面1a(器件表面或第一主表面)上(即背表面1b的相反侧上)具有通过STI区3等彼此隔离的N沟道MISFET(Qn)和P沟道MISFET(Qp)。N沟道MISFET(Qn)和P沟道MISFET(Qp)都具有经由栅绝缘膜4提供的栅极5(例如栅多晶硅膜)。提供在半导体衬底部1s的表面1a侧上的半导体区中的P阱区WP在其表面中具有N沟道MISFET(Qn)的N型源漏区DN。另一方面,提供在半导体衬底部1s的表面1a侧上的半导体区中的N阱区WN在其表面中具有P沟道MISFET(Qp)的P型源漏区DP。
半导体衬底部1s在其表面1a中具有金属前绝缘膜6(例如具有约300nm的厚度)且其例如由作为下层的主金属前绝缘膜6a和作为上层的帽盖层金属前绝缘膜6b构成。主金属前绝缘膜6a例如由作为下层的相对薄的氮化硅基绝缘膜(例如氮化硅膜)和作为上层的相对厚的氧化硅基绝缘膜(例如臭氧TEOS基氧化硅膜)构成。帽盖层金属前绝缘膜6b例如由氧化硅基绝缘膜(例如等离子体TEOS基氧化硅膜)构成。
金属前绝缘膜6具有掩埋其中的导电插塞7,且该导电插塞穿过该绝缘膜并到达栅极5、N型源漏区DN、P型源漏区DP等。导电插塞7由主金属插塞7a(例如钨插塞)、金属插塞阻挡金属膜7b(例如氮化钛膜)等构成。金属前绝缘膜6上具有第一级布线层间绝缘膜12(例如具有约200nm厚度的臭氧TEOS基氧化硅膜)且该第一级布线层间绝缘膜中具有耦合至导电插塞7等的第一级掩埋布线8。
如图1中所示,在本示例中,金属前绝缘膜6中具有多个贯通通孔16,它们穿过金属前绝缘膜6并到达半导体衬底部1s内部。这些贯通通孔具有经由贯通通孔衬里绝缘膜11而掩埋其中的贯通通孔电极9。顺便提及,在本示例中,贯通通孔衬里绝缘膜11是与第一级布线层间绝缘膜12相同的层,且它们同时形成,但这并不是必要条件。贯通通孔16例如由作为内层的贯通通孔主金属电极9a(例如具有铜作为主要成分的金属构件)和作为侧面和底层的贯通通孔阻挡金属膜9b(例如氮化钛膜)构成。通常,至少一个贯通通孔电极9经由栅极-贯通通孔电极布线14电耦合到至少一个栅极5。栅极-贯通通孔布线14由栅极5、每一层的布线,或者它们的组合构成。
在本示例中,此时,贯通通孔16在其通孔底部16b处还不具有贯通通孔衬里绝缘膜11,因此贯通通孔电极9和半导体衬底部1s(P型单晶硅衬底)基本上彼此电耦合(欧姆接触或肖特基结)以防止出现大的电势差。因此在制造步骤期间,贯通通孔16好像接地至半导体衬底部1s,使得能防止出现由贯通通孔16的不希望的充电而导致的栅击穿等。
以下在图3中示出用于实现这种结构的制造方法的概要(参考图2)。如图3中所示,以下是制造方法的概要。(1)在半导体表面区中形成从晶片1的表面1a侧延伸至其内部的多个孔。(2)随后,在孔的内表面上形成绝缘膜。(3)在步骤(2)之后,在孔中掩埋导电构件,同时利用绝缘膜覆盖除底部之外的孔的内表面(换言之,不覆盖底部的至少一部分)以形成多个贯通通孔电极。
通过采用上述方法,在从开始在贯通通孔中掩埋导电构件直至通过背面研磨(晶片的减薄)移除贯通通孔的底部期间,所有贯通通孔电极9和半导体衬底部1s基本上都彼此电耦合。
2.对根据第一实施例的半导体集成电路器件的制造方法中直到完成通孔填充的工艺(通孔中间工艺)的局部说明(主要参考图4至图15)。
此处所示出的工艺是一个示例,且显然可以变更各个元件工艺。除非规定为必要或除非显然必要,否则各个元件工艺不是必不可少的。这也适用于第三部分中所述的各个元件。显然,部分3至6中所示的其他元件不是必须而是任意的。
图4是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(在完成掩埋钨插塞时),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图5是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(图案化贯通通孔以形成抗蚀膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图6是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图7是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成第一级布线层间绝缘膜和贯通通孔衬里绝缘膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图8是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(图案化用于移除贯通通孔底部绝缘膜的抗蚀膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图9是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(移除贯通通孔底部绝缘膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图10是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔阻挡金属膜的步骤),其用于部分说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图11是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋和平坦化贯通通孔主金属电极的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图12是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(图案化第一级布线沟槽以形成抗蚀膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图13是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成第一级布线沟槽的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图14是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成第一级布线阻挡金属膜的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。图15是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋和平坦化贯通通孔电极的步骤),其用于局部说明根据本发明的第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充时的工艺(通孔中间工艺)。基于上述附图,对根据本发明第一实施例的半导体集成电路器件的制造方法中直至完成了通孔填充的工艺(通孔中间工艺)进行局部说明。
图4中示出例如根据典型CMIS工艺的完成金属前步骤时的器件截面结构。在图4或其后的附图中,与图2不同,原则上省略半导体衬底中的杂质掺杂区,以便防止附图变得复杂。
随后,如图5中所示,在器件表面1a侧上,在晶片1的几乎所有表面上形成贯通通孔形成抗蚀膜15(例如具有5μm的厚度),之后例如通过典型光刻进行图案化。
随后,如图6中所示,利用图案化的贯通通孔形成抗蚀膜15作为掩膜,执行各向异性干蚀刻以形成基本上具有圆形平面形状的贯通通孔16(具有约10μm的顶部直径以及约50μm的深度)。换言之,形成到达半导体晶片的半导体表面区的内部的多个孔(贯通通孔16)。随后例如通过灰化移除变成不必要的抗蚀膜。贯通通孔16的内侧面16i可以是垂直或向底部略微渐缩的。
随后,如图7中所示,在器件表面1a侧上的晶片1的几乎所有表面上,例如通过CVD来形成氧化硅基绝缘膜(例如,具有例如约200nm厚度的臭氧TEOS膜),以形成贯通通孔衬里绝缘膜11和第一级布线层间绝缘膜12。
随后,如图8中所示,形成贯通通孔底部绝缘膜移除抗蚀膜17(例如具有约1μm的厚度),随后例如通过典型光刻进行图案化。
随后,如图9中所示,利用图案化的抗蚀膜17作为掩膜,进行各向异性干蚀刻,来从贯通通孔底部16b移除绝缘膜。随后例如通过灰化移除变成不必要的抗蚀膜。
随后,如图10中所示,例如通过采用MOCVD(金属有机CVD)或溅射(例如,电离溅射)在器件表面侧1a上的晶片1的几乎所有表面上形成氮化钛膜(例如具有约30nm的厚度)作为贯通通孔阻挡金属膜9b。之前的示例包括TDMAT(四(二甲基氨)钛)以及TDEAT(四(二乙基氨)钛),其也类似地应用于下述MOCVD中。通过采用溅射形成的膜的优点是不会混入碳,而MOCVD的优点是即使在深孔的情况下也能形成较均匀的膜。
随后,如图11中所示,例如通过采用溅射(例如,电离溅射)在器件表面1a侧上以及贯通通孔阻挡金属膜9b上的晶片1的整个表面(包括贯通通孔16的内表面)上形成铜籽晶膜。随后,利用铜籽晶膜作为籽晶层进行电镀以在器件表面1a侧上的晶片1的整个表面(包括贯通通孔16的内表面)上形成铜膜(包括籽晶膜),由此填充贯通通孔16。随后进行金属CMP以移除贯通通孔16外部的铜膜和贯通通孔阻挡金属膜9b,从而形成由贯通通孔主金属电极9a(铜膜)和贯通通孔阻挡金属膜9b构成的贯通通孔电极9。这意味着通过在多个孔的内表面上形成绝缘膜且利用导电构件填充孔,而同时覆盖除孔底部之外的孔的内表面,而形成了多个贯通通孔电极。注意到在任意步骤中,至少一个贯通通孔电极电耦合至栅电极。
随后,如图12中所示,在器件表面1a一侧上的晶片1的整个表面上形成第一级布线沟槽形成抗蚀膜18(例如具有1μm的厚度),随后例如通过典型光刻进行图案化。
随后,如图13中所示,利用图案化的抗蚀膜18作为掩膜执行各向异性干蚀刻以形成第一级布线沟槽47。随后例如通过灰化移除变成不必要的抗蚀膜。
随后,如图14中所示,例如通过溅射在器件表面1a侧上的晶片1的几乎整个表面(包括第一级布线沟槽47的内表面)上形成氮化钛膜(例如具有约10nm的厚度)作为第一级布线阻挡金属膜8b。
随后,如图15中所示,例如通过采用溅射在器件表面1a侧上的晶片1的整个表面上(包括第一级布线沟槽47的内表面)形成铜籽晶膜。随后进行电镀以形成膜来填充第一级布线沟槽47。例如,进行CMP(化学机械抛光)以平坦化器件表面1a侧的晶片1,且移除第一级布线沟槽47外部的第一级布线阻挡金属膜8b以及包括了铜籽晶膜的铜膜。因此,完成由第一级铜布线膜8a和第一级布线阻挡金属膜8b构成的第一级掩埋布线8。
在下一部分中将更全面说明本部分中所述的工艺及其后续工艺。
已经在上文具体说明了下述工艺(不同时工艺),其中,主要在第一级布线形成步骤中,在不同时刻进行第一级布线的掩埋以及贯通通孔电极的掩埋。显然可采用下述工艺(同时进行的工艺),其中同时进行如图12至15中所示的第一级布线的掩埋以及贯通通孔电极的掩埋。不同时工艺的优点是容易实现工艺,而同时工艺的优点是可简化工艺步骤。
3.对根据本发明第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺的整体说明(主要参考图16至图27)。
将通过B2F(背面对正面)键合的D2D(管芯-管芯)键合作为示例,具体说明半导体衬底的键合或堆叠方法,但是显然也可替代采用F2F(面对面)键合。对于堆叠方法来说,显然可采用W2W(晶片-晶片)堆叠或D2W(管芯-晶片)堆叠。这种W2W方法包括通过在晶片或类似晶片的衬底上重排列已知的良好的管芯而获得的重配置晶片。类似地,B2F键合F2F键合可应用至W2W堆叠或D2W堆叠。
在以下说明中,以焊接键合作为一个示例来具体说明衬底的键合,但显然可采用借助锡-铜金属间的键合或借助诸如铜、银或金的另一金属的键合。
图16是示出整个晶片的截面示意图(在完成FEOL步骤时,即对应于图4的视图),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图17是示出整个晶片的截面示意图(第一级掩埋布线形成步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图18是示出整个晶片的截面示意图(在焊盘上的晶片的探针测试步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图19是示出整个晶片的截面示意图(在凸块上的晶片的探针测试步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图20是示出整个晶片的截面示意图(晶片裁边步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图21是示出整个晶片的截面示意图(玻璃支撑板附接步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图22是示出整个晶片的截面示意图(背面研磨步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图23是示出整个晶片的截面示意图(背面蚀刻步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图24是示出整个晶片的截面示意图(形成背侧绝缘膜和背侧焊盘的步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图25是示出整个晶片的截面示意图(安装在切割带上并移除玻璃支撑板的步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图26是示出整个晶片的截面示意图(划片且管芯键合到另一芯片上的步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。图27是示出整个晶片的截面示意图(管芯键合到布线衬底上的步骤),其用于整体说明根据本发明的第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺。以下,基于上述附图,对根据本发明第一实施例的半导体集成电路器件的制造方法中在完成FEOL步骤之后的工艺进行整体说明。
从更全面的视角将图4示出为图16。图16至图27(以及图28)省略了除了与贯通通孔和贯通通孔电极有直接关系的结构之外的半导体衬底中的结构(例如杂质掺杂区和STI区),以便避免复杂化附图。
随后,如图17中所示,如部分2中所述形成贯通通孔电极9。随后,根据需要,例如在导电插塞7上形成第一级掩埋布线8的同时在贯通通孔电极9上形成第一级掩埋布线8。
随后,如图18中所示,根据需要在第一级布线层间绝缘膜12上形成多层中间级掩埋布线19(例如通过双镶嵌工艺制成的铜基掩埋布线),多层中间级掩埋布线19掩埋在主要由氧化硅基绝缘膜(例如低k多孔SiOC基氧化硅膜)制成的中间级和上级层间绝缘膜21中。随后,除了掩埋在中间级和上级层间绝缘膜21中的焊盘层之外,在中间级掩埋布线19上形成最上级布线22(最上级掩埋布线,例如,通过双镶嵌工艺形成的铜基掩埋布线)。这里,第一级布线层间绝缘膜12、中间级和上级层间绝缘膜21等构成布线层间绝缘膜20。随后,在最上级布线22上的布线层间绝缘膜20中,例如掩埋钨插塞23作为上层。随后,在布线层间绝缘膜20上形成电极焊盘24p(例如铝焊盘),并且在其上除焊盘开口之外的部分由最终钝化膜25覆盖。最终钝化膜25的优选示例包括氧化硅基绝缘膜和氮化硅基绝缘膜及其复合膜(统称为“无机最终钝化膜”)。有机最终钝化膜(例如聚酰亚胺基树脂膜)可形成在无机最终钝化膜上。随后,例如使探针51与电极焊盘24p接触以执行晶片探针测试。显然该测试不是必需的。
随后,如图19中所示,诸如铜凸块电极的金属凸块电极26例如通过电镀并经由UBM(下凸块金属)层形成在电极焊盘24p上。随后,在铜凸块电极26上,例如通过电镀等形成焊料阻挡金属膜27(例如镍膜)。随后,在焊料阻挡金属膜27上,通过电镀等形成诸如无铅焊料的焊料层28(例如锡银基焊料)。随后,使探针51接触焊料层28以执行晶片探针测试。显然该测试不是必需的。
随后,如图20中所示,根据需要执行器件表面1a侧上的晶片1的裁边。
随后,如图21中所示,支撑衬底31(例如玻璃支撑晶片)经由粘附层29附接至晶片1的器件表面1a侧。
随后,如图22中所示,在晶片上具有支撑衬底31的情况下,对晶片1的背表面1b(第二主表面)进行诸如背面研磨处理的膜减薄处理,从而暴露贯通通孔电极9的下端部,更精确地说,贯通通孔主金属电极9a的下端部。通过此处进行的膜减薄处理,晶片的厚度被降至接近于最终晶片的目标厚度的值。因此研磨量等于晶片的原始厚度(例如约700μm)减去晶片的目标厚度(例如约50μm)获得的差。
随后,如图23中所示,例如通过采用干蚀刻(采用卤素基气体作为气体系统),略微蚀刻晶片1的背表面1b侧上的硅衬底,而使贯通通孔电极9等从晶片1的背表面1b略微突出。这种蚀刻是所谓的背面蚀刻。
随后,如图24中所示,在背表面1b侧上的晶片1的几乎整个表面上涂布诸如聚酰亚胺的树脂膜作为背面绝缘膜32,随后通过CMP或回蚀对其平坦化并再次暴露贯通通孔电极9的下端部。随后,例如通过溅射,在背表面1b侧上的晶片1的几乎整个表面上,从晶片1侧起依次形成例如钛膜、铜膜、镍膜等。随后例如通过湿蚀刻图案化所得的膜叠层以形成背面焊盘33。随后,通过将晶片暴露至穿过支撑衬底31的紫外光来降低粘附层29的粘附力,以从晶片1的表面1a(器件表面)移除支撑衬底31和粘附层29。
随后,如图25中所示,晶片1(1x)的背表面1b附接至切割带34,切割带34附接至切割框架。在这种状态下,例如通过划片将晶片1(1x)分割成独立的芯片区。
随后,如图26中所示,例如通过焊料键合,以类似方式将分割的芯片2(2x)的背表面1b上的背侧焊盘33键合到另一芯片2(2y)的器件表面1a上的凸块电极30。通过该键合,多个贯通通孔电极耦合至提供在另一半导体衬底上的凸块电极。
随后,如图27中所示,例如通过焊料键合(是指倒装芯片键合),使芯片2(2x)的器件表面1a上的凸块电极30和多层布线衬底35的上表面上的上焊垫(land)36彼此耦合。随后,例如通过回流,使外部焊料凸块电极38(焊球)附接至多层布线衬底35的下表面上的下焊垫37。因此几乎完成BGA(球栅阵列)。
4.对根据本发明第一实施例的半导体集成电路器件的制造方法中的晶片探针测试进行补充说明(图28)。
这部分说明了用于克服在制造中每次都在晶片探针测试中可能发生的问题的额外技术。因此这种方法不是必需的。
图28是晶片的芯片区中的电路示意图,其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的晶片探针测试。基于该附图,将对根据本发明第一实施例的半导体集成电路器件的制造方法中的晶片探针测试进行补充说明。
在上文说明的实施例中(例如图18或图19),几乎所有的贯通通孔电极9都与晶片1的衬底区1s具有连结性。当某些贯通通孔电极9电耦合至用于晶片探针测试的电极(电极焊盘24p或凸块电极30)且该电极是数据输入电极时,有时不能进行测试。
以下将说明用于避免这种不便之处的方法的示例。假设如图28中所示,例如输出电极焊盘24pg、数据输入电极焊盘24pi等电耦合至该芯片2的LSI内部电路IC且该数据输入电极焊盘24pi例如经由输入/输出电路IF耦合至贯通通孔电极9x和9y中的一个。当数据输入电极焊盘耦合至贯通通孔电极9x时,即使数据输入至数据输入电极焊盘24pi,有时也不能正常测试,因为例如处于接地电势的半导体衬底部1s会产生影响。
在本示例中,为了避免这种情况,例如在LSI内部电路IC和输入/输出电路IF之间插入开关或开关电路SW以通过来自开关控制电极焊盘24ps(通常处于接通状态)的信号而断开。这就能进行正常探针测试。
5.对根据本发明第一实施例的半导体集成电路器件的制造方法中的VC(电压对比)测试进行补充说明(主要参考图29和30)
在本部分中,对通过采用电子束等进行的贯通通孔电极的导电测试进行说明,该测试例如在部分2中的图11的步骤中进行(在完成贯通通孔填充时)。
图29是贯通通孔的外周处的晶片的截面示意图,其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的PVC测试(正电压对比)。图30是贯通通孔的外周处的晶片的截面示意图,其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的NVC测试(负电压对比)。基于上述附图,将在下文对根据本发明第一实施例的半导体集成电路器件的制造方法中的VC(电压对比)测试进行补充说明。
(1)PVC测试的说明(主要参考图29)
该电压对比测试可粗略分成两种类型。一种是PVC(正电压对比)测试,其中晶片1的表面1a侧被正充电,而另一种是NVC(负电压对比)测试,其中晶片1的表面1a侧被负充电。首先说明PVC测试。
在PVC测试中,如图29中所示,当贯通通孔电极9n正常时,从半导体衬底部1s向其提供电子,以便不发生充电且电极看上去明亮。另一方面,当贯通通孔电极9d处于非导电状态时,没有从半导体衬底部1s向其提供电子,因此发生充电且电极看上去暗淡。
因此,因为在制造步骤中,所有贯通通孔电极的底部都基本上电耦合至半导体衬底部1s,这就能在完成贯通通孔电极的掩埋之后的非常短的阶段内容易地在非正常贯通通孔电极和正常贯通通孔电极之间区分。这也完全适用于以下NVC测试。
(2)对NVC测试的说明(主要参考图30)
在NVC测试中,如图30中所示,贯通通孔电极9n正常且从半导体衬底部1s向其提供电子,因此没有充电且电极看上去暗淡。另一方面,当贯通通孔电极9d处于非导电状态时,没有对其提供电子,因此进行充电且电极看上去明亮。
(3)这些测试的适当时刻
这些测试的适当时刻的示例在部分2中的图11、图38、图42以及图51(都在完成通孔填充时)中所示。因此,通过将晶片的器件表面暴露到电子束,能就在完成后(无须等待后续步骤)相对容易地测试许多(多个)贯通通孔电极的导电状态。
6.对根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔底部处的接触电阻的改善的补充说明(主要参考图31至图33)。
这部分说明已经在上文提及的用于进一步提高贯通通孔电极9和半导体衬底部1s之间的电耦合状态的额外方法。
图31是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1并对应于图9的截面示意图(引入贯通通孔底部重掺杂区的步骤),其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的通孔底部的接触电阻的提升。图32是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1并对应于图9的截面示意图(引入贯通通孔底部硅化层的步骤),其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的通孔底部的接触电阻的提升。图33是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1并对应于图15的截面示意图(掩埋并平坦化贯通通孔电极的步骤),其用于补充说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的通孔底部的接触电阻的提升。基于上述附图对根据本发明第一实施例的半导体集成电路器件的制造方法中的通孔底部处的接触电阻的改善进行补充说明。
(1)对贯通通孔底部引入重掺杂区进行说明(主要参考图31)
如图31中所示,例如在完成从图9中所示的贯通通孔底部16b移除绝缘膜的阶段,例如通过离子注入,从晶片1的器件表面1a将浓度高于半导体衬底部的杂质浓度的p型杂质(例如硼)引入半导体衬底部1s(例如p型硅衬底)。以下是注入条件的规范示例:注入角度:基本上直角,剂量:例如约1×1015/cm2,且注入能量:例如约50KeV。通过在贯通通孔底部16b处在半导体衬底部1s中提供重掺杂区39,可在贯通通孔电极9和半导体衬底部1s之间形成欧姆接触。
可利用诸如树脂膜的图案执行离子注入。或者,可以在不采用抗蚀膜的情况下以自对准方式执行离子注入,且在这种情况下,工艺会变得更简单。另一方面,采用抗蚀膜提高工艺的自由度。
如图8中所示,可在贯通通孔底部具有绝缘膜的同时执行离子注入。但是在这种情况下需要略高的注入能量。这种方法也具有简化工艺的优点。
如图9中所示,还能在贯通通孔底部上具有牺牲氧化膜的同时执行离子注入。其优点是排除了污染物的引入。
当半导体衬底部1s是N型时,要引入的杂质是N型,例如磷或砷。
如上所述,根据这种工艺,因为至少在完成贯通通孔填充时(例如图11),在各个贯通通孔电极的下端附近,具有与衬底部相同导电类型并被重掺杂的区域形成在半导体衬底部中,因此各个贯通通孔电极和半导体衬底部都具有良好接触。
(2)对贯通通孔底部引入金属硅化膜的说明(主要参考图32)
在图31的步骤之后,如图32中所示,通过在重掺杂区39的表面上形成金属硅化膜46(其材料的示例包括镍基硅化物、硅化钨、硅化钴以及铂基硅化物)而进一步降低接触电阻。因为金属硅化物层形成在各个贯通通孔电极及其附近的半导体区之间,因此其具有改善两者之间的相互接触的优点。
(3)对贯通通孔的内表面上的阻挡金属膜的详细结构的变型例的说明(主要参考图33)
如图33中所示,例如在完成从图9中的贯通通孔底部16b移除绝缘膜之后且在形成贯通通孔阻挡金属膜9b之前,例如通过溅射在器件表面1a侧上的晶片1的几乎整个表面上形成相对薄的钛膜9c(例如具有10nm的厚度),即图10中所示的氮化钛膜。通过采用作为外部膜的钛膜以及作为内部膜的氮化钛膜来形成阻挡金属结构,由于提高钛膜与氧化物膜等的粘附性以及降低对硅的还原作用而能够确保良好的接触特性。
7.对根据本发明第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺)的说明(主要参考图34至图39)。
在本部分中,将说明通孔最后工艺的示例,作为部分2等中说明的工艺的变型例。该工艺流程基本上类似于图4至图27中所示的流程,不同之处在于贯通通孔的部分,因为贯通通孔形成的时刻从完成金属前区的时间转移至完成最上级掩埋布线22的时间。因此,原则上,下文将说明取决于贯通通孔形成的时刻的变迁而改变的部分。
这里将说明通孔最后工艺,其中在基本上完成掩埋布线形成步骤之后开始的贯通通孔形成。为了简化附图,作为双镶嵌结构的第二或更高级的掩埋布线的结构将示出为类似于作为单镶嵌结构的第一级掩埋布线的简化结构。
图34是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(在完成最上级掩埋布线形成步骤时),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺)。图35是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(图案化贯通通孔以形成抗蚀膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺)。图36是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺)。图37是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔衬里绝缘膜和贯通通孔阻挡金属膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺)。图38是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋并平坦化贯通通孔电极的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺)。图39是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(最终钝化步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺)。基于上述附图,将说明根据本发明第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔最后工艺)。
如图34中所示,类似于图4至图18,形成下级和中间级掩埋布线42,随后完成除焊盘层等之外的最上级布线22(最上级掩埋布线)的掩埋。
随后,如图35中所示,类似于图5,在器件表面1a(表面)侧上的晶片1的几乎整个表面上形成贯通通孔形成抗蚀膜15,随后例如采用典型光刻进行图案化。
随后,如图36中所示,类似于图6,利用图案化的贯通通孔形成抗蚀膜15作为掩膜,通过各向异性干蚀刻(采用用于绝缘膜部的碳氟基气体以及用于衬底部的卤素基气体作为气体系统)形成贯通通孔16(例如具有约20μm的顶部直径以及约60μm的深度),贯通通孔16穿过布线层间绝缘膜20和金属前绝缘膜6并到达半导体衬底部1s的内部。随后例如通过灰化移除变成不必要的抗蚀膜。
随后,如图37中所示,类似于图7,在器件表面1a侧(表面侧)上的晶片1的几乎整个表面上,例如通过CVD,形成氧化硅基绝缘膜(例如具有约200nm厚度的臭氧TEOS膜),从而形成贯通通孔衬里绝缘膜11。随后,如图8和9中那样,通过各向异性干蚀刻从贯通通孔衬里绝缘膜11(孔)的底部16b移除贯通通孔衬里绝缘膜11。随后,如图10中那样,在器件表面1a侧的晶片1的几乎整个表面上(包括贯通通孔16的内表面),例如通过MOCVD(金属有机CVD)或溅射(例如电离溅射),形成氮化钛膜(例如具有约30nm的厚度)作为贯通通孔阻挡金属膜9b。
随后,如图38中所示,如在图11中那样,在贯通通孔阻挡金属膜9b上以及器件表面1a侧上的晶片1的整个表面(包括贯通通孔16的内表面)上,例如通过溅射(例如电离溅射)形成铜籽晶膜。随后,例如通过以铜籽晶膜作为籽晶层进行电镀,在整个表面(包括贯通通孔16的内表面)上形成铜膜(包括籽晶膜),由此填充贯通通孔16。随后,借助金属CMP,通过金属CMP移除贯通通孔16外部的铜膜和贯通通孔阻挡金属膜9b,从而形成由贯通通孔主金属电极9a(铜膜)、贯通通孔阻挡金属膜9b等构成的贯通通孔电极9。
随后,如图39中所示,如图18中那样,在最上级布线22上形成下焊盘层间绝缘膜20p且在其中掩埋上钨插塞23。随后,如图18中所示,电极焊盘24p(例如铝基焊盘)形成在下焊盘层间绝缘膜20p上且其上除了焊盘开口之外的部分由最终钝化膜25覆盖。因此,至少一个贯通通孔电极利用属于焊盘层的布线电耦合至焊盘。
这之后的步骤类似于参考图18至27所述的情况,因此此处省略其重复说明。
至此,在这部分中说明的示例中,在形成除焊盘层之外的最上级布线的步骤期间形成贯通通孔电极。因此其优点是形成电极与需要短时处理的中间或下级布线的形成步骤分开。简言之,其优点是通过采用具有相对粗精度的处理设备形成贯通通孔电极。
8.对根据本发明第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺)的说明(主要参考图40至图46)
在这部分中,将说明通孔优先-多晶硅工艺的示例作为改变贯通通孔的形成时刻的、部分2等中所述的工艺的示例。工艺流程基本上类似于图4至图27中所述的流程,不同之处在于贯通通孔的部分,因为仅贯通通孔形成的时刻从完成金属前区的时间推移至完成STI区和杂质掺杂区的部分(例如图2中的N阱区WN,p阱区WP等)的时间。因此原则上在下文将说明根据贯通通孔形成的时刻的推移而变化的部分。
图40是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺)。图41是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔衬里绝缘膜并蚀刻的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺)。图42是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋并平坦化贯通通孔电极的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺)。图43是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成栅绝缘膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺)。图44是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(蚀刻栅绝缘膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺)。图45是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成栅电极膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺)。图46是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(加工栅电极膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺)。基于上述附图,将说明根据本发明第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先-多晶硅工艺)。
如图40中所示,在完成STI区3等时,在器件表面1a侧上的晶片1的几乎整个表面上形成贯通通孔形成抗蚀膜15(例如具有约5μm的厚度),随后例如通过典型光刻进行图案化。随后,利用图案化的贯通通孔形成抗蚀膜15作为掩膜,执行各向异性干蚀刻以形成具有基本上圆形平面形状的贯通通孔16(具有约3μm的顶部直径以及约20μm的深度)。随后例如利用灰化移除变成不必要的抗蚀膜。贯通通孔16的内侧表面16i可朝向底部垂直或略微渐缩。
随后,如图41中所示,如图7中那样,在器件表面1a侧上的晶片1的几乎整个表面上,例如通过CVD,形成氧化硅基绝缘膜(例如具有约200nm厚度的臭氧TEOS膜),从而形成贯通通孔衬里绝缘膜11。随后,如图8中所示,在器件表面1a侧上的晶片1的几乎整个表面上形成贯通通孔底部绝缘膜移除抗蚀膜17(例如具有约1μm的厚度),随后例如通过典型光刻进行图案化。随后,如图9中所示,例如利用图案化的贯通通孔底部绝缘膜移除抗蚀膜17作为掩膜,执行各向异性干蚀刻以从贯通通孔底部16b移除绝缘膜。随后,例如通过灰化移除变成不必要的抗蚀膜。
随后,如图42中所示,热氧化晶片1的器件表面1a以形成薄氧化硅膜(牺牲膜)。例如,随后例如通过CVD在整个牺牲膜上形成硼掺杂多晶硅膜以便以此填充贯通通孔16。随后,例如通过干回蚀移除贯通通孔16外部的多晶硅膜且还例如通过湿蚀刻移除牺牲膜。因此,多晶硅贯通通孔电极9p被掩埋在贯通通孔16中。
随后,如图43中所示,在晶片1的几乎整个器件表面1a上形成栅绝缘膜4。
随后,如图44中所示,例如在器件表面1a侧上的几乎整个晶片1的表面上形成栅绝缘膜蚀刻抗蚀膜43,随后例如通过典型光刻进行图案化。随后,利用图案化的栅绝缘膜蚀刻抗蚀膜43作为掩膜,蚀刻栅绝缘膜4以在多晶硅贯通通孔电极9p上形成开口。随后例如用过灰化移除变成不必要的抗蚀膜。
如图45中所示,例如通过CVD在晶片1的几乎整个器件表面1a上形成要作为栅极的导电膜5(例如多晶硅膜)。
随后,如图46中所示,在晶片1的几乎整个器件表面1a上形成栅极加工抗蚀膜44,随后例如通过典型光刻进行图案化。随后,例如利用图案化的栅极加工抗蚀膜44作为掩膜执行各向异性干蚀刻,从而图案化栅极5等。随后,例如通过灰化移除变成不必要的抗蚀膜。
此后进行源和漏的引入、侧壁的形成、金属前绝缘膜6的形成、导电插塞7的掩埋等,由此获得类似于图4或图16的结构。
在这部分说明的示例中,例如在栅电极形成步骤期间执行贯通通孔电极的掩埋且在不同于栅电极膜形成的时刻执行(不同时工艺)。或者其可与栅电极膜的形成同时进行(同时工艺)。前者的优点是简化工艺,而后者的优点是简化工艺步骤。
9.对根据本发明第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)的说明(主要参考图47至图54)
这部分说明通孔优先接触工艺的示例作为改变贯通通孔形成时刻的、部分2等中所述的工艺的示例。工艺流程基本上类似于图4至图27中所述的流程,不同之处在于贯通通孔的部分,因为仅贯通通孔形成的开始时刻从完成金属前区的时间推移至完成栅极(例如在图案化栅极、源和漏的引入、侧壁的形成等之后且在金属前绝缘膜6的形成之前)的时间。因此原则上仅在下文说明根据贯通通孔形成的时刻的推移而变化的部分。
图47是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。图48是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔衬里绝缘膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。图49是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(移除贯通通孔底部绝缘膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。图50是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成贯通通孔阻挡金属膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。图51是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋并平坦化贯通通孔电极的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。图52是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成接触孔的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。图53是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(形成金属插塞阻挡金属膜的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。图54是示出从图2截取的MISFET和贯通通孔的外周处的晶片区域R1的截面示意图(掩埋并平坦化导电插塞的步骤),其用于说明根据本发明的第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。基于上述附图将说明根据本发明第一实施例的半导体集成电路器件的制造方法中的贯通通孔形成工艺的变型例(通孔优先接触工艺)。
例如,在完成栅极之后,如图47中所示,在器件表面1a一侧上的晶片1的几乎整个表面上形成贯通通孔形成抗蚀膜15(例如具有约5μm的厚度),随后例如通过典型光刻进行图案化。随后,例如利用图案化的贯通通孔形成抗蚀膜15作为掩膜进行各向异性干蚀刻以形成具有基本上圆形平面形状的贯通通孔16(例如具有约3μm的顶部直径以及约20μm的深度)。随后例如通过灰化移除变成不必要的抗蚀膜。贯通通孔16的内侧表面16i可朝向底部垂直或略微渐缩。
随后,如图48中所示,在器件表面1a侧上的晶片1的几乎整个表面上,例如通过CVD,形成氧化硅基绝缘膜(例如,具有例如约200nm厚度的臭氧TEOS膜),从而形成贯通通孔衬里绝缘膜11以及主金属前绝缘膜6a。随后,例如通过CVD,在器件表面1a侧上的晶片1的几乎整个表面上形成氧化硅基绝缘膜(例如具有约100nm厚度的等离子体TEOS膜)作为帽盖层金属前绝缘膜6b。
随后,如图49中所示,例如利用贯通通孔底部绝缘膜移除抗蚀膜17作为掩膜,移除贯通通孔16中的帽盖层金属前绝缘膜6b以及贯通通孔底部16b上的贯通通孔衬里绝缘膜11。例如随后通过灰化移除变成不必要的抗蚀膜。
随后,如图50中所示,例如通过MOCVD(金属有机CVD)或溅射(电离溅射),在器件表面1a侧上的晶片1的几乎整个表面(包括贯通通孔16的内表面)上形成氮化钛膜(例如具有约30nm的厚度)作为贯通通孔阻挡金属膜9b。
随后,如图51中所示,例如通过CVD(采用用于成核的B2H6/WF6以及用于形成表层的H2/WF6作为气体系统)在氮化钛膜9b上以及器件表面1a侧上的晶片1的几乎整个表面(包括贯通通孔16的内表面)上形成钨膜,以便填充贯通通孔16。随后,执行金属CMP以移除贯通通孔16外部的钨膜和氮化钛膜9b。
随后,如图52中所示,在器件表面1a侧上的晶片1的几乎整个表面上形成接触孔形成抗蚀膜45,随后例如通过典型光刻进行图案化。利用由此图案化的接触孔形成抗蚀膜45作为掩膜,例如通过各向异性干蚀刻(例如采用碳氟基气体作为气体系统)形成接触孔40。随后例如通过灰化移除变成不必要的抗蚀膜。
随后,如图53中所示,例如通过MOCVD或溅射(例如电离溅射),在器件表面1a侧上的晶片1的几乎整个表面(包括接触孔40的内表面)上形成作氮化钛膜为金属插塞阻挡金属膜7b。
随后,如图54中所示,例如通过CVD(采用用于成核的B2H6/WF6以及用于形成表层的H2/WF6作为气体系统),在器件表面1a侧上的晶片1的几乎整个表面(包括接触孔40的内表面)上沉积钨膜7a,以便填充接触孔40。随后,执行金属CMP以移除接触孔40外部的钨膜7a以及金属插塞阻挡金属膜7b。除已经完成贯通通孔电极9之外,可获得等同于图4中所示的情况。
因此后续步骤基本上与图5至图27中所示的步骤相同,因此此处省略重复说明。
在本部分的上述示例中,在接触形成步骤期间执行贯通通孔电极的掩埋且在与接触插塞的形成不同的时刻执行(不同时工艺)。或者,与接触插塞的形成同时进行(同时工艺)。不同时工艺的优点是简化工艺,而同时工艺的优点是简化工艺步骤。
10.对上述实施例(包括变型例)和总体条件的补充说明
(1)TSV的问题以及各示例的特点:
在TSV,即在诸如硅衬底的半导体衬底中制造的形成在贯通孔(through hole)中的贯通通孔电极中,在本文中主要说明的贯通通孔在先正通孔型工艺中,通常下端在晶片减薄之前是封闭的,这就难以对贯通通孔电极执行导电测试。此外,晶片的半导体衬底部通常与各个贯通通孔电极绝缘,因此可能存在由掩埋贯通通孔电极之后的工艺造成的不希望的充电时发生的诸如栅击穿的缺陷。
在上述实施例(包括变型例)中,利用工艺的组合,即,适于微制造的半导体衬底中的孔形成以及孔的内表面上的衬里绝缘膜的形成作为基础,与具有电开路的下端的贯通通孔电极结构组合使用,从而实现适于微制造的贯通通孔电极工艺,以下将具体进行说明。
(2)对贯通通孔电极形成的时刻的考虑:如主要在部分1至6中说明的通孔中间工艺的优点是形成低阻贯通通孔电极,因为可采用下级布线(例如第一级掩埋布线)的微制造且同时,铜等可用作贯通通孔电极的主要材料。
另一方面,主要在部分7中说明的通孔中间工艺不能采用在通孔中间工艺或通孔优先工艺中采用的微制造,但其优点是在基本完成晶片工艺之后采用低阻铜等作为贯通通孔电极的主要材料。
因为如主要在部分8中说明的通孔优先-多晶硅工艺中贯通通孔电极在源-漏引入的步骤之前形成,因此从热平衡的立场考虑,该工艺是有利的。多晶硅在工艺中是非常稳定的材料且其不会导致任何污染。另一方面,甚至与钨等相比,添加硼(或磷等)显著增大电阻。通孔优先-多晶硅工艺属于通孔优先工艺,因此其优点是采用FEOL步骤的微制造。
如主要在部分9中说明的通孔优先-接触工艺可采用诸如钨的相对低阻的材料作为贯通通孔电极的主材料,因此其能实现相对低的电阻。通孔优先-接触工艺属于通孔优先工艺,因此其优点是能采用FEOL步骤的微制造。
11.总结
已经基于实施例具体说明了本发明人提出的本发明。但是应当注意,本发明不限于上述实施例或由上述实施例限定。显然在不脱离本发明要点的情况下可对本发明进行改变。
例如,在上述实施例中,利用栅优先工艺作为示例具体说明本发明。但是本发明不限于此,显然本发明可应用于FUSI工艺、高k优先且栅最后工艺、高k且栅最后工艺、P侧栅最后混合工艺等等。
在上述实施例中,具体说明了采用铜基掩埋布线(包括银基掩埋布线等)的结构。但是本发明不限于采用掩埋布线作为主布线系统的结构,显然本发明可应用于采用铝基非掩埋布线作为主布线系统的结构。
此外,在上述实施例中,利用主要由铝基非掩埋布线的焊盘层(包括仅由焊盘构成的焊盘层)作为示例对本发明进行说明,但本发明不限于此。显然本发明还可应用于由铜基掩埋布线构成的焊盘层(包括银基掩埋布线且包括仅由焊盘构成的焊盘层)。
Claims (19)
1.一种半导体集成电路器件的制造方法,包括步骤:
(a)制备具有器件主表面和背表面的半导体晶片;
(b)从所述半导体晶片的所述器件主表面至所述半导体晶片的半导体表面区形成多个到达其内部的孔;
(c)在所述孔的内表面上形成绝缘膜;以及
(d)在步骤(c)之后,在利用所述绝缘膜覆盖所述孔的除所述孔的底部之外的所述内表面的同时,在所述孔中掩埋导电构件,并且由此形成多个贯通通孔电极。
2.根据权利要求1所述的半导体集成电路器件的制造方法,还包括步骤:
(e)在晶片工艺中,将至少一个所述贯通通孔电极电耦合至栅电极。
3.根据权利要求2所述的半导体集成电路器件的制造方法,
其中,利用通孔中间工艺形成所述贯通通孔电极。
4.根据权利要求3所述的半导体集成电路器件的制造方法,
其中,在形成第一级布线的步骤中但在不同于掩埋所述第一级布线的时刻掩埋所述贯通通孔电极。
5.根据权利要求3所述的半导体集成电路器件的制造方法,
其中,与第一级布线的掩埋同时地掩埋所述贯通通孔电极。
6.根据权利要求2所述的半导体集成电路器件的制造方法,
其中,利用通孔最后工艺形成所述贯通通孔电极。
7.根据权利要求6所述的半导体集成电路器件的制造方法,
其中,在形成除焊盘层之外的最上级布线的步骤期间形成所述贯通通孔电极。
8.根据权利要求7所述的半导体集成电路器件的制造方法,
其中,至少一个所述贯通通孔电极通过属于所述焊盘层的布线电耦合至焊盘。
9.根据权利要求2所述的半导体集成电路器件的制造方法,还包括步骤:
(f)在步骤(d)之后但在晶片工艺期间,对所述晶片的所述器件主表面照射电子束以测试所述贯通通孔电极的导电状态。
10.根据权利要求2所述的半导体集成电路器件的制造方法,
其中,利用通孔优先工艺形成所述贯通通孔电极。
11.根据权利要求10所述的半导体集成电路器件的制造方法,
其中,在栅电极形成步骤中但在不同于形成栅电极膜的时刻执行所述贯通通孔电极的掩埋。
12.根据权利要求10所述的半导体集成电路器件的制造方法,
其中,与栅电极膜的形成同时地执行所述贯通通孔电极的掩埋。
13.根据权利要求10所述的半导体集成电路器件的制造方法,
其中,在接触形成步骤中但在不同于形成接触插塞的时刻执行所述贯通通孔电极的掩埋。
14.根据权利要求10所述的半导体集成电路器件的制造方法,
其中,与接触插塞的形成同时地执行所述贯通通孔电极的掩埋。
15.根据权利要求2所述的半导体集成电路器件的制造方法,
其中,至少在步骤(d)之后,所述贯通通孔电极的每一个的下端附近的半导体区具有重掺杂区,所述重掺杂区的导电类型与其周围的半导体区的导电类型相同并且具有高杂质浓度。
16.根据权利要求2所述的半导体集成电路器件的制造方法,
其中,所述贯通通孔电极具有主要以钛膜作为外层且以氮化钛膜作为内层的阻挡金属结构。
17.根据权利要求2所述的半导体集成电路器件的制造方法,
其中,所述贯通通孔电极的每一个的下端及其附近的半导体区之间具有金属硅化物层。
18.根据权利要求2所述的半导体集成电路器件的制造方法,还包括步骤:
(g)在步骤(d)之后,从所述半导体晶片的所述背表面侧对所述半导体晶片进行膜减薄处理以暴露所述半导体晶片的所述背表面侧上的所述贯通通孔电极。
19.根据权利要求18所述的半导体集成电路器件的制造方法,还包括步骤:
(h)在步骤(g)之后,所述贯通通孔电极耦合至在另一半导体衬底上提供的凸块电极。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012069669A JP5925006B2 (ja) | 2012-03-26 | 2012-03-26 | 半導体集積回路装置の製造方法 |
JP2012-069669 | 2012-03-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103441095A true CN103441095A (zh) | 2013-12-11 |
CN103441095B CN103441095B (zh) | 2017-03-01 |
Family
ID=49212216
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310099950.XA Expired - Fee Related CN103441095B (zh) | 2012-03-26 | 2013-03-26 | 半导体集成电路器件的制造方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US9240330B2 (zh) |
JP (1) | JP5925006B2 (zh) |
CN (1) | CN103441095B (zh) |
TW (1) | TWI594388B (zh) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106816426A (zh) * | 2015-11-30 | 2017-06-09 | 台湾积体电路制造股份有限公司 | 集成芯片及其制造方法 |
CN108122889A (zh) * | 2017-12-15 | 2018-06-05 | 西安科锐盛创新科技有限公司 | 基于横向二极管的tsv转接板 |
CN112447881A (zh) * | 2019-08-29 | 2021-03-05 | 阿聚尔斯佩西太阳能有限责任公司 | 用于半导体晶片的贯通开口的保护方法 |
CN113056814A (zh) * | 2018-04-27 | 2021-06-29 | 菲拓梅里克斯公司 | 确定半导体器件特性的系统和方法 |
US11988611B2 (en) | 2014-11-12 | 2024-05-21 | Femtometrix, Inc. | Systems for parsing material properties from within SHG signals |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8487410B2 (en) | 2011-04-13 | 2013-07-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon vias for semicondcutor substrate and method of manufacture |
US9305865B2 (en) | 2013-10-31 | 2016-04-05 | Micron Technology, Inc. | Devices, systems and methods for manufacturing through-substrate vias and front-side structures |
CN104078416B (zh) * | 2013-03-28 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | 硅通孔布局结构、硅通孔互联结构的形成方法 |
KR101397667B1 (ko) * | 2013-04-25 | 2014-05-23 | 전자부품연구원 | 반도체 소자용 배선 및 그 배선의 형성 방법 |
US9093380B2 (en) * | 2013-06-05 | 2015-07-28 | Texas Instruments Incorporated | Dielectric liner added after contact etch before silicide formation |
US9105644B2 (en) * | 2013-07-23 | 2015-08-11 | Analog Devices, Inc. | Apparatus and method for forming alignment features for back side processing of a wafer |
KR20150053088A (ko) * | 2013-11-07 | 2015-05-15 | 에스케이하이닉스 주식회사 | 반도체 소자 및 제조 방법 |
EP2889901B1 (en) | 2013-12-27 | 2021-02-03 | ams AG | Semiconductor device with through-substrate via and corresponding method |
JP6547932B2 (ja) * | 2013-12-27 | 2019-07-24 | ローム株式会社 | チップ部品およびその製造方法、ならびに当該チップ部品を備えた回路アセンブリおよび電子機器 |
US9583417B2 (en) * | 2014-03-12 | 2017-02-28 | Invensas Corporation | Via structure for signal equalization |
US10163705B2 (en) | 2014-04-28 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Profile of through via protrusion in 3DIC interconnect |
US10115701B2 (en) | 2014-06-26 | 2018-10-30 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming conductive vias by backside via reveal with CMP |
US9768066B2 (en) | 2014-06-26 | 2017-09-19 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming conductive vias by direct via reveal with organic passivation |
JP6667215B2 (ja) | 2014-07-24 | 2020-03-18 | キヤノン株式会社 | X線遮蔽格子、構造体、トールボット干渉計、x線遮蔽格子の製造方法 |
US9508642B2 (en) * | 2014-08-20 | 2016-11-29 | Globalfoundries Inc. | Self-aligned back end of line cut |
WO2016154526A1 (en) * | 2015-03-26 | 2016-09-29 | Board Of Regents, The University Of Texas System | Capped through-silicon-vias for 3d integrated circuits |
US10748906B2 (en) | 2015-05-13 | 2020-08-18 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
KR102366804B1 (ko) | 2015-05-13 | 2022-02-25 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
JP6502751B2 (ja) * | 2015-05-29 | 2019-04-17 | 東芝メモリ株式会社 | 半導体装置および半導体装置の製造方法 |
US9620488B2 (en) | 2015-08-19 | 2017-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional integrated circuit structure and bonded structure |
US10163655B2 (en) | 2015-11-20 | 2018-12-25 | Micron Technology, Inc. | Through substrate via liner densification |
KR20180097179A (ko) * | 2016-01-21 | 2018-08-30 | 어플라이드 머티어리얼스, 인코포레이티드 | 실리콘 관통 비아들의 도금의 프로세스 및 케미스트리 |
US10866273B2 (en) * | 2016-03-09 | 2020-12-15 | Xallent, LLC | Functional prober chip |
US10014255B2 (en) * | 2016-03-14 | 2018-07-03 | International Business Machines Corporation | Contacts having a geometry to reduce resistance |
US9960076B2 (en) * | 2016-08-05 | 2018-05-01 | Infineon Technologies Ag | Devices with backside metal structures and methods of formation thereof |
KR20180041297A (ko) * | 2016-10-13 | 2018-04-24 | 삼성전자주식회사 | 인터포저의 제조방법 및 이를 포함하는 반도체 패키지의 제조방법 |
KR102524962B1 (ko) * | 2016-11-14 | 2023-04-21 | 삼성전자주식회사 | 기판 구조체 제조 방법 및 이를 이용하여 제조된 기판 구조체 |
KR102406583B1 (ko) | 2017-07-12 | 2022-06-09 | 삼성전자주식회사 | 반도체 장치 |
CN112164688B (zh) * | 2017-07-21 | 2023-06-13 | 联华电子股份有限公司 | 芯片堆叠结构及管芯堆叠结构的制造方法 |
KR102450580B1 (ko) | 2017-12-22 | 2022-10-07 | 삼성전자주식회사 | 금속 배선 하부의 절연층 구조를 갖는 반도체 장치 |
JP2019140178A (ja) | 2018-02-07 | 2019-08-22 | 東芝メモリ株式会社 | 半導体装置 |
CN111247636B (zh) * | 2018-03-22 | 2024-04-19 | 闪迪技术有限公司 | 包含具有贯穿衬底通孔结构的键合芯片组件的三维存储器件及其制造方法 |
US10354980B1 (en) | 2018-03-22 | 2019-07-16 | Sandisk Technologies Llc | Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same |
US10354987B1 (en) * | 2018-03-22 | 2019-07-16 | Sandisk Technologies Llc | Three-dimensional memory device containing bonded chip assembly with through-substrate via structures and method of making the same |
JP7242220B2 (ja) * | 2018-09-03 | 2023-03-20 | キヤノン株式会社 | 接合ウェハ及びその製造方法、並びにスルーホール形成方法 |
US10700041B2 (en) * | 2018-09-21 | 2020-06-30 | Facebook Technologies, Llc | Stacking of three-dimensional circuits including through-silicon-vias |
US10861808B2 (en) * | 2018-11-21 | 2020-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bonding structure of dies with dangling bonds |
US11600519B2 (en) * | 2019-09-16 | 2023-03-07 | International Business Machines Corporation | Skip-via proximity interconnect |
JP7391741B2 (ja) | 2020-03-23 | 2023-12-05 | 株式会社東芝 | 構造体 |
DE102020127527A1 (de) * | 2020-04-29 | 2021-11-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Verbindungsstruktur und -verfahren |
US11450563B2 (en) | 2020-04-29 | 2022-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect structure and method |
CN111883541A (zh) * | 2020-06-30 | 2020-11-03 | 复旦大学 | 一种用于三维封装的soi有源转接板及其制备方法 |
US20220384357A1 (en) * | 2021-05-26 | 2022-12-01 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for fabricating a semiconductor structure |
US11901266B2 (en) * | 2021-08-30 | 2024-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device structure and method for forming the same |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090152602A1 (en) * | 2007-12-17 | 2009-06-18 | Kazutaka Akiyama | Semiconductor device and method for manufacturing the same |
US20090166846A1 (en) * | 2007-12-28 | 2009-07-02 | Micron Technology, Inc. | Pass-through 3d interconnect for microelectronic dies and associated systems and methods |
CN101663742A (zh) * | 2006-12-29 | 2010-03-03 | 丘费尔资产股份有限公司 | 具有直通芯片连接的前端处理晶片 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005026405A (ja) * | 2003-07-01 | 2005-01-27 | Sharp Corp | 貫通電極構造およびその製造方法、半導体チップならびにマルチチップ半導体装置 |
JP4241856B2 (ja) * | 2006-06-29 | 2009-03-18 | 三洋電機株式会社 | 半導体装置および半導体装置の製造方法 |
JP5361156B2 (ja) * | 2007-08-06 | 2013-12-04 | ラピスセミコンダクタ株式会社 | 半導体装置及びその製造方法 |
US7968460B2 (en) * | 2008-06-19 | 2011-06-28 | Micron Technology, Inc. | Semiconductor with through-substrate interconnect |
JP2010027973A (ja) * | 2008-07-23 | 2010-02-04 | Fujitsu Microelectronics Ltd | ビア不良検出構造及びビア不良検出方法 |
JP4945545B2 (ja) * | 2008-11-10 | 2012-06-06 | 株式会社日立製作所 | 半導体装置の製造方法 |
JP2010186870A (ja) | 2009-02-12 | 2010-08-26 | Toshiba Corp | 半導体装置 |
JP5518091B2 (ja) * | 2009-11-12 | 2014-06-11 | パナソニック株式会社 | 半導体装置及び半導体装置の製造方法 |
KR20120031811A (ko) * | 2010-09-27 | 2012-04-04 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US8492241B2 (en) * | 2010-10-14 | 2013-07-23 | International Business Machines Corporation | Method for simultaneously forming a through silicon via and a deep trench structure |
-
2012
- 2012-03-26 JP JP2012069669A patent/JP5925006B2/ja not_active Expired - Fee Related
-
2013
- 2013-03-12 US US13/795,731 patent/US9240330B2/en not_active Expired - Fee Related
- 2013-03-13 TW TW102108854A patent/TWI594388B/zh not_active IP Right Cessation
- 2013-03-26 CN CN201310099950.XA patent/CN103441095B/zh not_active Expired - Fee Related
-
2015
- 2015-12-08 US US14/962,556 patent/US20160093555A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101663742A (zh) * | 2006-12-29 | 2010-03-03 | 丘费尔资产股份有限公司 | 具有直通芯片连接的前端处理晶片 |
US20090152602A1 (en) * | 2007-12-17 | 2009-06-18 | Kazutaka Akiyama | Semiconductor device and method for manufacturing the same |
US20090166846A1 (en) * | 2007-12-28 | 2009-07-02 | Micron Technology, Inc. | Pass-through 3d interconnect for microelectronic dies and associated systems and methods |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11988611B2 (en) | 2014-11-12 | 2024-05-21 | Femtometrix, Inc. | Systems for parsing material properties from within SHG signals |
CN106816426A (zh) * | 2015-11-30 | 2017-06-09 | 台湾积体电路制造股份有限公司 | 集成芯片及其制造方法 |
CN108122889A (zh) * | 2017-12-15 | 2018-06-05 | 西安科锐盛创新科技有限公司 | 基于横向二极管的tsv转接板 |
CN113056814A (zh) * | 2018-04-27 | 2021-06-29 | 菲拓梅里克斯公司 | 确定半导体器件特性的系统和方法 |
CN112447881A (zh) * | 2019-08-29 | 2021-03-05 | 阿聚尔斯佩西太阳能有限责任公司 | 用于半导体晶片的贯通开口的保护方法 |
CN112447881B (zh) * | 2019-08-29 | 2023-12-05 | 阿聚尔斯佩西太阳能有限责任公司 | 用于半导体晶片的贯通开口的保护方法 |
Also Published As
Publication number | Publication date |
---|---|
JP2013201353A (ja) | 2013-10-03 |
US9240330B2 (en) | 2016-01-19 |
TW201401474A (zh) | 2014-01-01 |
TWI594388B (zh) | 2017-08-01 |
JP5925006B2 (ja) | 2016-05-25 |
CN103441095B (zh) | 2017-03-01 |
US20130252416A1 (en) | 2013-09-26 |
US20160093555A1 (en) | 2016-03-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN103441095A (zh) | 半导体集成电路器件的制造方法 | |
US7919835B2 (en) | Semiconductor device and method for manufacturing the same | |
US8497551B2 (en) | Self-aligned contact for trench MOSFET | |
US20150061147A1 (en) | Device with Through-Substrate Via Structure and Method for Forming the Same | |
TW201616607A (zh) | 半導體裝置與其形成方法 | |
US11798848B2 (en) | Semiconductor device structure with resistive element | |
TWI777359B (zh) | 半導體元件與其製造方法 | |
TW201013842A (en) | Semiconductor device with local interconnects | |
JPH11317525A (ja) | 半導体素子およびその製造方法 | |
CN113284841A (zh) | 形成三维半导体结构的方法 | |
CN101673719A (zh) | 在sin和tin之间引入金属层以改善p-tsv的cbd接触电阻 | |
CN113206082A (zh) | 半导体装置 | |
KR20230145955A (ko) | 금속 상에 랜딩되는 배면 또는 전면 기판 관통 비아(tsv) | |
TWI782473B (zh) | 半導體元件及其製造方法 | |
US20240096805A1 (en) | Semiconductor devices with backside routing and method of forming same | |
US11942390B2 (en) | Thermal dissipation in semiconductor devices | |
CN116314024A (zh) | 集成电路装置及其制造方法 | |
US20220328363A1 (en) | Dual-Side Power Rail Design and Method of Making Same | |
US11862561B2 (en) | Semiconductor devices with backside routing and method of forming same | |
US10811315B2 (en) | Method for producing a through semiconductor via connection | |
US20090115065A1 (en) | Semiconductor device and manufacturing method thereof | |
US6759331B1 (en) | Method for reducing surface zener drift | |
US11973075B2 (en) | Dual substrate side ESD diode for high speed circuit | |
KR101386749B1 (ko) | 반도체 집적 회로 제조 방법 | |
US12033919B2 (en) | Backside or frontside through substrate via (TSV) landing on metal |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information |
Address after: Tokyo, Japan Applicant after: Renesas Electronics Corporation Address before: Kanagawa Applicant before: Renesas Electronics Corporation |
|
COR | Change of bibliographic data | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170301 Termination date: 20190326 |