CN103441095A - Method of manufacturing a semiconductor integrated circuit device - Google Patents

Method of manufacturing a semiconductor integrated circuit device Download PDF

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Publication number
CN103441095A
CN103441095A CN201310099950XA CN201310099950A CN103441095A CN 103441095 A CN103441095 A CN 103441095A CN 201310099950X A CN201310099950X A CN 201310099950XA CN 201310099950 A CN201310099950 A CN 201310099950A CN 103441095 A CN103441095 A CN 103441095A
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CN
China
Prior art keywords
hole
manufacture method
semiconductor device
wafer
perforation
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CN201310099950XA
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CN103441095B (en
Inventor
武田康裕
组桥孝生
柳田博史
竹内隆
松田安司
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN103441095A publication Critical patent/CN103441095A/en
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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Abstract

The invention relates to a method of manufacturing a semiconductor integrated circuit device. The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Description

The manufacture method of semiconductor device
Cross-reference to related applications
Disclosure by the Japanese patent application No.2012-069669 of application on March 26th, 2012, comprise specification, accompanying drawing and summary, and integral body is incorporated to this paper by reference.
Technical field
The present invention relates to the manufacture method of a kind of semiconductor device (or semiconductor device), relate to particularly and a kind ofly be applied to connect through hole (through via) technology, be TSV(Through Silicon Via, connect the silicon through hole) effective technology during technology.
Background technology
Japanese Patent Laid-Open No.2009-43779(patent documentation 1) or the U.S. Patent No. 7932602(patent documentation 2 corresponding with it) a kind of technology that forms tungsten base penetrating electrode disclosed, this tungsten base penetrating electrode is through burying before silicon oxide film and the metal on burying silicon oxide film dielectric film and arriving its lower surface in the surface region that has been buried in advance silicon substrate.In the document, disclosed TSV technology belongs to through hole (via) first process, and before metal, dielectric film forms the technique that connects through hole after forming.
Japanese Patent Laid-Open No.2010-186870(patent documentation 3) disclose a kind of technology that forms penetrating electrode, this penetrating electrode is from the back of the body face side of silicon substrate through silicon substrate and arrive the lower surface of metal pad.In the document, disclosed TSV technology belongs to so-called " back of the body through hole type through hole last (back via type via last) " technique.
[patent documentation]
[patent documentation 1] Japanese Patent Laid-Open No.2009-43779
[patent documentation 2] U.S. Patent No. 7932602
[patent documentation 3] Japanese Patent Laid-Open No.2010-186870
Summary of the invention
The TSV technology is commonly used for the technology of stacking a plurality of semiconductor chips etc.But the inventor has illustrated when (via middle) technique, last (the front via type via last) technique of positive through hole type through hole etc. form TSV in the middle of using so-called via-first technique, through hole, may exist because the electrostatic breakdown in subsequent technique causes occurring the possibility such as the defect of gate breakdown.
Below will illustrate for overcoming the means of the problems referred to above.From description and the accompanying drawing of this paper, will make other problems of the present invention and novel feature become apparent.
Below will sketch an exemplary embodiments in embodiment disclosed herein.
Below the general introduction of one embodiment of the present of invention: in the manufacture method of semiconductor device, form insulating component and imbed subsequently conductive member as connecting through hole electrode in hole by forming in Semiconductor substrate in, hole, hole, and the hole simultaneously covered except the bottom, hole with insulating component forms the perforation through hole electrode.
Below will sketch the beneficial effect that this exemplary embodiments from embodiment disclosed herein obtains.
Can reduce the possibility such as the defect generation of gate breakdown.
The accompanying drawing explanation
Fig. 1 be illustrate for explanation according to the vertical view of the regional area on the wafer of the summary (being mainly the through hole middle process) of the manufacture method of the semiconductor device of the first embodiment of the present invention (comprising modified example) (complete connect through hole electrode bury with planarization the time);
Fig. 2 is the sectional view corresponding to the wafer in the X-X ' cross section of Fig. 1;
Fig. 3 illustrates the process flow diagram of summary that forms the key step of technique according to the perforation through hole in the manufacture method of the semiconductor device of the first embodiment of the present invention (comprising modified example);
Fig. 4 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (completing while burying tungsten plug) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Fig. 5 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (patterning connects the step that through hole forms etchant resist) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Fig. 6 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (forming the step that connects through hole) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Fig. 7 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (form first order inter wiring layer insulating film and connect the step of through hole lining dielectric film) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Fig. 8 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (patterning connects the via bottoms dielectric film to form the step of etchant resist) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Fig. 9 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (removing the step that connects the via bottoms dielectric film) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Figure 10 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (forming the step that connects the through hole barrier metal film) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Figure 11 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (burying the step that connects through hole master metal electrode with planarization) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Figure 12 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (patterning first order wire laying slot is to form the step of etchant resist) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Figure 13 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (forming the step of first order wire laying slot) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Figure 14 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (forming the step of first order wiring barrier metal film) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Figure 15 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (burying the step that connects through hole electrode with planarization) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole;
Figure 16 be whole wafer is shown schematic cross-section (when completing the FEOL step, corresponding to the accompanying drawing of Fig. 4), it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 17 is the schematic cross-section (first order burial wiring forms step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 18 is the schematic cross-section (the probe test step of the wafer on pad) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 19 is the schematic cross-section (the probe test step of the wafer on projection) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 20 is the schematic cross-section (wafer cutting edge step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 21 is the schematic cross-section (glass support plate attach step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 22 is the schematic cross-section (grinding back surface step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 23 is the schematic cross-section (back etched step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 24 is the schematic cross-section (forming the step of dorsal part dielectric film and backside bond pad) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 25 is schematic cross-section that whole wafer is shown (is arranged on cutting belt and removes the step of glass support plate), and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 26 is schematic cross-section that whole wafer is shown (scribing and die bonding is to the step on another chip), and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 27 is schematic cross-section that whole wafer is shown (die bonding is to the step on wiring board), and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description;
Figure 28 is the circuit diagram in the chip area of wafer, and it is the wafer probe test according to the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes;
Figure 29 is the schematic cross-section of wafer that connects the periphery of through hole, and it is the PVC(positive voltage contrast according to the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes) test;
Figure 30 is the schematic cross-section of wafer that connects the periphery of through hole, and it is the NVC(negative voltage contrast according to the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes) test;
Figure 31 be illustrate from the MISFET of Fig. 2 intercepting and connect through hole periphery wafer area R1 and corresponding to the schematic cross-section (introducing the step that connects the via bottoms heavily doped region) of Fig. 9, it is the lifting according to the contact resistance of the via bottoms of the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes;
Figure 32 be illustrate from the MISFET of Fig. 2 intercepting and connect through hole periphery wafer area R1 and corresponding to the schematic cross-section (introducing the step that connects the via bottoms disilicide layer) of Fig. 9, it is the lifting according to the contact resistance of the via bottoms of the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes;
Figure 33 be illustrate from the MISFET of Fig. 2 intercepting and connect through hole periphery wafer area R1 and corresponding to the schematic cross-section of Figure 15 (bury and planarization connects the step of through hole electrode), it is the lifting according to the contact resistance of the via bottoms of the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes;
Figure 34 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (when completing higher level's burial wiring and form step) of wafer area R1 of the periphery of through hole, and it forms the modified example (through hole last process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 35 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (patterning connects through hole to form the step of etchant resist), and it is the modified example (through hole last process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 36 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects through hole), and it is the modified example (through hole last process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 37 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects through hole lining dielectric film and perforation through hole barrier metal film), and it forms the modified example (through hole last process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 38 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (burying the step that also planarization connects through hole electrode), and it is the modified example (through hole last process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 39 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (final passivation step), and it forms the modified example (through hole last process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 40 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects through hole), and it is the modified example (via-first-polysilicon process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 41 is the schematic cross-section (form and connect also etched step of through hole lining dielectric film) that the wafer area R1 of the MISFET intercepted from Fig. 2 and the periphery that connects through hole is shown, and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 42 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (burying the step that also planarization connects through hole electrode), and it is the modified example (via-first-polysilicon process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 43 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step of gate insulating film), and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 44 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section (gate insulating film etching step) of the wafer area R1 of the periphery that connects through hole, and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 45 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section (gate electrode film formation step) of the wafer area R1 of the periphery that connects through hole, and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 46 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (step of processing gate electrode film), and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 47 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (connect through hole and form step), and it is the modified example (via-first contact process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 48 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects through hole lining dielectric film), and it is the modified example (via-first contact process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 49 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (removing the step that connects the via bottoms dielectric film), and it forms the modified example (via-first contact process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 50 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects the through hole barrier metal film), and it is the modified example (via-first contact process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 51 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (burying the step that also planarization connects through hole electrode), and it is the modified example (via-first contact process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 52 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step of contact hole), and it forms the modified example (via-first contact process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 53 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step of metal plug barrier metal film), and it forms the modified example (via-first contact process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation;
Figure 54 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (burying the also step of planarize conductive connector), and it forms the modified example (via-first contact process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.
Embodiment
[embodiment summary] at first will illustrate exemplary embodiments disclosed herein.
1. the manufacture method of a semiconductor device, comprise the following steps: (a) prepare and have device first type surface and the surperficial semiconductor wafer of the back of the body; (b) semiconductor surface area from the device first type surface of semiconductor wafer to semiconductor wafer forms its inner hole of a plurality of arrival; (c) form dielectric film on the inner surface in hole; And (d) in step (c) afterwards, buried conductive member in hole, utilize dielectric film to cover the inner surface in the hole except the bottom, hole simultaneously, and form thus a plurality of perforation through hole electrodes.
2. the manufacture method of the semiconductor device described in above-mentioned 1, also comprise step: (e) in wafer process, at least one is connected to through hole electrode and be electrically coupled to gate electrode.
3. the manufacture method of the semiconductor device described in above-mentioned 1 or 2, wherein utilize the through hole middle process to form and connect through hole electrode.
4. as the manufacture method of semiconductor device described in above-mentioned 3, wherein in the step that forms first order wiring but bury the perforation through hole electrode being different from the moment of burying first order wiring.
5. the manufacture method of the semiconductor device described in above-mentioned 3 is wherein buried the perforation through hole electrode when burying first order wiring.
6. the manufacture method of the semiconductor device described in above-mentioned 1 or 2, wherein utilize the through hole last process to form and connect through hole electrode.
7. as the manufacture method of semiconductor device described in above-mentioned 6, wherein during the step that forms the higher level's wiring except pad layer, form the perforation through hole electrode.
8. as the manufacture method of semiconductor device described in above-mentioned 7, wherein at least one connects through hole electrode and is electrically coupled to pad by the wiring that belongs to pad layer.
9. the manufacture method of the described semiconductor device of any one as in above-mentioned 1 to 8, also comprise step: (f) in step (d) afterwards but during wafer process, the device first type surface irradiating electron beam of wafer is connected to the conduction state of through hole electrode with test.
10. the manufacture method of the semiconductor device described in above-mentioned 1,2 or 9, wherein utilize via-first technique to form and connect through hole electrode.
11. as the manufacture method of semiconductor device described in above-mentioned 10, wherein at gate electrode, form in step but carry out burying of perforation through hole electrode being different from the moment that forms gate electrode film.
12. the manufacture method of the semiconductor device described in above-mentioned 10, wherein connect burying of through hole electrode film formed execution of gate electrode simultaneously.
13. as the manufacture method of semiconductor device described in above-mentioned 10, wherein in contact, form in step when carrying out burying of perforation through hole electrode being different from the moment that forms contact plunger.
14. the manufacture method of the semiconductor device described in above-mentioned 10 is wherein carried out and is connected burying of through hole electrode when contact plunger forms.
15. as the manufacture method of the described semiconductor device of any one in above-mentioned 1 to 14, wherein at least in step (d) afterwards, near each semiconductor region connected the lower end of through hole electrode has heavily doped region, and the conduction type of its conduction type and its semiconductor region on every side is identical and have a high impurity concentration.
16. as the manufacture method of the described semiconductor device of any one in above-mentioned 1 to 15, wherein connect through hole electrode and there is the barrier metal structure, its outer for titanium film and internal layer be titanium nitride film.
17. as the manufacture method of the described semiconductor device of any one in above-mentioned 1 to 16, wherein each connects between the lower end of through hole electrode and near semiconductor region thereof and has metal silicide layer.
18. as the manufacture method of the described semiconductor device of any one in above-mentioned 1 to 17, also comprise step: (g) in step (d) afterwards, from the back of the body face side of semiconductor wafer, semiconductor wafer is carried out to the film reduction processing with the perforation through hole electrode the back of the body face side that exposes semiconductor wafer.
19. the manufacture method of the semiconductor device described in above-mentioned 18 also comprises step: (h) in step (g) afterwards, connect through hole electrode the salient pole provided on second half conductive substrate is provided.
[to the explanation of explanation mode, basic terms and the purposes of this paper]
1. in this application, for simplicity, if need after being divided into a plurality of parts, embodiment described.These parts are not independent of one another, and unless specified otherwise herein, otherwise they each can be the part of single example, or in them one can be another part details or another whole or a part of modified example.In principle, similar part is not carried out to repeat specification.In an embodiment, when relating to composed component, unless specified otherwise herein, be limited to theoretic numeral or be not from the apparent situation of context in principle, otherwise be not absolutely necessary.
In addition, in the present invention, term " semiconductor device " or " semiconductor device " mainly refer to various transistors (active element) unit that is integrated on semiconductor chip (such as monocrystalline substrate) etc., have the semiconductor chip of transistor unit as the device of critical piece, resistor, capacitor etc. and encapsulation.Various transistorized typical cases can comprise take the MOSFET(mos field effect transistor) be the MISFET(conductor insulator semiconductor fet of representative).In this case, the typical case of integrated circuit structure can comprise having the CMOS(complementary metal oxide semiconductors (CMOS) of N channel-type MISFET and P channel-type MISFET combination) the type integrated circuit CMIS(complementary metal insulator semiconductor that is representative) the type integrated circuit.
The wafer process of modern semiconductors integrated circuit (IC)-components, i.e. LSI(large-scale integrated) can usually be divided into two steps.The first step is from loading the FEOL(line front end to step metal as the silicon wafer of raw material) step (step that comprises the lower limb of M1 wiring layer and the formation of the interlayer dielectric between grid structure, the formation of contact hole, the mask of tungsten plug etc.).Second step is the BEOL(line rear end for the formation of the bonding pad opening of final passivating film that is formed on aluminium base pad electrode from the M1 wiring layer) step (in wafer-class encapsulation technique, also can comprise this technique).
2. similarly, in the explanation of embodiment etc., when about uses such as material, component " X is made by A " etc., unless concrete regulation or in principle can not be apparent from context, main Constitution Elements is not got rid of the composition except A.For example, for composition, above-mentioned sentence refers to " X comprises A as main component ".For example, apparent, term " silicon component " etc. not only refers to the member of being made by pure silicon, also refers to comprise the SiGe alloy, has the member of silicon as another multielement alloy of main component or additive.
Similarly, term " silicon oxide film ", " silicon oxide insulating film " etc. not only refer to the dielectric film of being made by relatively pure non-doped silicon oxide (non-doping silicon dioxide), also refer to have silica other dielectric films as main component.The example of silicon oxide film comprises impurity doped silicon oxide based insulation film, such as TEOS base silica, PSG(phosphosilicate glass) and the BPSG(boron-phosphorosilicate glass) film.In addition, heat oxide film, CVD oxide-film, by application such as the SOG(spin-coating glass) and NCS(nano-clustering silica, nano-cluster silicon dioxide) film of method acquisition of film also is encompassed in the scope of silicon oxide film or silica-based dielectric film.In addition, such as the FSG(fluorosilicate glass), the SiOC(silicon oxide carbide), carbon doped silicon oxide and OSG(organic silicate glass) the low k dielectric film of film also is encompassed in the scope of silicon oxide film or silica-based dielectric film.And, by the low k dielectric film (porous insulating film) of silicon-dioxide-substrate that introduction hole obtains in being similar to the member of above-mentioned material, also be encompassed in the scope of silicon oxide film or silica-based dielectric film.
In addition, the silica-based dielectric film be usually used in as silica-based dielectric film in semiconductor applications is nitride silicon based dielectric film.The material that belongs to this class comprises SiN, SiCN, SiNH and SiCNH.Unless specified otherwise herein, otherwise term used herein " silicon nitride " comprises SiN and SiNH.Similarly, unless specified otherwise herein, term used herein " SiCN " comprises SiCN and SiCNH.
Incidentally, the character of SiC is similar to SiN, but SiON often is classified as silica-based dielectric film.
Silicon nitride film is in the SAC(self-aligned contacts) in technology not only mainly as etch stop film, as the CESL(contact etch stop layer), but also at the SMT(stress memory technique) in be used as stress and apply film.
Similarly, term " nickle silicide " typically refers to the Ni-monocrystal silicide, but it not only comprises relatively pure Ni-monocrystal silicide, also comprises and respectively comprises the Ni-monocrystal silicide as the alloy of main component, mixed crystal etc.And silicide is not limited to nickle silicide, and can also be the conventional cobalt silicide used, titanium silicide, tungsten silicide etc.Metal film for silication, not only can adopt Ni(nickel) film, and can adopt the nickel alloy film such as Ni-Pt alloy film (alloy film of Ni and Pt), Ni-V alloy film (alloy film of Ni and V), Ni-Pd alloy film (alloy film of Ni and Pd), Ni-Yb alloy film (alloy film of Ni and Yb) or Ni-Er alloy film (alloy film of Ni and Er).Notice that comprising nickel is referred to as " Ni-based silicide " as the above-mentioned silicide of its major metal element.
3. similarly, the preferred exemplary of shape, position, attribute etc. is shown, unless but concrete regulation or in principle can not be apparent from context, otherwise shape, position, attribute etc. are not strictly limited to preferred exemplary.
4. in addition, when relating to concrete numeral or when amount, unless concrete regulation, theoretical upper limit in concrete numeral or amount or can not be apparent from context, otherwise numeral or amount can be greater than or less than concrete numeral or amount.
5. term " wafer " refers on it silicon single crystal wafer that will form semiconductor device (and semiconductor device or electronic device), but obviously also comprises epitaxial wafer and semiconductor layer and such as the composite crystal of the dielectric film substrate of SOI substrate or LCD glass substrate.
6. for the classification of the formation technique of TSV, the main technique that forms TSV during the FEOL step is called as " via-first technique ", and the main technique forming TSV during the BEOL step is called as " through hole middle process " and the main technique that forms TSV after the BEOL step and before stacking is called as " stacking rear technique ".In the present invention, as follows TSV is formed to technique and classified, it corresponds essentially to above-mentioned a kind of.At first, according to the formation moment of TSV, technique is divided into roughly " via-first technique ", " through hole middle process ", " through hole last process " and " stacking rear technique ".
In via-first technique, such as perforation through hole formation before first order inter wiring layer insulating film forms of TSV; In the through hole middle process, after completing the metal proparea and before the higher level's wiring layer except pad layer completes, form and connect through hole; In the through hole last process, after above-mentioned technique and before stacking, form the perforation through hole; And, in stacking rear technique, in stacking rear formation, connect through hole.
In addition, the perforation through hole formed from the face side of wafer is called as " positive through hole ", and is called as " back of the body through hole " from the perforation through hole that the dorsal part of wafer forms.
When the perforation through hole formed before distinguishing wafer grinding especially and the perforation through hole formed after wafer grinding, the former is called as " connecting through hole formerly " or " connecting through hole at antetype ".In following examples, main explanation belongs to the through hole of " connecting formerly positive through hole type of through hole ".
In addition, adopt polysilicon etc. to be called as " via-first polysilicon process " as the via-first technique of the main noggin piece that connects through hole, and the employing tungsten that is similar to contact hole is called as " via-first contact process " as the via-first technique of noggin piece.
7. term used herein " TSV ", " perforation through hole ", " perforation through hole electrode " etc., refer to the member that is penetrated or should be penetrated, unless should distinguish between the two, because can cause unnecessary obscuring with another title appellation member during step.Obviously the substrate for " TSV ", " silicon perforation through hole " etc. is not limited to silicon-based wafer etc.
[detailed description of embodiment] is following will more specifically illustrate embodiment.In institute's drawings attached, same or analogous member will mean by same or analogous mark or accompanying drawing number, and in principle will the repetitive description thereof will be omitted.
And, in institute's drawings attached, when hachure etc. can make accompanying drawing complicated or clearly the time, sometimes even in sectional view, also dispense hachure with the difference of blank parts.In this, even learning apparently that from specification etc. hole obviously during sealing, sometimes can omit the profile of background in vertical view.In addition, even in the situation that be not that sectional view also can be applied hachure, so that clear, illustrate and be not blank parts.
When alternately relation and one are called as " first " etc. and another one and are called as " second " etc., can determine corresponding relation when both based on exemplary embodiments.But obviously, when a certain member for example is called as " first " member, it is not limited to this selection.
1. according to the explanation (being mainly the through hole middle process) of the summary of the manufacture method of the semiconductor device of first embodiment of the invention (comprising modified example) (being mainly Fig. 1 to 3)
Below concrete with reference to silica-based CMIS type semiconductor device (being the mos semiconductor integrated circuit (IC)-components), as example, describe.But obviously bipolar semiconductor integrated circuit (IC)-components or another device also can be used as example.
This part mainly illustrates the through hole middle process, and it is used in part 2 to 6, but obviously this part can be applied to through hole last process or via-first technique.
The degree of depth (for example approximately 50 μ m and usually in the scope in about 10 to 100 μ m) that connects through hole is firmly got many than the degree of depth of the impurity doped region such as trap (being generally submicron order) usually, therefore in the accompanying drawings, unless necessary, otherwise omit in principle impurity doped region.In addition, the structure of grid periphery such as sidewall, is also omitted from figure.
Fig. 1 be illustrate regional area on wafer (complete connect through hole electrode bury with planarization the time) vertical view, the summary (being mainly the through hole middle process) for explanation according to the manufacture method of the semiconductor device of the first embodiment of the present invention (comprising modified example).Fig. 2 is the sectional view corresponding to the wafer of the X-X ' sectional view of Fig. 1.Fig. 3 illustrates the process flow diagram of summary that forms the major part of technique according to the perforation through hole in the manufacture method of the semiconductor device of the first embodiment of the present invention (comprising modified example).Will be based on the explanation of above-mentioned accompanying drawing the summary (being mainly the through hole middle process) according to the manufacture method of the semiconductor device of first embodiment of the invention.
Fig. 1 is illustrated in the manufacture method according to the semiconductor device of the first embodiment and completes the vertical view that master wafer is processed the part of the chip region 2 of the wafer 1 while processing (having the zone that connects through hole and peripheral circuit thereof).On the right side of Fig. 1, present a plurality of upper ends of circular perforation through hole electrode 9 basically.On the other hand, left side presents a plurality of first order burial wirings 8.Another part is first order inter wiring layer insulating film 12, and it is for example made by silica-based dielectric film.
Connect through hole electrode 9(its also do not become connect through hole) the perforation through hole barrier metal film 9b that makes of the perforation through hole master metal electrode 9a that made by for example copper member and for example titanium nitride forms.Similarly, the first order wiring barrier metal film 8b that the first order copper wiring film 8a that first order burial wiring 8 is made by for example copper member and for example titanium nitride are made forms.
X-X ' the cross section of Fig. 1 shown in Fig. 2.As shown in Figure 2, semiconductor wafer 1(is such as having the approximately thickness of 700 μ m) in the 1s(P of Semiconductor substrate section type monocrystalline substrate) surperficial 1a(device surface or the first first type surface) upper (carrying on the back on the opposition side of surperficial 1b) have the N raceway groove MISFET(Qn be isolated from each other by STI district 3 etc.) and P raceway groove MISFET(Qp).N raceway groove MISFET(Qn) and P raceway groove MISFET(Qp) for example gate polysilicon film of the grid 5(that provides via gate insulating film 4 all is provided).The P well region WP be provided in the semiconductor region on the surperficial 1a side of the 1s of Semiconductor substrate section has N raceway groove MISFET(Qn in its surface) N-type source-drain area DN.On the other hand, the N well region WN be provided in the semiconductor region on the surperficial 1a side of the 1s of Semiconductor substrate section has P raceway groove MISFET(Qp in its surface) P type source-drain area DP.
Before the 1s of Semiconductor substrate section has metal in its surperficial 1a, dielectric film 6(for example has the thickness of about 300nm) and its for example by dielectric film 6a before the main metal as lower floor with as dielectric film 6b before the cap layer metal on upper strata, form.Before main metal, dielectric film 6a for example for example, for example, consists of with the relative thick silica-based dielectric film (ozone TEOS base silicon oxide film) as upper strata the nitride silicon based dielectric film (silicon nitride film) of the relative thin as lower floor.Before the cap layer metal, dielectric film 6b for example for example, consists of silica-based dielectric film (plasma TEOS base silicon oxide film).
Before metal, dielectric film 6 has the conductive plunger 7 of burying wherein, and this conductive plunger passes this dielectric film and arrives grid 5, N-type source-drain area DN, P type source-drain area DP etc.Conductive plunger 7 by main metal plug 7a(such as tungsten plug), metal plug barrier metal film 7b(is such as titanium nitride film) etc. formation.There is first order inter wiring layer insulating film 12(such as the ozone TEOS base silicon oxide film with about 200nm thickness on dielectric film 6 before metal) and this first order inter wiring layer insulating film in there is the first order burial wiring 8 that is coupled to conductive plunger 7 etc.
As shown in fig. 1, in this example, before metal, in dielectric film 6, have a plurality of perforation through holes 16, they are through dielectric film 6 before metal and arrive the 1s of Semiconductor substrate section inside.These perforation through holes have buries perforation through hole electrode 9 wherein via connecting through hole lining dielectric film 11.Incidentally, in this example, connecting through hole lining dielectric film 11 is layers identical with first order inter wiring layer insulating film 12, and they form simultaneously, but this is not necessary condition.Connect through hole 16 and for example by the perforation through hole master metal electrode 9a(as internal layer, for example there is the hardware of copper as main component) and as the perforation through hole barrier metal film 9b(of side and bottom titanium nitride film for example) form.Usually, at least one connects through hole electrode 9 and is electrically coupled at least one grid 5 via grid-perforation through hole electrode wiring 14.Grid-perforation through hole wiring 14 wirings by grid 5, every one deck, or they constitute.
In this example, now, connect through hole 16 and also do not there is the through hole of perforation lining dielectric film 11 at its via bottoms 16b place, so connect through hole electrode 9 and the 1s(P of Semiconductor substrate section type monocrystalline substrate) basically be electrically coupled to one another (ohmic contact or schottky junction) to prevent large electrical potential difference.Therefore during manufacturing step, connect through hole 16 as being grounded to the 1s of Semiconductor substrate section, make can prevent the grid that caused by the undesirable charging that connects through hole 16 and puncture etc.
Below the summary (with reference to figure 2) for the manufacture method that realizes this structure shown in Figure 3.As shown in Figure 3, be below the summary of manufacture method.(1) form a plurality of holes that extend to its inside from the surperficial 1a side of wafer 1 in semiconductor surface area.(2) subsequently, on the inner surface in hole, form dielectric film.(3) in step (2) afterwards, buried conductive member in hole utilizes dielectric film to cover the inner surface (in other words, not covering at least a portion of bottom) in the hole except bottom to form a plurality of perforation through hole electrodes simultaneously.
By adopting said method, from beginning, connecting buried conductive member through hole until, remove the bottom that connects through hole by grinding back surface (attenuate of wafer) during, all perforation through hole electrodes 9 and the 1s of Semiconductor substrate section are electrically coupled to one another basically.
To in the manufacture method of the semiconductor device according to the first embodiment until complete the local specification (mainly with reference to figure 4 to Figure 15) of the technique (through hole middle process) of filling through hole.
The technique gone out shown here is an example, and obviously can change each element technique.Unless unless the necessity of being defined as or obviously necessary, otherwise each element technique is not absolutely necessary.This also is applicable to each element described in third part.Obviously, other elements shown in part 3 to 6 be not must but arbitrarily.
Fig. 4 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (completing while burying tungsten plug) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Fig. 5 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (patterning connects through hole to form the step of etchant resist) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Fig. 6 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (forming the step that connects through hole) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Fig. 7 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (form first order inter wiring layer insulating film and connect the step of through hole lining dielectric film) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Fig. 8 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (patterning is for removing the step of the etchant resist that connects the via bottoms dielectric film) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Fig. 9 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (removing the step that connects the via bottoms dielectric film) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Figure 10 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (forming the step that connects the through hole barrier metal film) of wafer area R1 of the periphery of through hole, its for the part explanation according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Figure 11 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (burying the step that connects through hole master metal electrode with planarization) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Figure 12 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (patterning first order wire laying slot is to form the step of etchant resist) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Figure 13 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (forming the step of first order wire laying slot) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Figure 14 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (forming the step of first order wiring barrier metal film) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Figure 15 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (burying the step that connects through hole electrode with planarization) of wafer area R1 of the periphery of through hole, its for local specification according to the manufacture method of the semiconductor device of the first embodiment of the present invention until the technique (through hole middle process) while having completed filling through hole.Based on above-mentioned accompanying drawing, in the manufacture method of the semiconductor device according to first embodiment of the invention, until completed the technique (through hole middle process) of filling through hole, carrying out local specification.
Shown in Fig. 4 for example according to typical CMIS technique complete step before metal the time the device cross section structure.In Fig. 4 or accompanying drawing thereafter, different from Fig. 2, omit in principle the impurity doped region in Semiconductor substrate, in order to prevent that accompanying drawing from becoming complicated.
Subsequently, as shown in Figure 5, on device surface 1a side, form on nearly all surface of wafer 1 and connect the thickness that through hole formation etchant resist 15(for example has 5 μ m), for example by typical photoetching, carry out patterning afterwards.
Subsequently, as shown in Figure 6, utilize the perforation through hole of patterning to form etchant resist 15 as mask, carry out anisotropic dry etch and there is the top diameter of about 10 μ m and the about degree of depth of 50 μ m to form the perforation through hole 16(that basically there is circular planar form).In other words, form a plurality of holes (connecting through hole 16) of the inside of the semiconductor surface area that arrives semiconductor wafer.For example by ashing, remove and become unnecessary etchant resist subsequently.The medial surface 16i that connects through hole 16 can be vertical or to bottom convergent slightly.
Subsequently, as shown in Figure 7, on nearly all surface of the wafer 1 on device surface 1a side, for example by CVD, (for example form silica-based dielectric film, there is for example ozone TEOS film of about 200nm thickness), connect through hole lining dielectric film 11 and first order inter wiring layer insulating film 12 to form.
Subsequently, as shown in Figure 8, formation perforation via bottoms dielectric film removes etchant resist 17(and for example has the approximately thickness of 1 μ m), for example by typical photoetching, carry out patterning subsequently.
Subsequently, as shown in Figure 9, utilize the etchant resist 17 of patterning as mask, carry out anisotropic dry etch, from connecting via bottoms 16b, remove dielectric film.For example by ashing, remove and become unnecessary etchant resist subsequently.
Subsequently, as shown in Figure 10, for example, by adopting the MOCVD(metallorganic CVD) or nearly all surface of the wafer 1 of sputter (for example, ionization sputter) on device surface side 1a on form titanium nitride film (thickness that for example there is about 30nm) as connecting through hole barrier metal film 9b.Example before comprises TDMAT(tetra-(dimethylamino) titanium) and TDEAT(tetra-(diethyl amino) titanium), it also is applied in following MOCVD similarly.The advantage of the film formed by the employing sputter is can not sneak into carbon, even and the advantage of MOCVD is in the situation that deep hole also can form more uniform film.
Subsequently, as shown in Figure 11, for example, for example, by adopting sputter (, ionization sputter) on device surface 1a side and the upper formation in whole surface (comprising the inner surface that connects through hole 16) the copper seed crystal film that connects the wafer 1 on through hole barrier metal film 9b.Subsequently, utilize the copper seed crystal film to be electroplated the upper copper film (comprising the seed crystal film) that forms in whole surface (comprising the inner surface that connects through hole 16) with the wafer 1 on device surface 1a side as inculating crystal layer, fill thus and connect through hole 16.Carry out subsequently metal CMP to remove the copper film that connects through hole 16 outsides and to connect through hole barrier metal film 9b, thereby form by connecting through hole master metal electrode 9a(copper film) and connect the perforation through hole electrode 9 that through hole barrier metal film 9b forms.This means by forming dielectric film and utilize the conductive member filler opening on the inner surface in a plurality of holes, and cover the inner surface in the hole except the bottom, hole simultaneously, and formed a plurality of perforation through hole electrodes.Notice in arbitrary steps, at least one connects through hole electrode and is electrically coupled to gate electrode.
Subsequently, as shown in Figure 12, form first order wire laying slot on the whole surface of the wafer 1 on device surface 1a mono-side and form the thickness that etchant resist 18(for example has 1 μ m), for example by typical photoetching, carry out patterning subsequently.
Subsequently, as shown in Figure 13, utilize the etchant resist 18 of patterning to carry out anisotropic dry etch to form first order wire laying slot 47 as mask.For example by ashing, remove and become unnecessary etchant resist subsequently.
Subsequently, as shown in Figure 14, for example by the almost whole surface (inner surface that comprises first order wire laying slot 47) that sputters at the wafer 1 on device surface 1a side, above form titanium nitride film (thickness that for example there is about 10nm) as first order wiring barrier metal film 8b.
Subsequently, as shown in Figure 15, for example by employing, sputter at (inner surface that comprises first order wire laying slot 47) on the whole surface of the wafer 1 on device surface 1a side and form the copper seed crystal film.Electroplated subsequently to form film and filled first order wire laying slot 47.For example, carry out the CMP(chemico-mechanical polishing) with the wafer 1 of planarization device surface 1a side, and remove the first order wiring barrier metal film 8b of first order wire laying slot 47 outsides and the copper film that has comprised the copper seed crystal film.Therefore, complete the first order burial wiring 8 formed by first order copper wiring film 8a and first order wiring barrier metal film 8b.
In next part, the technique described in this part and subsequent technique thereof will be described more comprehensively.
Above understand specifically following technique when different (technique), wherein, mainly in first order wiring forms step, what do not carry out in the same time first order wiring, burying and connecting burying of through hole electrode.Obviously can adopt following technique (technique of simultaneously carrying out), that wherein carries out the wiring of the first order as shown in Figure 12 to 15 buries and connects burying of through hole electrode simultaneously.When different, the advantage of technique is easily to realize technique, and the advantage of technique is to simplify processing step simultaneously.
3. to the overall description (mainly referring to figures 16 to Figure 27) of the technique after completing the FEOL step in the manufacture method of the semiconductor device according to first embodiment of the invention.
Will be by the B2F(back side to front) the D2D(tube core-tube core of bonding) bonding is as example, illustrate bonding or the stacking method of Semiconductor substrate, but obviously also alternative employing F2F(is face-to-face) bonding.For stacking method, obviously can adopt the W2W(wafer-to wafer) stacking or D2W(tube core-wafer) stacking.This W2W method comprises the reconfigured wafer that the good tube core known by permutatation on the substrate at wafer or similar wafer obtains.Similarly, B2F bonding F2F bonding can be applied to that W2W is stacking or D2W is stacking.
In the following description, the solder bonds of usining illustrates the bonding of substrate as an example, but obviously can adopt by the intermetallic bonding of tin-copper or by the bonding such as copper, silver or golden another metal.
Figure 16 be whole wafer is shown schematic cross-section (when completing the FEOL step, corresponding to the view of Fig. 4), it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 17 is the schematic cross-section (first order burial wiring forms step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 18 is the schematic cross-section (the probe test step of the wafer on pad) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 19 is the schematic cross-section (the probe test step of the wafer on projection) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 20 is the schematic cross-section (wafer cutting edge step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 21 is the schematic cross-section (glass support plate attach step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 22 is the schematic cross-section (grinding back surface step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 23 is the schematic cross-section (back etched step) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 24 is the schematic cross-section (forming the step of dorsal part dielectric film and backside bond pad) that whole wafer is shown, and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 25 is schematic cross-section that whole wafer is shown (is arranged on cutting belt and removes the step of glass support plate), and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 26 is schematic cross-section that whole wafer is shown (scribing and die bonding is to the step on another chip), and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Figure 27 is schematic cross-section that whole wafer is shown (die bonding is to the step on wiring board), and it is the technique of manufacture method after completing the FEOL step according to the semiconductor device of the first embodiment of the present invention for overall description.Below, based on above-mentioned accompanying drawing, the technique after completing the FEOL step in the manufacture method of the semiconductor device according to first embodiment of the invention is carried out to overall description.
From visual angle more fully, Fig. 4 is depicted as to Figure 16.Figure 16 to Figure 27 (and Figure 28) has omitted the structure (for example impurity doped region and STI district) in the Semiconductor substrate with connecting through hole and connect through hole electrode the structure that direct relation is arranged, in order to avoid complicated accompanying drawing.
Subsequently, as shown in Figure 17, form described in part 2 and connect through hole electrode 9.Subsequently, as required, for example on conductive plunger 7, in formation first order burial wiring 8, connecting formation first order burial wiring 8 on through hole electrode 9.
Subsequently, as shown in Figure 18, form as required the copper base burial wiring that multilayer intergrade burial wiring 19(for example makes by dual-damascene technics on first order inter wiring layer insulating film 12), multilayer intergrade burial wiring 19 is buried in the intergrade and higher level's interlayer dielectric 21 of mainly for example, being made by silica-based dielectric film (low k porous SiOC base silicon oxide film).Subsequently, the pad layer in being buried in intergrade and higher level's interlayer dielectric 21, form the higher level higher level's burial wiring of 22(that connects up on intergrade burial wiring 19, for example, the copper base burial wiring formed by dual-damascene technics).Here, first order inter wiring layer insulating film 12, intergrade and higher level's interlayer dielectric 21 etc. form inter wiring layer insulating film 20.Subsequently, in the inter wiring layer insulating film 20 connected up on 22 higher level, for example bury tungsten plug 23 as upper strata.Subsequently, form for example aluminum pad of electrode pad 24p(on inter wiring layer insulating film 20), and the part except bonding pad opening is covered by final passivating film 25 thereon.The preferred exemplary of final passivating film 25 comprises silica-based dielectric film and nitride silicon based dielectric film and composite membrane (being referred to as " inorganic final passivating film ") thereof.Organic final passivating film (for example polyimides base resin film) can be formed on inorganic final passivating film.Subsequently, for example make probe 51 and electrode pad 24p contact to carry out the wafer probe test.Obviously this test is optional.
Subsequently, as shown in Figure 19, such as the metal coupling electrode 26 of copper bump electrode for example by electroplate and via UBM(lower protruding block metal) layer is formed on electrode pad 24p.Subsequently, on copper bump electrode 26, such as waiting by plating, form for example nickel film of solder stop metal film 27().Subsequently, on solder stop metal film 27, by plating, wait and form the Xi Yinji scolder for example such as the solder layer 28(of lead-free solder).Subsequently, make the probe 51 Contact welding bed of materials 28 to carry out the wafer probe test.Obviously this test is optional.
Subsequently, as shown in Figure 20, the cutting edge of the wafer 1 on the 1a side of performer surface as required.
Subsequently, as shown in Figure 21, support substrates 31(is the glass support wafer for example) be attached to the device surface 1a side of wafer 1 via adhesion layer 29.
Subsequently, as shown in Figure 22, in the situation that there is support substrates 31 on wafer, back of the body surface 1b(the second first type surface to wafer 1) carry out the film reduction processing of processing such as grinding back surface, thereby expose the bottom that connects through hole electrode 9, or rather, connect the bottom of through hole master metal electrode 9a.By the film reduction processing of carrying out herein, the thickness of wafer is reduced to the value close to the target thickness of final wafer.Therefore the original thickness (for example approximately 700 μ m) that amount of grinding equals wafer deducts poor that the target thickness (for example approximately 50 μ m) of wafer obtains.
Subsequently, as shown in Figure 23, for example, by adopting dry ecthing (adopting halogen based gases as gas system), the silicon substrate on the 1b side of the back of the body of etched wafer 1 surface slightly, and it is slightly outstanding from the back of the body surface 1b of wafer 1 to make to connect through hole electrode 9 grades.This etching is so-called back etched.
Subsequently, as shown in Figure 24, on the almost whole surface of the wafer 1 at the back of the body on surperficial 1b side, the resin molding of coating such as polyimides is as back side dielectric film 32, subsequently by CMP or eat-back its planarization and again expose the bottom that connects through hole electrode 9.Subsequently, for example, by sputter, on the almost whole surface of the wafer 1 on the surperficial 1b side of the back of the body, form successively such as titanium film, copper film, nickel film etc. from wafer 1 side.For example pass through subsequently the film lamination of wet etching patterning gained to form back side pad 33.Subsequently, by wafer being exposed to the adhesion that reduces adhesion layer 29 through the ultraviolet light of support substrates 31, with the surperficial 1a(device surface from wafer 1) remove support substrates 31 and adhesion layer 29.
Subsequently, as shown in Figure 25, wafer 1(1x) back of the body surface 1b is attached to cutting belt 34, and cutting belt 34 is attached to cutting frame.In this state, for example by scribing by wafer 1(1x) be divided into independently chip region.
Subsequently, as shown in Figure 26, for example, by the scolder bonding, in a similar manner the backside bond pad 33 on the back of the body surface 1b of the chip 2 (2x) cut apart is bonded to the salient pole 30 on the device surface 1a of another chip 2 (2y).By this bonding, a plurality of perforation through hole electrodes are coupled to the salient pole be provided on second half conductive substrate.
Subsequently, as shown in Figure 27, for example, by scolder bonding (referring to the flip-chip bonding), make upper weld pad (land) 36 on the upper surface of salient pole 30 on the device surface 1a of chip 2 (2x) and multilayer wiring substrate 35 coupled to each other.Subsequently, for example, by refluxing, make outside solder projection electrode 38(soldered ball) be attached to the lower weld pad 37 on the lower surface of multilayer wiring substrate 35.Therefore almost complete the BGA(ball grid array).
4. the wafer probe in the manufacture method of the semiconductor device according to first embodiment of the invention is tested to remarked additionally (Figure 28).
This part has illustrated for overcoming each added technique of all in wafer probe, testing contingent problem in the mill.Therefore this method is optional.
Figure 28 is the circuit diagram in the chip region of wafer, and it is the wafer probe test according to the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes.Based on this accompanying drawing, will be remarked additionally to the test of the wafer probe in the manufacture method of the semiconductor device according to first embodiment of the invention.
For example, in embodiment explained above (Figure 18 or Figure 19), nearly all perforation through hole electrode 9 all has connectivity with the substrate zone 1s of wafer 1.Be electrically coupled to while for the electrode (electrode pad 24p or salient pole 30) of wafer probe test and this electrode, being the data input electrode when some connects through hole electrode 9, sometimes can not be tested.
The example of the method for avoiding this inconvenience below will be described.Suppose as shown in Figure 28, the LSI internal circuit IC and this data input electrode pad 24pi that are electrically coupled to this chip 2 such as output electrode pad 24pg, data input electrode pad 24pi etc. for example are coupled to one that connects in through hole electrode 9x and 9y via input/output circuitry IF.When data input electrode pad is coupled to while connecting through hole electrode 9x, even data input to data input electrode pad 24pi, sometimes can not proper testing, because for example the 1s of Semiconductor substrate section in ground potential can exert an influence.
In this example, for fear of this situation, for example between LSI internal circuit IC and input/output circuitry IF, insert switch or switching circuit SW with by from switch control electrode pad 24ps(usually in on-state) signal disconnect.This just can carry out normal probe test.
5. to the VC(voltage-contrast in the manufacture method of the semiconductor device according to first embodiment of the invention) test remarked additionally (mainly with reference to Figure 29 and 30)
In this part, the conductive test of the perforation through hole electrode by adopting electron beam etc. to carry out is described, this test case is (completing while connecting filling through hole) as carried out in the step of the Figure 11 in part 2.
Figure 29 is the schematic cross-section of wafer that connects the periphery of through hole, and it is the PVC test (positive voltage contrast) according to the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes.Figure 30 is the schematic cross-section of wafer that connects the periphery of through hole, and it is the NVC test (negative voltage contrast) according to the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes.Based on above-mentioned accompanying drawing, by hereinafter to the VC(voltage-contrast in the manufacture method of the semiconductor device according to first embodiment of the invention) test remarked additionally.
(1) explanation (mainly with reference to Figure 29) of PVC test
This voltage-contrast test can be divided into roughly two types.A kind of is the contrast of PVC(positive voltage) test, wherein the surperficial 1a side of wafer 1 is just charged, and another kind is the contrast of NVC(negative voltage) test, wherein the surperficial 1a side of wafer 1 is born charging.At first the PVC test is described.
In PVC test, as shown in Figure 29, when connecting through hole electrode 9n when normal, from the 1s of Semiconductor substrate section, to it, provide electronics, in order to charging does not occur and electrode looks bright.On the other hand, when connecting through hole electrode 9d in non-conductive state, from the 1s of Semiconductor substrate section, to it, do not provide electronics, therefore charging and electrode occur and look dim.
Therefore, because in manufacturing step, the bottom of all perforation through hole electrodes all is electrically coupled to the 1s of Semiconductor substrate section basically, this just can be within the very short stage completed after connecting the burying of through hole electrode easily at improper perforation through hole electrode with normally connect between through hole electrode and distinguish.This also is applicable to following NVC test fully.
(2) explanation (mainly with reference to Figure 30) of NVC being tested
In the NVC test, as shown in Figure 30, connect through hole electrode 9n normally and provide electronics from the 1s of Semiconductor substrate section to it, therefore charging and electrode do not look dim.On the other hand, when connecting through hole electrode 9d in non-conductive state, to it, do not provide electronics, therefore charged and electrode looks bright.
(3) the suitable moment of these tests
Shown in the example in the suitable moment of these tests Figure 11, Figure 38, Figure 42 and Figure 51 (all when completing filling through hole) in part 2.Therefore, by the device surface by wafer, be exposed to electron beam, can just after completing, (need not wait for subsequent step) and relatively easily test the conduction state that many (a plurality of) connect through hole electrode.
6. to the supplementary notes (mainly with reference to Figure 31 to Figure 33) of the improvement of the contact resistance at the perforation via bottoms place in the manufacture method of the semiconductor device according to the first embodiment of the present invention.
This part explanation is in the additional method that connects the electric coupling state between through hole electrode 9 and the 1s of Semiconductor substrate section for further raising mentioned above.
Figure 31 be illustrate from the MISFET of Fig. 2 intercepting and connect through hole periphery wafer area R1 and corresponding to the schematic cross-section (introducing the step that connects the via bottoms heavily doped region) of Fig. 9, it is the lifting according to the contact resistance of the via bottoms of the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes.Figure 32 be illustrate from the MISFET of Fig. 2 intercepting and connect through hole periphery wafer area R1 and corresponding to the schematic cross-section (introducing the step that connects the via bottoms disilicide layer) of Fig. 9, it is the lifting according to the contact resistance of the via bottoms of the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes.Figure 33 be illustrate from the MISFET of Fig. 2 intercepting and connect through hole periphery wafer area R1 and corresponding to the schematic cross-section of Figure 15 (bury and planarization connects the step of through hole electrode), it is the lifting according to the contact resistance of the via bottoms of the manufacture method of the semiconductor device of the first embodiment of the present invention for supplementary notes.Improvement based on above-mentioned accompanying drawing to the contact resistance at the via bottoms place in the manufacture method of the semiconductor device according to first embodiment of the invention is remarked additionally.
(1) describe (mainly with reference to Figure 31) to connecting via bottoms introducing heavily doped region
As shown in Figure 31, for example complete the stage that removes dielectric film from the perforation via bottoms 16b shown in Fig. 9, for example, by Implantation, from the device surface 1a of wafer 1, concentration for example, is introduced to for example p-type silicon substrate of the 1s(of Semiconductor substrate section higher than the p-type impurity (boron) of the impurity concentration of Semiconductor substrate section).Below the standard example of injection condition: implant angle: right angle basically, dosage: for example approximately 1 * 10 15/ cm 2, and Implantation Energy: about 50KeV for example.By in perforation via bottoms 16b is in the 1s of Semiconductor substrate section, providing heavily doped region 39, can between perforation through hole electrode 9 and the 1s of Semiconductor substrate section, form ohmic contact.
Can utilize such as the pattern of resin molding and carry out Implantation.Perhaps, can be in the situation that do not adopt etchant resist to carry out Implantation with self-aligned manner, and in this case, it is simpler that technique can become.On the other hand, adopt etchant resist to improve the degree of freedom of technique.
As shown in Figure 8, can when having dielectric film, the perforation via bottoms carry out Implantation.But need in this case slightly high Implantation Energy.This method also has advantages of the technique of simplification.
As shown in Figure 9, carry out Implantation when can also on connecting via bottoms, there is sacrificial oxidation film.Its advantage is the introducing of having got rid of pollutant.
When the 1s of Semiconductor substrate section is N-type, the impurity that introduce is N-type, for example phosphorus or arsenic.
As mentioned above, according to this technique, for example, because at least when completing the perforation filling through hole (Figure 11), near each connects the lower end of through hole electrode, have with substrate section identical conduction type the zone that is heavily doped and be formed in Semiconductor substrate section, so each connects through hole electrode and Semiconductor substrate section all has good contact.
(2) introduce the explanation (mainly with reference to Figure 32) of metal silicide film to connecting via bottoms
After the step of Figure 31, as shown in Figure 32, by the example that forms its material of metal silicide film 46(on the surface at heavily doped region 39, comprise Ni-based silicide, tungsten silicide, cobalt silicide and platinum base silicide) and further reduce contact resistance.Because metal silicide layer is formed on each and connects between through hole electrode and near semiconductor region thereof, so it has advantages of improvement being in contact with one another between the two.
(3) to the explanation (mainly with reference to Figure 33) of the modified example of the detailed construction of the barrier metal film on the inner surface that connects through hole
As shown in Figure 33, for example complete perforation via bottoms 16b from Fig. 9 remove dielectric film after and forming and connecting through hole barrier metal film 9b before, for example by the titanium film 9c(that forms relative thin on the almost whole surface that sputters at the wafer 1 on device surface 1a side, for example there is the thickness of 10nm), i.e. titanium nitride film shown in Figure 10.Form the barrier metal structure by adopting as the titanium film of outer membrane and as the titanium nitride film of internal membrane, because the adhesiveness that improves titanium film and oxidation film etc. and reduction can be guaranteed good contact performance to the reduction of silicon.
7. the perforation through hole in the manufacture method of the semiconductor device according to first embodiment of the invention is formed to the explanation (mainly with reference to Figure 34 to Figure 39) of the modified example (through hole last process) of technique.
In this part, by the example of explanation through hole last process, as the modified example of the technique illustrated in part 2 grades.This technological process is substantially similar to the flow process shown in Fig. 4 to Figure 27, and difference is to connect the part of through hole, because connect the time that the moment from time that completes the metal proparea that through hole forms has been transferred to higher level's burial wiring 22.Therefore, in principle, hereinafter explanation is depended on to the transition that connect the moment that through hole forms and the part changed.
Here the through hole last process will be described, the perforation through hole wherein started after basically completing burial wiring formation step forms.In order to simplify accompanying drawing, as the structure of second or more senior burial wiring of dual-damascene structure, will be depicted as the simplified structure be similar to as the first order burial wiring of single inlay structure.
Figure 34 illustrates from the MISFET of Fig. 2 intercepting and connects the schematic cross-section (when completing higher level's burial wiring and form step) of wafer area R1 of the periphery of through hole, and it forms the modified example (through hole last process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 35 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (patterning connects through hole to form the step of etchant resist), and it is the modified example (through hole last process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 36 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects through hole), and it is the modified example (through hole last process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 37 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects through hole lining dielectric film and perforation through hole barrier metal film), and it forms the modified example (through hole last process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 38 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (burying the step that also planarization connects through hole electrode), and it is the modified example (through hole last process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 39 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (final passivation step), and it forms the modified example (through hole last process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Based on above-mentioned accompanying drawing, explanation is formed to the modified example (through hole last process) of technique according to the perforation through hole in the manufacture method of the semiconductor device of first embodiment of the invention.
As shown in Figure 34, be similar to Fig. 4 to Figure 18, form subordinate and intergrade burial wiring 42, complete subsequently higher level except pad layer etc. the higher level's burial wiring of 22(that connects up) bury.
Subsequently, as shown in Figure 35, be similar to Fig. 5, on device surface 1a(surface) form on the almost whole surface of wafer 1 on side and connect through hole and form etchant resist 15, for example adopt subsequently typical photoetching to carry out patterning.
Subsequently, as shown in Figure 36, be similar to Fig. 6, utilize the perforation through hole of patterning to form etchant resist 15 as mask, by anisotropic dry etch (adopt for the carbon fluorine base gas of the membranous part that insulate and for the halogen based gases of substrate section as gas system) form connect through hole 16(and for example there is the top diameter of about 20 μ m and the about degree of depth of 60 μ m), connect through hole 16 through inter wiring layer insulating film 20 and metal before dielectric film 6 arrive the inside of the 1s of Semiconductor substrate section.For example by ashing, remove and become unnecessary etchant resist subsequently.
Subsequently, as shown in Figure 37, be similar to Fig. 7, on the almost whole surface of the wafer 1 on device surface 1a side (face side), for example, by CVD, form silica-based dielectric film (the ozone TEOS film that for example there is about 200nm thickness), thereby form, connect through hole lining dielectric film 11.Subsequently, as in Fig. 8 and 9, by anisotropic dry etch from connecting through hole lining dielectric film 11(hole) bottom 16b remove and connect through hole lining dielectric film 11.Subsequently, as in Figure 10, on the almost whole surface of the wafer 1 of device surface 1a side (comprising the inner surface that connects through hole 16), for example, by the MOCVD(metallorganic CVD) or sputter (for example ionizing sputter), titanium nitride film (thickness that for example there is about 30nm) formed as connecting through hole barrier metal film 9b.
Subsequently, as shown in Figure 38, as in Figure 11, connecting on through hole barrier metal film 9b and, on the whole surface (comprising the inner surface that connects through hole 16) of the wafer 1 on device surface 1a side, for example for example, by sputter (ionizing sputter), forming the copper seed crystal film.Subsequently, for example by usining the copper seed crystal film, as inculating crystal layer, electroplated, the upper copper film (comprising the seed crystal film) that forms that (comprises the inner surface that connects through hole 16) on whole surface, fill thus and connect through hole 16.Subsequently, by metal CMP, by metal CMP, remove the copper film that connects through hole 16 outsides and connect through hole barrier metal film 9b, thereby forming by connecting through hole master metal electrode 9a(copper film), connect the perforation through hole electrode 9 that through hole barrier metal film 9b etc. forms.
Subsequently, as shown in Figure 39, as in Figure 18, higher level connect up on 22 form under pad interlayer dielectric 20p and bury therein tungsten plug 23.Subsequently, as shown in Figure 18, electrode pad 24p(is aluminium base pad for example) be formed on lower pad interlayer dielectric 20p upper and it on the part except bonding pad opening by final passivating film 25 coverings.Therefore, at least one connects the wiring that through hole electrode utilization belongs to pad layer and is electrically coupled to pad.
Step after this is similar to referring to figs. 18 to 27 described situations, therefore omits its repeat specification herein.
So far, in this section in the example of explanation, form the perforation through hole electrode during the step that forms the higher level's wiring except pad layer.Therefore its advantage is to form electrode to separate with the formation step of the centre that need to process in short-term or subordinate's wiring.In brief, its advantage is to have the treatment facility formation perforation through hole electrode of relative rough grade by employing.
8. the perforation through hole in the manufacture method of the semiconductor device according to first embodiment of the invention is formed to the explanation (mainly with reference to Figure 40 to Figure 46) of the modified example (via-first-polysilicon process) of technique
In this section, the example of, technique part 2 etc. described in constantly as the formation that change to connect through hole using the example of explanation via-first-polysilicon process.Technological process is substantially similar to the flow process described in Fig. 4 to Figure 27, difference is to connect the part of through hole, because only connect moment that through hole forms from the passage of time that completes the metal proparea to the part that completes STI district and impurity doped region time of (for example the N well region WN Fig. 2, p well region WP etc.).Therefore the part that passing according to the moment that connects through hole formation changes will be described in principle hereinafter.
Figure 40 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects through hole), and it is the modified example (via-first-polysilicon process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 41 is the schematic cross-section (form and connect also etched step of through hole lining dielectric film) that the wafer area R1 of the MISFET intercepted from Fig. 2 and the periphery that connects through hole is shown, and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 42 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (burying the step that also planarization connects through hole electrode), and it is the modified example (via-first-polysilicon process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 43 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step of gate insulating film), and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 44 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section (step of etch-gate dielectric film) of the wafer area R1 of the periphery that connects through hole, and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 45 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step of gate electrode film), and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 46 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (step of processing gate electrode film), and it forms the modified example (via-first-polysilicon process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Based on above-mentioned accompanying drawing, explanation is formed to the modified example (via-first-polysilicon process) of technique according to the perforation through hole in the manufacture method of the semiconductor device of first embodiment of the invention.
As shown in Figure 40, when completing STI district 3 grade, form perforation through hole formation etchant resist 15(on the almost whole surface of the wafer 1 on device surface 1a side and for example there is the approximately thickness of 5 μ m), for example by typical photoetching, carry out patterning subsequently.Subsequently, utilize the perforation through hole of patterning to form etchant resist 15 as mask, carry out anisotropic dry etch and there is the perforation through hole 16(of circular planar form basically with formation and there is the top diameter of about 3 μ m and the about degree of depth of 20 μ m).For example utilize subsequently ashing to remove and become unnecessary etchant resist.The inner surface 16i that connects through hole 16 can be towards bottom vertical or convergent slightly.
Subsequently, as shown in Figure 41, as in Fig. 7, on the almost whole surface of the wafer 1 on device surface 1a side, for example, by CVD, form silica-based dielectric film (the ozone TEOS film that for example there is about 200nm thickness), thereby form, connect through hole lining dielectric film 11.Subsequently, as shown in Figure 8, form to connect the via bottoms dielectric film on the almost whole surface of the wafer 1 on device surface 1a side and remove etchant resist 17(and for example there is the approximately thickness of 1 μ m), for example by typical photoetching, carry out patterning subsequently.Subsequently, as shown in Figure 9, for example utilize the perforation via bottoms dielectric film of patterning to remove etchant resist 17 as mask, carry out anisotropic dry etch from connecting via bottoms 16b, to remove dielectric film.Subsequently, for example by ashing, remove and become unnecessary etchant resist.
Subsequently, as shown in Figure 42, the device surface 1a of thermal oxidation wafer 1 is to form thin silicon oxide film (expendable film).For example, for example by CVD, on whole expendable film, form boron doped polycrystalline silicon fiml subsequently in order to fill and connect through hole 16 with this.Subsequently, for example by dry eat-backing, remove the polysilicon film that connects through hole 16 outsides and also for example by wet etching, remove expendable film.Therefore, polysilicon perforation through hole electrode 9p is buried in and connects in through hole 16.
Subsequently, as shown in Figure 43, form gate insulating film 4 on the almost whole device surface 1a of wafer 1.
Subsequently, as shown in Figure 44, for example on the surface of the almost whole wafer 1 on device surface 1a side, form gate insulating film etching etchant resist 43, for example by typical photoetching, carry out patterning subsequently.Subsequently, utilize the gate insulating film etching etchant resist 43 of patterning as mask, etch-gate dielectric film 4 is to connect on through hole electrode 9p and to form opening at polysilicon.For example use subsequently ashing to remove and became unnecessary etchant resist.
As shown in Figure 45, for example by CVD, on the almost whole device surface 1a of wafer 1, forming will be as the conducting film 5(of grid polysilicon film for example).
Subsequently, as shown in Figure 46, form grid processing etchant resist 44 on the almost whole device surface 1a of wafer 1, for example by typical photoetching, carry out patterning subsequently.Subsequently, for example utilize the grid processing etchant resist 44 of patterning to carry out anisotropic dry etch as mask, thus patterning grid 5 etc.Subsequently, for example by ashing, remove and become unnecessary etchant resist.
After this carry out the burying etc. of formation, conductive plunger 7 of dielectric film 6 before the formation, metal of introducing, the sidewall of source and leakage, obtain thus the structure that is similar to Fig. 4 or Figure 16.
In the example illustrated in this section, for example during gate electrode forms step, carry out and connect burying and being different from the film formed moment execution of gate electrode (technique during difference) of through hole electrode.Perhaps it can carry out with the formation of gate electrode film (technique simultaneously) simultaneously.The former advantage is to simplify technique, and the latter's advantage is to simplify processing step.
9. the perforation through hole in the manufacture method of the semiconductor device according to first embodiment of the invention is formed to the explanation (mainly with reference to Figure 47 to Figure 54) of the modified example (via-first contact process) of technique
The example of this part explanation via-first contact process connects as changing the example that through hole forms technique constantly, described in part 2 etc.Technological process is substantially similar to the flow process described in Fig. 4 to Figure 27, difference is to connect the part of through hole, because only connect zero hour that through hole forms from the passage of time that completes the metal proparea to the time that completes grid (before the formation such as dielectric film 6 after the formation of the introducing in patterning grid, source and leakage, sidewall etc. and metal).Therefore the part changed according to the passing that connects the moment that through hole forms only is described in principle hereinafter.
Figure 47 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (form and connect the through hole step), and it is the modified example (via-first contact process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 48 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects through hole lining dielectric film), and it is the modified example (via-first contact process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 49 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (removing the step that connects the via bottoms dielectric film), and it forms the modified example (via-first contact process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 50 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step that connects the through hole barrier metal film), and it is the modified example (via-first contact process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 51 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (burying the step that also planarization connects through hole electrode), and it is the modified example (via-first contact process) according to the perforation through hole formation technique of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 52 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step of contact hole), and it forms the modified example (via-first contact process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 53 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (forming the step of metal plug barrier metal film), and it forms the modified example (via-first contact process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Figure 54 illustrates from the MISFET of Fig. 2 intercepting and the schematic cross-section of the wafer area R1 of the periphery that connects through hole (burying the also step of planarize conductive connector), and it forms the modified example (via-first contact process) of technique according to the perforation through hole of the manufacture method of the semiconductor device of the first embodiment of the present invention for explanation.Based on above-mentioned accompanying drawing, the modified example (via-first contact process) that forms technique according to the perforation through hole in the manufacture method of the semiconductor device of first embodiment of the invention will be described.
For example, after completing grid, as shown in Figure 47, form perforation through hole formation etchant resist 15(on the almost whole surface of the wafer 1 on device surface 1a mono-side and for example there is the approximately thickness of 5 μ m), for example by typical photoetching, carry out patterning subsequently.Subsequently, for example utilizing the perforation through hole of patterning to form etchant resist 15 carries out anisotropic dry etch as mask and has the perforation through hole 16(of circular planar form basically with formation and for example have the top diameter of about 3 μ m and the about degree of depth of 20 μ m).For example by ashing, remove and become unnecessary etchant resist subsequently.The inner surface 16i that connects through hole 16 can be towards bottom vertical or convergent slightly.
Subsequently, as shown in Figure 48, on the almost whole surface of the wafer 1 on device surface 1a side, for example pass through CVD, form silica-based dielectric film (for example, thering is for example ozone TEOS film of about 200nm thickness), thereby form, connect through hole lining dielectric film 11 and the front dielectric film 6a of main metal.Subsequently, for example, by CVD, on the almost whole surface of the wafer 1 on device surface 1a side, form silica-based dielectric film (the plasma TEOS film that for example there is about 100nm thickness) as the cap layer metal before dielectric film 6b.
Subsequently, as shown in Figure 49, for example utilize perforation via bottoms dielectric film to remove etchant resist 17 as mask, remove the front dielectric film 6b of the cap layer metal connected in through hole 16 and connect the perforation through hole lining dielectric film 11 on via bottoms 16b.For example remove and become unnecessary etchant resist by ashing subsequently.
Subsequently, as shown in Figure 50, for example, by the MOCVD(metallorganic CVD) or sputter (ionization sputter), the upper titanium nitride film (thickness that for example has about 30nm) that forms in the almost whole surface of the wafer 1 on device surface 1a side (comprising the inner surface that connects through hole 16) is as connecting through hole barrier metal film 9b.
Subsequently, as shown in Figure 51, for example by CVD(, adopt the B for nucleation 2h 6/ WF 6and the H that is used to form top layer 2/ WF 6as gas system) form tungsten film on titanium nitride film 9b and on the almost whole surface of the wafer 1 on device surface 1a side (comprising the inner surface that connects through hole 16), connect through hole 16 in order to fill.Subsequently, carry out metal CMP to remove tungsten film and the titanium nitride film 9b that connects through hole 16 outsides.
Subsequently, as shown in Figure 52, form contact hole on the almost whole surface of the wafer 1 on device surface 1a side and form etchant resist 45, for example by typical photoetching, carry out patterning subsequently.Utilize the contact hole of patterning thus to form etchant resist 45 as mask, for example for example, by anisotropic dry etch (adopting the carbon fluorine base gas as gas system), form contact hole 40.For example by ashing, remove and become unnecessary etchant resist subsequently.
Subsequently, as shown in Figure 53, for example, for example, by MOCVD or sputter (ionizing sputter), the upper formation in the almost whole surface (inner surface that comprises contact hole 40) of the wafer 1 on device surface 1a side is metal plug barrier metal film 7b as titanium nitride film.
Subsequently, as shown in Figure 54, for example by CVD(, adopt the B for nucleation 2h 6/ WF 6and the H that is used to form top layer 2/ WF 6as gas system), the almost whole surface (inner surface that comprises contact hole 40) of the wafer 1 on device surface 1a side upper deposition tungsten film 7a, so that filling contact hole 40.Subsequently, carry out tungsten film 7a and the metal plug barrier metal film 7b of metal CMP to remove contact hole 40 outsides.Connect through hole electrode 9 except completing, can obtain the situation shown in Fig. 4 that is equal to.
Therefore subsequent step is basically identical with the step shown in Fig. 5 to Figure 27, therefore omits repeat specification herein.
In the above-mentioned example of this part, during contact forms step, carry out connect through hole electrode burying and in the formation from contact plunger the different moment carry out when different (technique).Perhaps, carry out (technique simultaneously) with the formation of contact plunger simultaneously.When different, the advantage of technique is to simplify technique, and the advantage of technique is to simplify processing step simultaneously.
10. to the supplementary notes of above-described embodiment (comprising modified example) and overall conditions
(1) characteristics of the problem of TSV and each example:
At TSV, that in the Semiconductor substrate such as silicon substrate, manufactures is formed in the perforation through hole electrode in through hole (through hole), the perforation through hole of main explanation is formerly in positive through hole type technique in this article, usually lower end was sealed before wafer grinding, and this just is difficult to carry out conductive test to connecting through hole electrode.In addition, the Semiconductor substrate section of wafer usually connects through hole electrode insulation with each, therefore may exist by the defect punctured such as grid of burying generation while connecting undesirable charging that the technique after through hole electrode causes.
In above-described embodiment (comprising modified example), utilize the combination of technique,, be suitable for that hole in the Semiconductor substrate of micro-manufacture forms and the inner surface in hole on the formation of lining dielectric film as basis, with the perforation through hole electrode textural association with the lower end of establishing road by cable, use, thereby realize being suitable for the perforation through hole electrode technique of micro-manufacture, below will specifically describe.
(2) to connecting the consideration in the moment that through hole electrode forms: as main in part 1 to 6 advantage of the through hole middle process of explanation be to form low-resistance to connect through hole electrode, for example, because can adopt micro-manufacture and the while of subordinate's wiring (first order burial wiring), copper etc. can be used as connecting the main material of through hole electrode.
On the other hand, the through hole middle process of main explanation in part 7 can not adopt the micro-manufacture adopted in through hole middle process or via-first technique, but its advantage is to adopt the main material as the perforation through hole electrode such as low-resistance copper substantially completing wafer technique after.
Because, as in the via-first-polysilicon process of main explanation in part 8, the perforation through hole electrode formed before the step of source-leakage introducing, therefore considered from thermally equilibrated position, this technique is favourable.Polysilicon is that very stable material and its can not cause any pollution in technique.On the other hand, even with tungsten etc., compare, add boron (or phosphorus etc.) and enlarge markedly resistance.Via-first-polysilicon process belongs to via-first technique, so its advantage is the micro-manufacture that adopts the FEOL step.
As the via-first-contact process of main explanation in part 9 can adopt material such as the relative low-resistance of tungsten as the main material that connects through hole electrode, so it can realize relatively low resistance.Via-first-contact process belongs to via-first technique, so its advantage is micro-manufacture that can adopt the FEOL step.
11. sum up
Based on embodiment, understand specifically the present invention that the inventor proposes.But it should be noted that and the invention is not restricted to above-described embodiment or limited by above-described embodiment.Obviously in the situation that do not break away from main points of the present invention and can be changed the present invention.
For example, in the above-described embodiments, utilize the grid first process to illustrate the present invention as example.But the invention is not restricted to this, obviously the present invention can be applicable to FUSI technique, high k is preferential and grid last process, high k and grid last process, the last hybrid technique of P side grid etc.
In the above-described embodiments, understand specifically the structure that adopts copper base burial wiring (comprising money base burial wiring etc.).But the invention is not restricted to adopt the structure of burial wiring as the main wiring system, obviously the present invention can be applicable to adopt the structure of aluminium base non-burial wiring as the main wiring system.
In addition, in the above-described embodiments, the present invention will be described as example to utilize the main pad layer (comprising the pad layer only consisted of pad) by aluminium base non-burial wiring, but the invention is not restricted to this.Obviously the present invention also can be applicable to the pad layer (comprise the money base burial wiring and comprise the pad layer only consisted of pad) consisted of copper base burial wiring.

Claims (19)

1. the manufacture method of a semiconductor device comprises step:
(a) preparation has device first type surface and the surperficial semiconductor wafer of the back of the body;
(b) semiconductor surface area from the described device first type surface of described semiconductor wafer to described semiconductor wafer forms its inner hole of a plurality of arrival;
(c) form dielectric film on the inner surface in described hole; And
(d) in step (c) afterwards, when utilizing described dielectric film to cover the described inner surface except the bottom in described hole in described hole, buried conductive member in described hole, and form thus a plurality of perforation through hole electrodes.
2. the manufacture method of semiconductor device according to claim 1 also comprises step:
(e), in wafer technique, at least one described perforation through hole electrode is electrically coupled to gate electrode.
3. the manufacture method of semiconductor device according to claim 2,
Wherein, utilize the through hole middle process to form described perforation through hole electrode.
4. the manufacture method of semiconductor device according to claim 3,
Wherein, in the step that forms first order wiring but bury described perforation through hole electrode being different from the moment of burying described first order wiring.
5. the manufacture method of semiconductor device according to claim 3,
Wherein, side by side bury described perforation through hole electrode with burying of first order wiring.
6. the manufacture method of semiconductor device according to claim 2,
Wherein, utilize the through hole last process to form described perforation through hole electrode.
7. the manufacture method of semiconductor device according to claim 6,
Wherein, the described perforation through hole electrode of formation during the step that forms the higher level's wiring except pad layer.
8. the manufacture method of semiconductor device according to claim 7,
Wherein, at least one described perforation through hole electrode is electrically coupled to pad by the wiring that belongs to described pad layer.
9. the manufacture method of semiconductor device according to claim 2 also comprises step:
(f) in step (d) afterwards but during wafer technique, to the described device first type surface irradiating electron beam of described wafer to test the conduction state of described perforation through hole electrode.
10. the manufacture method of semiconductor device according to claim 2,
Wherein, utilize via-first technique to form described perforation through hole electrode.
11. the manufacture method of semiconductor device according to claim 10,
Wherein, form in step but carry out burying of described perforation through hole electrode being different from the moment that forms gate electrode film at gate electrode.
12. the manufacture method of semiconductor device according to claim 10,
Wherein, side by side carry out burying of described perforation through hole electrode with the formation of gate electrode film.
13. the manufacture method of semiconductor device according to claim 10,
Wherein, form in step but carry out burying of described perforation through hole electrode being different from the moment that forms contact plunger in contact.
14. the manufacture method of semiconductor device according to claim 10,
Wherein, side by side carry out burying of described perforation through hole electrode with the formation of contact plunger.
15. the manufacture method of semiconductor device according to claim 2,
Wherein, at least in step (d) afterwards, near the semiconductor region lower end of each of described perforation through hole electrode has heavily doped region, and the conduction type of the conduction type of described heavily doped region and its semiconductor region on every side is identical and have a high impurity concentration.
16. the manufacture method of semiconductor device according to claim 2,
Wherein, described perforation through hole electrode has and mainly usings titanium film as outer and using the barrier metal structure of titanium nitride film as internal layer.
17. the manufacture method of semiconductor device according to claim 2,
Wherein, described perforation through hole electrode each lower end and near semiconductor region between there is metal silicide layer.
18. the manufacture method of semiconductor device according to claim 2 also comprises step:
(g) in step (d) afterwards, from the described back of the body face side of described semiconductor wafer, described semiconductor wafer is carried out to the film reduction processing with the described perforation through hole electrode the described back of the body face side that exposes described semiconductor wafer.
19. the manufacture method of semiconductor device according to claim 18 also comprises step:
(h) in step (g) afterwards, the salient pole provided on second half conductive substrate is provided described perforation through hole electrode.
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