CN101663742A - front-end processed wafer having through-chip connections - Google Patents
front-end processed wafer having through-chip connections Download PDFInfo
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- CN101663742A CN101663742A CN200780047912A CN200780047912A CN101663742A CN 101663742 A CN101663742 A CN 101663742A CN 200780047912 A CN200780047912 A CN 200780047912A CN 200780047912 A CN200780047912 A CN 200780047912A CN 101663742 A CN101663742 A CN 101663742A
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- via hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metalization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.
Description
Technical field
[0001] the present invention relates to semiconductor, and relate in particular to the electrical connection that is used for this device.
The cross reference of related application
[0002] the application requires the sequence number 60/882 of submission on December 29th, 2006 according to 35U.S.C.119 (e), 671 U.S. Provisional Application No. rights and interests, and as the 11/422nd of submission on June 6th, 2006, the extendible portion of 551 U.S. Patent applications, its full content is bonded to herein by reference, as all setting forth in this article.
Background technology
[0003] often wishes that can pass chip with effective and efficient manner forms electrical connection so that be connected to another element.As a rule, with make of conventional method the same, this means the use of via hole and relate to connection, these connect with the periphery that is formed on chip on or near the connection of periphery opposite, near the formation device of chip.
[0004] using a shortcoming of through-chip via hole on (i.e. device supporting (device-bearing)) chip of handling fully is that the cost than the chip of comparable blank wafer of a slice or section processes is more expensive significantly for the chip that is completed into.If the aligning at the via hole that is used for being electrically connected produces mistake, then may damage the device on chip or one or more metal layer, perhaps can not make the connection of hope.
[0005] in both cases, the result may be useless chip, needs discarded this chip.
Summary of the invention
[0006] we have invented a kind of method, so that relevant the risk and cost of use that the through-chip collaborative with installing supports chip is electrically connected minimizes.
[0007] utilizes a kind of being included in to form the execution mode that through-chip connects on the blank wafer, advantageously eliminated the risk (because device does not damage) of damaging device.In addition, if the obsolete problem of the wafer that provides, the influence that yet reduces cost is not created or the back-end processing process because wafer also carries out any device.
[0008] another kind of execution mode is included in and forms the through-chip connection on the wafer that forms device, but does not also finish the back-end processing of adding metal interconnecting layer.Utilize this execution mode, after the first metal layer deposition but before second layer metal deposition, perhaps in general, before any " n " layer deposition that may deposit as the part of back-end processing, can be in that do not have under the situation of pollution risk to form may be to handling very sensitive and needing the transistor in smooth extremely impeccable zone, thereby improve transistor output, via hole also obtains the benefit of routing simultaneously, because can form during the back-end processing before the first metal layer deposition.
[0009] advantage of explanation and feature are several in numerous advantages that can obtain from representational embodiment and the feature in this article, and the present invention only occurs being used for helping to understand.Be to be understood that they are not considered to as the restriction of the present invention that claim limited, perhaps to being equivalent to the restriction of claim.For example, some advantages are in opposition to each other, because they can not be present among the single embodiment simultaneously.Similarly, some advantages are applicable to one aspect of the present invention, and are not suitable for other aspects.Therefore, the summary of feature and advantage should not be considered to determining that aspect the equivalence be conclusive.Additional feature and advantage of the present invention will become apparent from accompanying drawing and in the accessory rights claim in the following description.
Description of drawings
[0010] Fig. 1 illustrates the part of the blank wafer that will be used to illustrate processing with the form of simplifying;
[0011] Fig. 2 illustrates the part of the wafer of the Fig. 1 after via hole forms with the form of simplifying;
[0012] Fig. 3 with the form of simplifying illustrate used simple via and ring-type via hole metal filled one of them after the via hole of Fig. 2;
[0013] Fig. 4 illustrates the part of the wafer of the Fig. 1 after finishing front-end processing with the form of simplifying;
[0014] Fig. 5 illustrates with the form of simplifying and will be used to illustrate the part of replacing the front-end processed wafer of handling;
[0015] Fig. 6 illustrates the part of the front-end processed wafer after via hole forms with the form of simplifying;
[0016] Fig. 7 illustrates the via hole of the Fig. 6 after it has been filled with required conductive filling material with the form of simplifying;
[0017] Fig. 8 illustrates the structure of having added the Fig. 7 after the metal-1 layer during back-end processing with the form simplified; With
[0018] Fig. 9 A to 9D illustrates the sequential steps in the changing method.
Embodiment
[0019] sequence number that is combined in by reference herein is 11/329,481,11/329,506,11/329,539,11/329,540,11/329,556,11/329,557,11/329,558,11/329,574,11/329,575,11/329,576,11/329,873,11/329,874,11/329,875,11/329,883,11/329,885,11/329,886,11/329,887,11/329,952,11/329,953,11/329,955,11/330,011,11/556,747 and 11/422,551 U.S. Patent application has been described and has been used for forming little at semiconductor wafer, dark via hole and the various technology that are used for the electric contact of semiconductor wafer.Via hole density and position that our technology can't obtain before considering, and can on chip or wafer ratio, carry out.
[0020] if desirable be to set up through-chip to be electrically connected, relate to the risk minimization of handling wafer (promptly installing supporting wafer) fully but make, then can use following method.
[0021] in sum, this method directly be included in they should with in case will be arranged in when finishing front-end processing on the relevant position of device on the wafer and form via hole in blank wafer, make hole-through conductive, manufacturing installation on wafer then obtains the connection between connecting of device and through-chip thereby handle by means of device manufacturing.
[0022] particularly, handle from blank wafer, for example silicon (Si), germanium (Ge), silicon-germanium (SiGe), GaAs (GaAs), indium phosphide (InP) or other wafers begin.
[0023] Fig. 1 illustrates the cross section of the part 100 of the blank wafer 102 that will be used to illustrate processing with the form of simplifying.Attention makes ratio distortion substantially in order to state simplification.
[0024] next, if formed device, then with the local corresponding wafer that obtains it on, in wafer, form via hole in the position of selecting in advance.Depend on specific execution mode, may comprise that use is for example above-mentioned in conjunction with applying for that one of described technology forms via hole.In other words, perhaps in addition, via hole can be handled by other that comprise for example laser drilling and form.
[0025] Fig. 2 illustrates the part 100 of the blank wafer 102 after via hole 202,204,206 forms with the form of simplifying.As shown in the figure, the via hole in the part comprises a simple via 202 and two ring-type via holes 204,206.Note,,, but stop, coming off to prevent newel in short distance from the bottom surface 104 of wafer so via hole does not have complete through-wafer because use the ring-type via hole.
[0026] in case via hole form, by with can standing specific front-end treatment step and particularly, device in setting up related temperature and the conductor of stress come filled vias, make hole-through conductive.For example, handle if will carry out CMOS, then conductor can be any Au, Cu, Ni, W, Ti or any other metal, perhaps can stand the alloy of temperature related in the CMOS processing.Optionally, can with before conductor filled with dielectric or insulator layer coating via hole, with prevent or guarantee conductor not can with the substrate short circuit.
[0027] depends on specific execution mode, can comprise that any other that use vapor deposition process, electroplating processes or cause that via hole fills handle filled vias.In other words, if using the ring-type via hole handles, then the ring-type via hole can be filled suitably firm insulator, and newel can be by complete reservation (promptly not removing), so that during front-end processing, newel can suitably be mixed, thus itself serve as conductor and in this via hole at all without any need for metal.
[0028] Fig. 3 illustrates with the form of simplifying and is filling simple via 202 with metal 208 and also with the via hole 202,204,206 after the space that one of metal 208 filling ring-type via holes 202 (its newel is removed) is arranged and stay because of removal.Notice that ring-type via hole 204,206 all has been filled with appropriate insulation body 210.But the newel 212 within the second ring-type via hole 206 is not removed, so that it can become conductor during front-end processing.
[0029] under the situation of using the ring-type via hole, bottom surface 104 attenuation that can make wafer now are to expose the bottom of conductor metal 208 or newel 212.As will discerning, attenuation can not influence the via hole 206 in the place that newel 212 is retained, because insulator 210 holds it in suitable position.Certainly, if do not use the ring-type via hole, then via hole can through-wafer or as the not through-wafer of expectation, remember that latter event may need attenuation, connect unless for example plan capacitive character.
[0030] in the variation example of another replacement, via hole is through-wafer fully not, and the bottom of wafer and the zone between the via hole be maintained at enough sizes, so that it can become the device zone during front-end processing.
[0031] at this moment, finish the processing of current method, and wafer comprises a whole set of conductive via now.
[0032] after this, wafer can carry out processing of normal front-end and back-end and cutting in a conventional manner.In case finish dealing with, last chip will have and be connected by the through-chip of carrying out the same type that one of above-mentioned associated methods can have, but be in lower risk and may have higher output.
[0033] Fig. 4 illustrates the part of the wafer of the Fig. 1 after finishing front-end processing with the form of simplifying.Therefore, as shown in Figure 4, wafer becomes the wafer 400 of front-end processing and comprises the doped region 402 that device can occur now.Advantageously, by means of its position with respect to device, via hole is electrically connected to the suitable part of device now.
[0034] will form handling very sensitivity and the smooth and extremely impeccable zone of needs, thereby must then can use following method there not being possibility to occur in the transistorized situation that forms under the situation of the pollution risk during via hole forms.
[0035] in sum, this method comprises that directly finishing ability up to front-end processing forms device on wafer, but before one or more stages of back-end processing begin, forms via hole in front-end processed wafer, make and carry out one or more additional back-end processing stages then by hole-through conductive.
[0036] Fig. 5 illustrates the part 500 that will be used to illustrate the wafer 502 of replacing the front-end processing of handling with the form of simplifying.As shown in the figure, wafer 502 is included in established device in the doped region 504.But at this moment, the back-end processing that increases metal interconnecting layer does not take place.
[0037] next, be in wafer in the suitable position that is used for being connected to device or avoids device and form via hole.Depend on specific execution mode, this can comprise that use is for example above-mentioned in conjunction with applying for that one of described technology forms via hole.In other words, perhaps in addition, via hole can be handled by other that comprise for example laser drilling and form.
[0038] Fig. 6 illustrates the part 500 of the wafer 502 of the front-end processing after via hole 602,604,606 forms with the form of simplifying.As shown in the figure, the via hole in the part 500 comprises a simple via 602 (can or can not comprise dielectric or insulator coating arbitrarily) and two ring-type via holes 604,606.Note,,, but stop, coming off to prevent newel in short distance from the bottom surface 506 of wafer 502 so via hole does not have complete through-wafer because use the ring-type via hole.
[0039] in case via hole forms, makes hole-through conductive by filler filled vias with conduction.Depend on specific execution mode, this can comprise that any other that use vapor deposition process, electroplating processes or cause that via hole fills handle filled vias.Depend on specific execution mode, can with the metal level identical materials that is used for forming, for example aluminium, tungsten or copper come filled vias, it can be to be different from the material that will be used to form metal level, for example, and gold, silver or nickel, perhaps be connected directly under the situation of device, be to arrive with via hole and material that specific part that will attached device is complementary, for example, use and polysilicon that the grid material of field-effect transistor is complementary.
[0040] Fig. 7 illustrates with the via hole 602,604,606 after the via hole 602,604,606 of conductive filling material 608 blank maps 6 of wishing with the form of simplifying.Note, as shown in the figure, and before filling conductor, fill the ring-type via hole, and the newel of each ring-type via hole 604,606 is removed with appropriate insulation body 610.
[0041] in the situation of using the ring-type via hole, then the bottom surface 506 of wafer 502 now can attenuation to expose conductive filling material 608.In other words, after this, attenuation (if desired) can occur in certain point.
[0042] next, back-end processing can be from putting down the first rear end articulamentum (being called " metal-1 " layer here).
[0043] Fig. 8 illustrates the structure of adding the Fig. 7 after the metal-1 layers 800 during back-end processing with the form of simplifying.
[0044] advantageously, by using this method, the conductive filling material 608 of given via hole can be connected directly to metal-1 layers 800, perhaps be not connected directly to metal-1 layers 800 as expected, in the previous case, this can pass through plated metal-1 layers 800 and takes place simply, so that the part of metal-1 layers 800 directly contacts and cover the conductive filling material 608 of via hole, such as shown in Figure 8.
[0045] in other words, and advantageously, in the execution mode of an example, for example, if use electroplating processes, then the formation of metal-1 layer can be used as via hole and fills a part of handling and exist.Adopt this method, will make wafer patternization with route that is used for metal-1 layers 800 and the via hole that exposes with being filled.After this, inculating crystal layer (seed layer) is applied to promote electroplating plating generation then.So, the plating " cover layer " that forms in seed crystal (seed) location will form metal-1 layers 800 inherently.In addition, by patterning optionally, as required, specific via hole can " make progress " and run through metal layer, to be connected to one or more specific metal layers (for example, any metal-2 is to metal-N, and wherein " N " is outermost layer).
[0046] can use further favourable replacement changing method, wherein must be connected to metal-2 one or more to metal-N layer.Except photoresist can be used to make the overlay layer patternization, this changing method is similar to the method formerly that is right after.Operable a kind of photoresist is " solid " photoresist that can be used for optionally covering certain via hole, although so that all via holes all are formed in the wafer, those via holes that will be connected to metal-1 layer are exposed to be used for the first round electroplate.As unrestriced example, suitable " solid " photo anti-corrosion agent material comprises available on the market from E.I.du Pont de Nemours ﹠amp; Co's
Dry film photoresist series commodity, perhaps effective other similar photoresists in suitable sheet thickness.Particularly, for
Dry film photoresist series commodity can use photoresist
PlateMaster, EtchMaster and TentMaster series commodity.As
The advantage of photoresist product be that it can be used as that thin slice is placed from the teeth outwards and it has rigidity.Rigidity means that it can cover via hole and allow it to be patterned in the mode that the later time point is easily exposed once more by it.In other words, not the problem of any reason if unintentional via hole is filled, then can use the photoresist of traditional non-solid or viscosity.Fig. 9 A illustrates the sequential steps in the diverse ways that carries out on the example part 900 of wafer 902 to 9D, comprise the use of solid photoresist, the via hole 906,908,910,912 that wafer 902 has had device and formed as described in this article thereon in device zone 904.
[0047] use and the patterning by solid photoresist 905, the formation that will be connected to the filling of via hole 906 of metal-1 layer and metal-1 layer with its conductive filler is by electroplating with conductive filling material 608 and (Fig. 9 A) taking place simultaneously, form metal-1 layer so that electroplate " cover layer ", solid photoresist 905 prevents that other via holes 908,910,912 are by conductive filling material 608 or photoresist filling itself simultaneously.
[0048] planning that should be noted that certain level will be necessary, so that guarantee not have partially metallised layer to surpass the via hole that will be connected to metal layer subsequently.If this can not be avoided, then via hole will be filled within one or more metal layers before need and changing its course in its metallization.Advantageously, big problem does not appear, because the metallized partly cause of making in layer at first changes its course.
[0049] gets back to this method; first " solid " photoresist is removed for 905 layers; and 905 layers of new " solid " photoresists are applied with protection metal-1 layer and via hole 910,912; via hole 910,912 will be connected to other layers and be patterned to expose via hole 908; via hole 908 will be filled when forming metal-2 layer; the applied electroplating of going forward side by side of inculating crystal layer is electroplated " cover layer " as metal-2 layer (Fig. 9 B) with filled vias and use.
[0050] continuous metal layer is repeated this method (Fig. 9 C, Fig. 9 D) repeatedly, up to all via holes all as being connected of needing, wherein can use traditional back-end processing to form remaining metal layer (promptly straight-through metal-N).Significantly, though current back-end processing can comprise more than 10 to 12 layers (be N=10,11,12 or more than), advantageously, the number of the back end layers that no matter finally needs, this method can be identical.
[0051] optionally, replace and then finishing front-end processing etching and manufacturing via hole afterwards, can use any one in two kinds of replacement methods.In an alternative, can carry out front-end processing is added up to the parts of device, via hole is set up and is filled and can take place simultaneously with the foundation of parts then, for example, can carry out etching and filling to via hole in grid conductor (for transistorized grid) deposition.In another alternative, can as above finish front-end processing, but back-end processing will be only up to metal-" X " layer just finish (wherein N be the integrated circuit (IC) chip finished layer last sum and 1＜X＜N), via hole will etchedly reach that layer with filling then.After this, back-end processing will continue, and, optionally, after finishing some additional numbers of plies, before finishing metal-N layer, can repeat this processing.
[0052] also should note, method herein also allows back-end processing to stop at for example intermediate point of simple functions of device to test, if so that any be that inoperative or whole wafers has not enough output to fixed mold, then handle can be stopped or only to chip continuation by this centre test.
Therefore [0053] should be appreciated that this specification (comprising accompanying drawing) only represents some illustrative embodiment.For convenience of the reader, above-mentioned explanation concentrates on the representative example of all possible embodiment, instructs the example of principle of the present invention.This specification does not attempt at large to enumerate all possible variation example.The embodiment that replaces may not occur for specific part of the present invention, perhaps the embodiment of the replacement of further not describing can obtain a part, is not considered to abandon the embodiment of those replacements.One of those skilled in the art will understand many not embodiment of description and combine same principle of the present invention and be equal to mutually.
Claims (26)
1. a method is characterized in that, comprising:
In the device support semi-conductor wafers, form via hole;
Make at least some hole-through conductives in the described via hole in the described device support semi-conductor wafers; And
Described device support semi-conductor wafers is carried out back-end processing, be electrically connected between conductive via and metal layer, to set up.
2. the method for claim 1 is characterized in that, forms via hole and comprises:
Form the ring-type via hole.
3. method as claimed in claim 2 is characterized in that, forms described ring-type via hole and comprises:
Remove at least one newel.
4. the method for claim 1 is characterized in that, at least some hole-through conductives in the described via hole in the blank semiconductor wafer are comprised:
Fill described via hole with one of them of metal, metal alloy, polysilicon.
5. the method for claim 1 is characterized in that, fills described via hole and comprises:
Fill described via hole when forming metal layer.
6. method as claimed in claim 5 is characterized in that described metal layer is a first metal layer.
7. method as claimed in claim 5 is characterized in that described metal layer is the N metal level.
8. method as claimed in claim 5 is characterized in that, described metal layer is the metal level between the first metal layer and the N metal level.
9. method as claimed in claim 5 is characterized in that, fills described via hole when forming described metal layer and comprises:
The applying solid photoresist;
Make described solid photoresist patterning;
Inculating crystal layer is applied to the zone of exposing by patterning; With
Electroplate described inculating crystal layer.
10. the method for claim 1 is characterized in that, fills described via hole and comprises:
After forming at least one metal layer, fill described via hole.
11. the method for claim 1 is characterized in that, carries out described back-end processing and occur in after at least some hole-through conductives that make in the described device support semi-conductor wafers on described device support semi-conductor wafers.
12. the method for claim 1 is characterized in that, on described device support semi-conductor wafers, carry out described back-end processing and comprise via electroplating processes and set up metal-X layer, wherein X 1 and N between.
13. method as claimed in claim 12 is characterized in that, X equals:
1, in 2,3,4,5,6,7,8,9,10,11 or 12.
14. method as claimed in claim 12 is characterized in that X is greater than 10.
15. the method for claim 1 is characterized in that, further comprises:
After the execution of described back-end processing begins, but before back-end processing complete, the device on the described semiconductor wafer is carried out functional test.
16. the method for claim 1 is characterized in that, further comprises:
Applying solid photoresist at least one via hole makes that described at least one via hole will can not be filled with plated metal after described solid photoresist patterning, electroplating processes execution and described solid photoresist are removed.
17. a method is characterized in that, comprising:
In the device support semi-conductor wafers, form via hole;
Make at least some the described hole-through conductives in the described device support semi-conductor wafers; And
Handle described device support semi-conductor wafers, be electrically connected between conductive via and conductive semiconductor layer, to set up.
18. a method is characterized in that, comprising:
In blank semiconductor wafer, form via hole;
Make at least some hole-through conductives in the described via hole in the described blank semiconductor wafer; And
Carry out front-end processing on described blank wafer, with apparatus for establishing on described wafer, described wafer is connected to conductive via.
19. method as claimed in claim 18 is characterized in that, forms described via hole and comprises:
Form the ring-type via hole.
20. method as claimed in claim 19 is characterized in that, forms described ring-type via hole and comprises:
Remove at least one newel.
21. method as claimed in claim 19 is characterized in that, forms described ring-type via hole and comprises:
At least one newel is kept intact, and makes it possible to realize during the front-end processing of described blank semiconductor wafer conduction.
22. method as claimed in claim 18 is characterized in that, at least some hole-through conductives in the described via hole in the described blank semiconductor wafer are comprised:
Fill described via hole with one of them of metal or metal alloy.
23. method as claimed in claim 18 is characterized in that, forms described via hole and comprises:
Form described via hole to the degree of depth littler than the degree of depth that will pass described wafer.
24. method as claimed in claim 23 is characterized in that, carries out front-end processing and comprises:
Form device near the zone that is arranged in the bottom of at least one via hole.
25. method as claimed in claim 18 is characterized in that, describedly carries out front-end processing and comprises:
Form device near the zone that is arranged in the outer end of at least one via hole.
26. method as claimed in claim 18 is characterized in that, further comprises:
Make a side attenuation of the bottom of close at least one via hole of described wafer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88267106P | 2006-12-29 | 2006-12-29 | |
| US60/882,671 | 2006-12-29 | ||
| PCT/US2007/089061 WO2008083284A2 (en) | 2006-12-29 | 2007-12-28 | Front-end processed wafer having through-chip connections |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101663742A true CN101663742A (en) | 2010-03-03 |
| CN101663742B CN101663742B (en) | 2013-11-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007800479122A Active CN101663742B (en) | 2006-12-29 | 2007-12-28 | Front-end processed wafer having through-chip connections |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP2097924A4 (en) |
| JP (2) | JP2010515275A (en) |
| KR (1) | KR101088926B1 (en) |
| CN (1) | CN101663742B (en) |
| WO (1) | WO2008083284A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103441095A (en) * | 2012-03-26 | 2013-12-11 | 瑞萨电子株式会社 | Method of manufacturing a semiconductor integrated circuit device |
| CN104247004A (en) * | 2012-03-12 | 2014-12-24 | 阿尔塔科技半导体公司 | Method for manufacturing semiconductor wafers |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007044685B3 (en) * | 2007-09-19 | 2009-04-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Electronic system and method for manufacturing a three-dimensional electronic system |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03218653A (en) * | 1989-11-13 | 1991-09-26 | Mitsubishi Electric Corp | Semiconductor device provided with air bridge metal wiring and manufacture thereof |
| JP3979791B2 (en) | 2000-03-08 | 2007-09-19 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
| EP2560199B1 (en) * | 2002-04-05 | 2016-08-03 | STMicroelectronics S.r.l. | Process for manufacturing a through insulated interconnection in a body of semiconductor material |
| JP4285629B2 (en) * | 2002-04-25 | 2009-06-24 | 富士通株式会社 | Method for manufacturing interposer substrate mounting integrated circuit |
| JP3748844B2 (en) * | 2002-09-25 | 2006-02-22 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor integrated circuit and test method thereof |
| WO2004064159A1 (en) * | 2003-01-15 | 2004-07-29 | Fujitsu Limited | Semiconductor device, three-dimensional mounting semiconductor apparatus, method for manufacturing semiconductor device |
| JP4322508B2 (en) * | 2003-01-15 | 2009-09-02 | 新光電気工業株式会社 | Manufacturing method of semiconductor device |
| SE526366C3 (en) * | 2003-03-21 | 2005-10-26 | Silex Microsystems Ab | Electrical connections in substrate |
| JP3891299B2 (en) * | 2003-05-06 | 2007-03-14 | セイコーエプソン株式会社 | Semiconductor device manufacturing method, semiconductor device, semiconductor device, electronic device |
| JP4340517B2 (en) * | 2003-10-30 | 2009-10-07 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
| TWI228295B (en) * | 2003-11-10 | 2005-02-21 | Shih-Hsien Tseng | IC structure and a manufacturing method |
| JP4114660B2 (en) * | 2003-12-16 | 2008-07-09 | セイコーエプソン株式会社 | Semiconductor device manufacturing method, semiconductor device, circuit board, electronic device |
| KR100569590B1 (en) * | 2003-12-30 | 2006-04-10 | 매그나칩 반도체 유한회사 | Radio frequency semiconductor device and method of manufacturing the same |
| TW200535918A (en) * | 2004-03-09 | 2005-11-01 | Japan Science & Tech Agency | Semiconductor device and methods for fabricating the same, semiconductor system having laminated structure, semiconductor interposer, and semiconductor system |
| JP3875240B2 (en) | 2004-03-31 | 2007-01-31 | 株式会社東芝 | Manufacturing method of electronic parts |
| JP4492196B2 (en) * | 2004-04-16 | 2010-06-30 | セイコーエプソン株式会社 | Semiconductor device manufacturing method, circuit board, and electronic apparatus |
| US7249992B2 (en) * | 2004-07-02 | 2007-07-31 | Strasbaugh | Method, apparatus and system for use in processing wafers |
| JP2006049557A (en) * | 2004-08-04 | 2006-02-16 | Seiko Epson Corp | Semiconductor device |
| CN101714512B (en) * | 2004-08-20 | 2012-10-10 | 佐伊科比株式会社 | Method of fabricating semiconductor device having three-dimensional stacked structure |
| JP4524156B2 (en) * | 2004-08-30 | 2010-08-11 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| US7838997B2 (en) * | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
| US7767493B2 (en) * | 2005-06-14 | 2010-08-03 | John Trezza | Post & penetration interconnection |
| US7488680B2 (en) | 2005-08-30 | 2009-02-10 | International Business Machines Corporation | Conductive through via process for electronic device carriers |
-
2007
- 2007-12-28 CN CN2007800479122A patent/CN101663742B/en active Active
- 2007-12-28 KR KR1020097014823A patent/KR101088926B1/en active IP Right Grant
- 2007-12-28 WO PCT/US2007/089061 patent/WO2008083284A2/en active Application Filing
- 2007-12-28 JP JP2009544291A patent/JP2010515275A/en active Pending
- 2007-12-28 EP EP07870039A patent/EP2097924A4/en not_active Withdrawn
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2013
- 2013-05-31 JP JP2013115456A patent/JP5686851B2/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104247004A (en) * | 2012-03-12 | 2014-12-24 | 阿尔塔科技半导体公司 | Method for manufacturing semiconductor wafers |
| CN103441095A (en) * | 2012-03-26 | 2013-12-11 | 瑞萨电子株式会社 | Method of manufacturing a semiconductor integrated circuit device |
| CN103441095B (en) * | 2012-03-26 | 2017-03-01 | 瑞萨电子株式会社 | The manufacture method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101088926B1 (en) | 2011-12-01 |
| JP2013175786A (en) | 2013-09-05 |
| JP2010515275A (en) | 2010-05-06 |
| WO2008083284A3 (en) | 2008-08-21 |
| JP5686851B2 (en) | 2015-03-18 |
| CN101663742B (en) | 2013-11-06 |
| EP2097924A2 (en) | 2009-09-09 |
| WO2008083284A2 (en) | 2008-07-10 |
| EP2097924A4 (en) | 2012-01-04 |
| KR20090094371A (en) | 2009-09-04 |
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