CN101663742B - Front-end processed wafer having through-chip connections - Google Patents
Front-end processed wafer having through-chip connections Download PDFInfo
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- CN101663742B CN101663742B CN2007800479122A CN200780047912A CN101663742B CN 101663742 B CN101663742 B CN 101663742B CN 2007800479122 A CN2007800479122 A CN 2007800479122A CN 200780047912 A CN200780047912 A CN 200780047912A CN 101663742 B CN101663742 B CN 101663742B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Abstract
A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metalization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.
Description
Technical field
The present invention relates to semiconductor, and relate in particular to the electrical connection for this device.
The cross reference of related application
The application requires the sequence number 60/882 of submission on December 29th, 2006 according to 35U.S.C.119 (e), the benefit of priority of 671 U.S. Provisional Application, and as the 11/422nd of submission on June 6th, 2006, the part of No. 551 U.S. Patent applications continues, its full content is bonded to herein by reference, as all setting forth in this article.
Background technology
Often wish that can run through chip in effective mode forms electrical connection so that be connected to another element.As a rule, with make of conventional method the same, this means the use of via hole and relate to connection, these connect with the periphery that is formed on chip on or periphery neighbouring being connected the device that relatively is formed on chip near.
Using a shortcoming that runs through the chip via hole on (being device supporting (device-bearing)) chip of processing fully is that the cost than the chip of the comparable blank wafer of a slice or section processes is more expensive significantly for the chip that is completed into.If the aligning at the via hole that is used for being electrically connected to produces mistake, may damage the device on chip or one or more metal layer, perhaps can not form the connection of hope.
In both cases, result may be all useless chip, needs discarded this chip.
Summary of the invention
We have invented a kind of method, so that the risk and cost relevant with the use that chip is electrically connected to of running through of using together of device supports chip minimizes.
Utilize a kind of being included in to form the execution mode that runs through the chip connection on blank wafer, advantageously eliminated the risk (because there is no device failure) of damaging device.In addition, if the obsolete problem of the wafer that provides also reduces costs impact, because also carrying out any device, wafer do not form or the back-end processing process.
Another kind of execution mode is included in to form on the wafer that forms device and runs through the chip connection, but does not also complete the back-end processing of adding metal interconnecting layer.Utilize this execution mode, after the first metal layer deposition but before the second metal level deposition, perhaps in general, before any " n " layer deposition that may deposit as the part of back-end processing, can in the situation that do not have pollution risk to form may be to processing very sensitive and needing the transistor in smooth extremely impeccable zone, thereby improve transistor output, via hole also obtains simultaneously the benefit of routing, because can form during back-end processing before the first metal layer deposition.
The advantage of explanation and feature are several in the many merits that can obtain from representational embodiment and feature in this article, and only provide in order to help to understand the present invention.Be to be understood that they are not considered to restriction of the present invention to limiting as claim, perhaps to the equivalents of claim.For example, some advantages are in opposition to each other, because they can not be present in single embodiment simultaneously.Similarly, some advantages are applicable to one aspect of the present invention, and are not suitable for other aspects.Therefore, should not to be considered at definite equivalent be conclusive in the summary of feature and advantage.Additional feature and advantage of the present invention will become apparent from accompanying drawing and in the accessory rights claim in the following description.
Description of drawings
Fig. 1 illustrates the part of the blank wafer that will be used for the explanation processing with the form of simplifying;
Fig. 2 illustrates the part of the wafer of the Fig. 1 after via hole forms with the form of simplifying;
Fig. 3 with the form of simplifying illustrate used simple via and ring-type via hole metal filled one of them after the via hole of Fig. 2;
Fig. 4 illustrates the part of the wafer of the Fig. 1 after completing front-end processing with the form of simplifying;
Fig. 5 illustrates the part of the front-end processed wafer that will be used for the explanation alternate process with the form of simplifying;
Fig. 6 illustrates the part of the front-end processed wafer after via hole forms with the form of simplifying;
Fig. 7 illustrates the via hole of the Fig. 6 after it has been filled with required conductive filling material with the form of simplifying;
Fig. 8 illustrates the structure of having added the Fig. 7 after metal-1 layer during back-end processing with the form simplified; With
Fig. 9 A to 9D illustrates the sequential steps in changing method.
Embodiment
the sequence number that is combined in by reference herein is 11/329, 481, 11/329, 506, 11/329, 539, 11/329, 540, 11/329, 556, 11/329, 557, 11/329, 558, 11/329, 574, 11/329, 575, 11/329, 576, 11/329, 873, 11/329, 874, 11/329, 875, 11/329, 883, 11/329, 885, 11/329, 886, 11/329, 887, 11/329, 952, 11/329, 953, 11/329, 955, 11/330, 011, 11/556, 747 and 11/422, 551 U.S. Patent application has been described and has been used for forming little at semiconductor wafer, dark via hole and be used for the various technology of the electric contact of semiconductor wafer.Via hole density and position that our technology can't obtain before considering, and can carry out on chip or wafer-scale.
If desirable is to set up to run through the chip electrical connection, relate to but make the risk minimization of processing wafer (being the device supporting wafer) fully, can use following methods.
In sum, the method directly be included in they should in case will be arranged in when completing front-end processing on device on wafer relevant position and form via hole in blank wafer, make hole-through conductive, then make device on wafer, thereby obtain device and run through the connection of chip between connecting by means of device fabrication process.
Particularly, process from blank wafer, for example silicon (Si), germanium (Ge), silicon-germanium (SiGe), GaAs (GaAs), indium phosphide (InP) or other wafers begin.
Fig. 1 illustrates the cross section of the part 100 of the blank wafer 102 that will be used for the explanation processing with the form of simplifying.Attention makes ratio distortion substantially in order to state simplification.
Next, if formed device, with the local corresponding wafer that forms via hole on the position of selection in advance, form via hole in wafer.Depend on specific execution mode, may comprise that use is for example above-mentioned in conjunction with applying for that one of described technology forms via hole.Alternatively, perhaps additionally, via hole can be processed to form by other that comprise for example laser drilling.
Fig. 2 illustrates the part 100 of the blank wafer 102 after via hole 202,204,206 forms with the form of simplifying.As shown in the figure, the via hole in this part comprises a simple via 202 and two ring-type via holes 204,206.Note, because use the ring-type via hole, so via hole does not have complete through-wafer, but stop in the short distance from the bottom surface 104 of wafer, come off to prevent newel.
In case via hole forms, by with can stand specific front-end treatment step and particularly, device in setting up related temperature and the conductor of stress come filled vias, make hole-through conductive.For example, process if will carry out CMOS, conductor can be any Au, Cu, Ni, W, Ti, perhaps can stand any other metal or alloy of temperature related in the CMOS processing.Optionally, can with before conductor filled with dielectric or insulator layer coating via hole, with prevent or guarantee conductor not can with the substrate short circuit.
Depend on specific execution mode, can comprise with vapor deposition process, electroplating processes or cause that via hole fills any other process filled vias.Alternatively, if using the ring-type via hole processes, the ring-type via hole can be filled suitably firm insulator, and newel can be by complete reservation (namely not removing), so that during front-end processing, newel can suitably be adulterated, thus itself serve as conductor and in this via hole at all without any need for metal.
Fig. 3 illustrates the via hole 202,204,206 of the Fig. 2 after filling simple via 202 with metal 208 and also using the space that one of metal 208 filling ring-type via holes 202 (its newel is removed) is arranged and stay because of removal with the form of simplifying.Notice that ring-type via hole 204,206 all has been filled with suitable insulator 210.But the newel 212 within the second ring-type via hole 206 is not removed, so that it can become conductor during front-end processing.
In the situation that used the ring-type via hole, can make now bottom surface 104 attenuates of wafer to expose the bottom of conductor metal 208 or newel 212.As will recognize, attenuate can not affect the via hole 206 in the place that newel 212 is retained, because insulator 210 holds it in suitable position.Certainly, if do not use the ring-type via hole, via hole can through-wafer or as the not through-wafer of expectation, remember, latter event may need attenuate, connect unless for example plan capacitive character.
In variation example that another substitutes, via hole is through-wafer fully not, and the bottom of wafer and the zone between via hole be maintained at enough sizes, so that it can become device area during front-end processing.
At this moment, complete the processing of current method, and wafer comprises a whole set of conductive via now.
After this, wafer can carry out the processing of normal front-end and back-end and cutting in a conventional manner.In case finish dealing with, last chip will have and be connected by the chip that runs through of carrying out the same type that one of above-mentioned associated methods can have, but be in lower risk and may have higher output.
Fig. 4 illustrates the part of the wafer of the Fig. 1 after completing front-end processing with the form of simplifying.Therefore, as shown in Figure 4, wafer becomes the wafer 400 of front-end processing and comprises now the doped region 402 that can have device.Advantageously, by means of its position with respect to device, via hole is electrically connected to the suitable part of device now.
Will form may be very sensitive and need smooth and extremely impeccable zone to processing, thus must be in the situation that do not have can use following methods during possibility occurs in the transistorized situation that the pollution risk during via hole forms forms.
In sum, the method directly comprises until front-end processing is completed just form device on wafer, but before one or more stages of back-end processing begin, forms via hole in front-end processed wafer, make hole-through conductive, then carry out one or more additional back-end processing stages.
Fig. 5 illustrates the part 500 of the wafer 502 of the front-end processing that will be used for the explanation alternate process with the form of simplifying.As shown in the figure, wafer 502 is included in established device in doped region 504.But at this moment, the back-end processing that increases metal interconnecting layer does not occur.
Next, be in wafer in the suitable position that is used for being connected to device or avoids device and form via hole.Depend on specific execution mode, this can comprise that use is for example above-mentioned in conjunction with applying for that one of described technology forms via hole.Alternatively, perhaps additionally, via hole can be processed to form by other that comprise for example laser drilling.
Fig. 6 illustrates the part 500 of the wafer 502 of the front-end processing after via hole 602,604,606 forms with the form of simplifying.As shown in the figure, the via hole in this part 500 comprises a simple via 602 (can or can not comprise dielectric or insulator coating arbitrarily) and two ring-type via holes 604,606.Note, because use the ring-type via hole, so via hole does not have complete through-wafer 502, but stop in the short distance from the bottom surface 506 of wafer 502, come off to prevent newel.
In case via hole forms, the filler filled vias that conducts electricity by use makes hole-through conductive.Depend on specific execution mode, can comprise with vapor deposition process, electroplating processes or cause that via hole fills any other process filled vias.Depend on specific execution mode, the via hole filler can be the material identical with the metal level that is used for forming, for example aluminium, tungsten or copper, can be the material different from being used to form metal level, for example, gold, silver or nickel, perhaps in the situation that be connected directly to device, can be to arrive with via hole and material that specific part that will attached device is complementary, for example, use and polysilicon that the grid material of field-effect transistor is complementary.
Fig. 7 illustrates with the via hole 602,604,606 after the via hole 602,604,606 of conductive filling material 608 blank maps 6 of wishing with the form of simplifying.Note, as shown in the figure, and before filling conductor, with suitable insulator 610 filling ring-type via holes, and each ring-type via hole 604,606 newel are removed.
In the situation of using the ring-type via hole, the bottom surface 506 of wafer 502 now can attenuate to expose conductive filling material 608.Alternatively, attenuate (if necessary) can occur in certain point subsequently.
Next, back-end processing can be from putting down the first rear end articulamentum (referred to herein as " metal-1 " layer).
Fig. 8 illustrates the structure of adding the Fig. 7 after metal-1 layers 800 during back-end processing with the form of simplifying.
Advantageously, by using the method, the conductive filling material 608 of given via hole can be connected directly to metal-1 layers 800, perhaps be not connected directly to as expected metal-1 layers 800, in the previous case, this can pass through plated metal-1 layers 800 and occurs simply, so that the part of metal-1 layers 800 directly contacts and cover the conductive filling material 608 of via hole, such as shown in Figure 8.
Alternatively, and advantageously, in the execution mode of an example, for example, if use electroplating processes, the formation of metal-1 layer can be used as via hole and fills a part of processing and exist.Adopt this method, to wafer pattern with the route that is formed for metal-1 layers 800 with make the via hole that will be filled expose.After this, inculating crystal layer (seed layer) is set to promote plating, then electroplates generation.So, the plating " cover layer " that forms in seed crystal (seed) location will form metal-1 layers 800 inherently.In addition, by patterning optionally, as required, specific via hole can " make progress " and run through metal layer, to be connected to one or more specific metal layers (for example, any in metal-N of metal-2, wherein " N " is outermost layer).
Can use further favourable alternate variation method, wherein must be connected to one or more to metal-N layer of metal-2.Except photoresist can be used for making overlay layer pattern, this changing method is similar to the formerly method that is right after.Operable a kind of photoresist is to be used for optionally covering " solid " photoresist of certain via hole, although so that all via holes all are formed in wafer, those via holes that will be connected to metal-1 layer are exposed to be used for the first round electroplate.As unrestriced example, suitable " solid " photo anti-corrosion agent material comprises available on the market from E.I.du Pont de Nemours ﹠amp; Co's
In film photoresist series commodity, perhaps effective other similar photoresists in suitable sheet thickness.Particularly, for
In film photoresist series commodity, can use photoresist
PlateMaster, EtchMaster and TentMaster series commodity.As
The advantage of photoresist product be that it can be used as that thin slice is placed from the teeth outwards and it has rigidity.Rigidity means that it can cover via hole and allow it to be patterned in the mode that subsequently time point is easily exposed again by it.Alternatively, not problem if unintentional via hole is filled for any reason, can use the photoresist of traditional non-solid or viscosity.Fig. 9 A illustrates the sequential steps in the diverse ways that carries out on the example part 900 of wafer 902 to 9D, comprise the use of solid photoresist, wafer 902 has had device thereon and has formed as described in this article via hole 906,908,910,912 in device area 904.
Use and patterning by solid photoresist 905, the formation that will be connected to the filling of via hole 906 of metal-1 layer and metal-1 layer with its conductive filler is by electroplating with conductive filling material 608 and (Fig. 9 A) occuring simultaneously, form metal-1 layer so that electroplate " cover layer ", solid photoresist 905 prevents that other via holes 908,910,912 are by conductive filling material 608 or photoresist filling itself simultaneously.
The planning that should be noted that certain level will be necessary, in order to guarantee not have partially metallised layer to surpass the via hole that will be connected to metal layer subsequently.If this can not be avoided, via hole will be filled within one or more metal layers before need to and changing its course in its metallization.Advantageously, large problem does not appear, because at first the metallized partly cause of making in layer changes its course.
Get back to the method; 905 layers of first " solid " photoresists are removed; and 905 layers of new " solid " photoresists are applied with protection metal-1 layer and via hole 910,912; via hole 910,912 will be connected to other layers and be patterned to expose via hole 908; via hole 908 will be filled when forming metal-2 layer; the applied electroplating of going forward side by side of inculating crystal layer is electroplated " cover layer " as metal-2 layer (Fig. 9 B) with filled vias and use.
Continuous metal layer is repeated the method (Fig. 9 C, Fig. 9 D) repeatedly, (namely run through metal-N) until all via holes all as being connected of needing, wherein can form with traditional back-end processing remaining metal layer.Significantly, although current back-end processing can comprise more than 10 to 12 layers (be N=10,11,12 or more than), advantageously, the number of the back end layers that no matter finally needs, the method can be identical.
Optionally, replace and then completing front-end processing etching and manufacturing via hole afterwards, can use any one in two kinds of alternative methods.In a replacement scheme, front-end processing can be carried out until the parts of device are added, then via hole is set up and is filled and can occur simultaneously with the foundation of parts, for example, can carry out etching and filling to via hole in grid conductor (for transistorized grid) deposition.In another replacement scheme, can as above complete front-end processing, but back-end processing will be only until metal-" X " layer just complete (wherein N be the integrated circuit (IC) chip completed layer last sum and 1＜X＜N), then via hole will etchedly reach that layer with filling.After this, back-end processing will continue, and, optionally, after completing some additional numbers of plies, before completing metal-N layer, can repeat this processing.
Also should note, method herein also allows back-end processing to stop at intermediate point to carry out device detection, the for example test of simple functions, if do not reach enough rate of finished productss so that any given tube core is inoperative or whole wafer, process and to be stopped, perhaps only the tube core by this centre test is continued to process.
Therefore should be appreciated that this specification (comprising accompanying drawing) only represents some illustrative embodiment.In order to help reader, above-mentioned explanation concentrates on the representative example of all possible embodiment, the example of instruction principle of the present invention.This specification does not attempt at large to enumerate all possible variation example.The embodiment that replaces may not occur for specific part of the present invention, the embodiment of the replacement of perhaps further not describing can obtain a part, is not considered to abandon the embodiment of those replacements.One of those skilled in the art will understand many embodiment that do not describe and combine same principle of the present invention and be equal to mutually.
Claims (15)
1. the method for a process semiconductor wafers, is characterized in that, comprising:
Form a plurality of via holes in semiconductor wafer;
Make at least some hole-through conductives in described a plurality of via hole;
Use and the identical processing that is used for making described a plurality of some hole-through conductives excessively, form metal layer on described a plurality of via holes; And
Carry out back-end processing on described semiconductor wafer after forming described metal layer,
After the execution of described back-end processing begins, but before described back-end processing complete, the device on described semiconductor wafer is carried out functional test.
2. the method for claim 1, it is characterized in that, describedly make at least some hole-through conductives in described a plurality of via hole be included in one of them that configures metal, metal alloy or polysilicon in via hole, and wherein carry out described configuration when forming metal layer.
3. method as claimed in claim 2, is characterized in that, described configuration comprises:
The solid photoresist is applied to described semiconductor wafer;
Make described solid photoresist patterning;
Inculating crystal layer is arranged at the zone of exposing by described patterning; And
Electroplate described inculating crystal layer with configuration plated material in described via hole and form described metal layer.
4. method as claimed in claim 3, is characterized in that, described applying solid photoresist is included in applying solid photoresist at least one via hole, makes described via hole can not be filled with plated material during the described inculating crystal layer of described plating.
5. the method for claim 1, is characterized in that, a plurality of via holes of described formation comprise formation ring-type via hole.
6. method as claimed in claim 5, is characterized in that, described formation ring-type via hole comprises by the described semiconductor wafer of partial penetration and forms described ring-type via hole.
7. method as claimed in claim 6, is characterized in that, further comprises with electric conducting material filling described ring-type via hole.
8. method as claimed in claim 7, is characterized in that, further comprise remove by described ring-type via hole around newel.
9. method as claimed in claim 6, is characterized in that, described at least some hole-through conductives in described a plurality of via hole comprised:
Fill described ring-type via hole with insulator; And
To by described ring-type via hole around newel doping so that described newel conduction.
10. method as claimed in claim 9, is characterized in that, carries out described doping in front-end processing, and described method further comprises the bottom of removing described semiconductor wafer.
11. the method for claim 1 is characterized in that, and is further comprising the steps:
Utilize photoresist to cover described via hole, by patterning exposed portions serve via hole, utilize electric conducting material to fill described part via hole, form metal layer, expose other via holes, utilize electric conducting material to fill described other via holes, and form metal layer.
12. the method for claim 1, it is characterized in that, described semiconductor wafer is blank wafer, and described method forms device after further being included in a plurality of via holes of described formation and described at least some hole-through conductives that make in described a plurality of via hole on described semiconductor wafer.
13. the method for claim 1, it is characterized in that, described semiconductor wafer is the device support semi-conductor wafers, and described method is carried out back-end processing after further being included in described at least some hole-through conductives that make in described a plurality of via hole on described device support semi-conductor wafers.
14. method as claimed in claim 13 is characterized in that, the described back-end processing of carrying out comprises via electroplating processes formation metal level.
15. method as claimed in claim 13 is characterized in that, further comprises stopping carrying out back-end processing, to carry out the intermediary device test.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88267106P | 2006-12-29 | 2006-12-29 | |
| US60/882,671 | 2006-12-29 | ||
| PCT/US2007/089061 WO2008083284A2 (en) | 2006-12-29 | 2007-12-28 | Front-end processed wafer having through-chip connections |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101663742A CN101663742A (en) | 2010-03-03 |
| CN101663742B true CN101663742B (en) | 2013-11-06 |
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| CN2007800479122A Active CN101663742B (en) | 2006-12-29 | 2007-12-28 | Front-end processed wafer having through-chip connections |
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|---|---|
| EP (1) | EP2097924A4 (en) |
| JP (2) | JP2010515275A (en) |
| KR (1) | KR101088926B1 (en) |
| CN (1) | CN101663742B (en) |
| WO (1) | WO2008083284A2 (en) |
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| DE102007044685B3 (en) * | 2007-09-19 | 2009-04-02 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Electronic system and method for manufacturing a three-dimensional electronic system |
| FR2987937B1 (en) * | 2012-03-12 | 2014-03-28 | Altatech Semiconductor | METHOD FOR MAKING SEMICONDUCTOR WAFERS |
| JP5925006B2 (en) * | 2012-03-26 | 2016-05-25 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor integrated circuit device |
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| CN1791975A (en) * | 2003-03-21 | 2006-06-21 | 西雷克斯微系统股份有限公司 | Electrical connections in substrates |
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| TWI427700B (en) * | 2004-08-20 | 2014-02-21 | Kamiyacho Ip Holdings | Method of fabricating semiconductor device with three-dimensional stacked structure |
| JP4524156B2 (en) * | 2004-08-30 | 2010-08-11 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| US7767493B2 (en) * | 2005-06-14 | 2010-08-03 | John Trezza | Post & penetration interconnection |
| US7838997B2 (en) * | 2005-06-14 | 2010-11-23 | John Trezza | Remote chip attachment |
| US7488680B2 (en) | 2005-08-30 | 2009-02-10 | International Business Machines Corporation | Conductive through via process for electronic device carriers |
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2007
- 2007-12-28 EP EP07870039A patent/EP2097924A4/en not_active Withdrawn
- 2007-12-28 JP JP2009544291A patent/JP2010515275A/en active Pending
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- 2007-12-28 KR KR1020097014823A patent/KR101088926B1/en active IP Right Grant
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Patent Citations (1)
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|---|---|---|---|---|
| CN1791975A (en) * | 2003-03-21 | 2006-06-21 | 西雷克斯微系统股份有限公司 | Electrical connections in substrates |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101088926B1 (en) | 2011-12-01 |
| EP2097924A4 (en) | 2012-01-04 |
| JP5686851B2 (en) | 2015-03-18 |
| WO2008083284A2 (en) | 2008-07-10 |
| CN101663742A (en) | 2010-03-03 |
| WO2008083284A3 (en) | 2008-08-21 |
| JP2013175786A (en) | 2013-09-05 |
| KR20090094371A (en) | 2009-09-04 |
| JP2010515275A (en) | 2010-05-06 |
| EP2097924A2 (en) | 2009-09-09 |
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