JP4524156B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP4524156B2
JP4524156B2 JP2004250420A JP2004250420A JP4524156B2 JP 4524156 B2 JP4524156 B2 JP 4524156B2 JP 2004250420 A JP2004250420 A JP 2004250420A JP 2004250420 A JP2004250420 A JP 2004250420A JP 4524156 B2 JP4524156 B2 JP 4524156B2
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semiconductor
semiconductor substrate
pattern
recess
semiconductor element
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JP2006066803A (en
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晶紀 白石
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Description

本発明は半導体装置及びその製造方法に関し、更に詳細には半導体素子が一面側に造り込まれた半導体基板の半導体素子形成面側には、前記半導体素子の電極端子から前記半導体基板と電気的に絶縁されて延出されたパターンと、前記半導体素子及びパターンを覆う絶縁層とが形成され、前記半導体基板の他面側には、前記パターンと電気的に接続された外部接続端子用のパッドが形成された半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically, on a semiconductor element forming surface side of a semiconductor substrate in which a semiconductor element is formed on one side, the electrode terminal of the semiconductor element is electrically connected to the semiconductor substrate. An insulated and extended pattern and an insulating layer covering the semiconductor element and the pattern are formed, and pads for external connection terminals electrically connected to the pattern are formed on the other surface side of the semiconductor substrate. The present invention relates to a formed semiconductor device and a manufacturing method thereof.

シリコン基板の一面側に半導体素子が造り込まれた半導体基板の他面側に、外部接続端子を装着するパッドを形成した半導体装置の製造方法は、例えば下記特許文献１に提案されている。
かかる半導体装置の製造方法を図５に示す。図５に示す製造方法では、図５（ａ）に示す様に、半導体素子が造り込まれた半導体基板としてのシリコン基板１００の一面側に、半導体素子の電極に接続されたパッド１０２，１０２を形成した後、エポキシ樹脂をシリコン基板１００の両面に塗布して第１樹脂層１０４，１０４を形成する［図５（ｂ）］。
更に、パッド１０２，１０２の各中心を狙い、レーザ加工によって第１樹脂層１０４，１０４、シリコン基板１００及びパッド１０２を貫通する貫通孔１０６，１０６を形成する［図５（ｃ）］。
この様にして形成した貫通孔１０６，１０６及び樹脂層１０４，１０４を覆うように形成した、図５（ｄ）に示す第２樹脂層１０８の両面に研磨を施して薄くし［図５（ｅ）］、第２樹脂層１０８に充填された貫通孔１０６，１０６の中心を狙ってレーザ加工を施す。かかるレーザ加工によって、貫通孔１０６の内壁面を形成する絶縁層が第２樹脂層１０８から成るスルーホール１１０が形成される［図５（ｆ）］。 A method for manufacturing a semiconductor device in which a pad for mounting an external connection terminal is formed on the other surface side of a semiconductor substrate in which a semiconductor element is formed on one surface side of a silicon substrate is proposed in, for example, Patent Document 1 below.
FIG. 5 shows a method for manufacturing such a semiconductor device. In the manufacturing method shown in FIG. 5, as shown in FIG. 5A, pads 102 and 102 connected to electrodes of a semiconductor element are formed on one surface side of a silicon substrate 100 as a semiconductor substrate on which a semiconductor element is built. After the formation, an epoxy resin is applied to both sides of the silicon substrate 100 to form the first resin layers 104 and 104 [FIG. 5B].
Further, through the centers of the pads 102 and 102, through holes 106 and 106 penetrating the first resin layers 104 and 104, the silicon substrate 100, and the pad 102 are formed by laser processing [FIG. 5C].
The both sides of the second resin layer 108 shown in FIG. 5 (d) formed so as to cover the through holes 106, 106 and the resin layers 104, 104 thus formed are polished and thinned [FIG. 5 (e). ]], Laser processing is performed aiming at the center of the through holes 106, 106 filled in the second resin layer 108. Through the laser processing, a through hole 110 in which the insulating layer forming the inner wall surface of the through hole 106 is formed of the second resin layer 108 is formed [FIG. 5F].

次いで、スルーホール１１０の内壁面を含む第２樹脂層１０８の全面に、無電解めっき等によって形成した薄膜金属層を給電層とする電解めっきによって、スルーホール１１０内を金属で充填してヴィア１１６を形成すると共に、スルーホール１１０の内壁面を除く第２樹脂層１０８の表面に金属層を形成した後、この金属層にフォトリソ等によりパターニングすることによって、はんだボール１１４等の外部接続端子を搭載するパッド１１２を形成できる。
特開２０００−２７７６８９号公報 Next, the inside of the through hole 110 is filled with metal by electrolytic plating using a thin film metal layer formed by electroless plating or the like over the entire surface of the second resin layer 108 including the inner wall surface of the through hole 110 as a power supply layer. And forming a metal layer on the surface of the second resin layer 108 excluding the inner wall surface of the through-hole 110, and then patterning the metal layer with photolithography or the like to mount external connection terminals such as solder balls 114 The pad 112 to be formed can be formed.
JP 2000-276789 A

図５に示す製造方法によれば、シリコン基板１００を貫通するスルーホール１１０内に金属が充填されたヴィア１１６が形成されるため、はんだバンプ１１４の外部接続端子をヴィア１１６の直上及び／又は直下に形成できる。
しかし、図５に示す製造方法では、シリコン基板１００を貫通する貫通孔１０６は、パッド１０２，１０２の各中心を狙って、第１樹脂層１０４，１０４、シリコン基板１００及びパッド１０２を貫通するレーザ加工によって形成する。
更に、貫通孔１０６の内壁面に絶縁層を形成したスルーホール１１０は、第２樹脂層１０８に充填された貫通孔１０６の中心を狙って、貫通孔１０６に充填された第２樹脂層１０８を貫通するレーザ加工によって形成する。
この様に、パッド１０２の中心や樹脂に充填された貫通孔１０６の中心を狙ったレーザ加工を行なうには、その位置決めに細心の注意を払うことを要し、生産性の向上を図ることは困難である。
しかも、スルーホール１１０内に電解めっきによって金属を充填する際には、スルーホール１１０の入口近傍に電荷が集中し易いため、スルーホール１１０内にボイドを形成することなく金属を充填することは困難である。このため、シリコン基板１００に形成された多数個のスルホール１１０の各々にボイドを形成することなく金属を確実に充填することは至難のことである。 According to the manufacturing method shown in FIG. 5, since the via 116 filled with metal is formed in the through hole 110 penetrating the silicon substrate 100, the external connection terminal of the solder bump 114 is directly above and / or directly below the via 116. Can be formed.
However, in the manufacturing method shown in FIG. 5, the through holes 106 that penetrate the silicon substrate 100 aim at the centers of the pads 102 and 102, and the laser penetrates the first resin layers 104 and 104, the silicon substrate 100 and the pad 102. Formed by processing.
Further, the through-hole 110 in which an insulating layer is formed on the inner wall surface of the through-hole 106 aims at the center of the through-hole 106 filled in the second resin layer 108 and the second resin layer 108 filled in the through-hole 106. It is formed by laser processing that penetrates.
As described above, in order to perform laser processing aiming at the center of the pad 102 or the center of the through hole 106 filled with the resin, it is necessary to pay close attention to the positioning and to improve the productivity. Have difficulty.
In addition, when the metal is filled in the through hole 110 by electrolytic plating, it is difficult to fill the metal without forming a void in the through hole 110 because charges are likely to concentrate near the entrance of the through hole 110. It is. For this reason, it is extremely difficult to reliably fill the metal without forming voids in each of the large number of through holes 110 formed in the silicon substrate 100.

また、半導体素子の電極端子に接続されたパッド１０２とヴィア１１６とは、スルーホール１１０の内壁面に形成された樹脂層によって電気的に絶縁されている。このため、パッド１０２とヴィア１１６とを電気的に接続するには、パッド１０２とヴィア１１６とを電気的に接続するパターンを、シリコン基板１００の半導体素子形成面側に形成することを要し、半導体素子の電極端子から外部接続端子までを電気的に接続する距離が長くなり、高周波用の半導体装置には不利となる。
更に、シリコン基板１００の半導体素子形成面側は、半導体素子からの熱が最も放熱される面であるが、ヴィア１１６の端面が露出し、且つ半導体素子の電極端子とヴィア１１６とを電気的に接続するパターンを形成等するため、放熱板等の放熱手段を設けて放熱性を向上することもできない。
そこで、本発明の課題は、半導体基板の一面側に形成された半導体素子の電極端子と、この半導体基板の他面側に形成された外部接続端子用のパッドとを電気的に接続する距離を可及的に短距離にできる半導体装置、及びこの半導体装置を容易に製造できる半導体装置の製造方法を提供することにある。 Further, the pad 102 and the via 116 connected to the electrode terminal of the semiconductor element are electrically insulated by a resin layer formed on the inner wall surface of the through hole 110. Therefore, in order to electrically connect the pad 102 and the via 116, it is necessary to form a pattern for electrically connecting the pad 102 and the via 116 on the semiconductor element forming surface side of the silicon substrate 100. The distance for electrically connecting the electrode terminal of the semiconductor element to the external connection terminal becomes long, which is disadvantageous for a high-frequency semiconductor device.
Further, the semiconductor element forming surface side of the silicon substrate 100 is a surface where the heat from the semiconductor element is most radiated, but the end face of the via 116 is exposed, and the electrode terminal of the semiconductor element and the via 116 are electrically connected. Since a pattern to be connected is formed, it is not possible to improve heat dissipation by providing heat dissipation means such as a heat sink.
Accordingly, an object of the present invention is to provide a distance for electrically connecting an electrode terminal of a semiconductor element formed on one side of the semiconductor substrate and a pad for an external connection terminal formed on the other side of the semiconductor substrate. It is an object of the present invention to provide a semiconductor device that can be made as short as possible, and a semiconductor device manufacturing method that can easily manufacture the semiconductor device.

本発明者は、前記課題を解決するには、半導体基板の一面側に形成された半導体素子の電極端子から延出されたパターンの半導体素子の外周縁近傍から半導体基板の他面側に垂下されたヴィアの端面に外部接続端子用のパッドを形成することによって、半導体素子の電極端子と外部接続端子用のパッドとを最短距離で電気的に接続できること、及びパターンの半導体素子近傍の半導体基板側面が底面に露出する凹部には、半導体基板を貫通するスルーホールに比較して、電解めっきによって金属を充填し易いことを知り、本発明に到達した。   In order to solve the above problems, the present inventor hangs down from the vicinity of the outer peripheral edge of the semiconductor element of the pattern extended from the electrode terminal of the semiconductor element formed on one surface side of the semiconductor substrate to the other surface side of the semiconductor substrate. By forming a pad for an external connection terminal on the end face of the via, the electrode terminal of the semiconductor element and the pad for the external connection terminal can be electrically connected in the shortest distance, and the side surface of the semiconductor substrate near the semiconductor element of the pattern It has been found that the recess exposed on the bottom surface is more easily filled with metal by electrolytic plating than the through-hole penetrating the semiconductor substrate.

すなわち、本発明は、半導体素子が一面側に造り込まれた半導体基板の半導体素子形成面側には、前記半導体素子の電極端子から前記半導体基板と電気的に絶縁されて延出されたパターンと、前記半導体素子及びパターンを覆う絶縁層とが形成され、前記半導体基板の他面側には、前記パターンと電気的に接続された外部接続端子用のパッドが形成された半導体装置であって、該半導体基板に形成された、前記半導体基板の他面側に開口され且つ底面に前記パターンの半導体素子近傍の半導体基板側面が露出する凹部は、その側壁面を覆う絶縁層と、前記パターンの半導体基板側面に一端部が接続された金属から成る柱状導体部とによって充填されていると共に、前記柱状導体部の他端部に接続された前記パッドが、前記凹部を覆うように形成されており、前記柱状導体部が金属ワイヤによって形成され、前記金属ワイヤと凹部内壁面との間に樹脂が充填されて絶縁層が形成されていることを特徴とする半導体装置にある。 That is, according to the present invention, on the semiconductor element forming surface side of the semiconductor substrate in which the semiconductor element is formed on one surface side, a pattern that is electrically insulated from the semiconductor substrate and extended from the electrode terminal of the semiconductor element; An insulating layer covering the semiconductor element and the pattern is formed, and a pad for an external connection terminal electrically connected to the pattern is formed on the other surface side of the semiconductor substrate, A recess formed in the semiconductor substrate and opened to the other surface of the semiconductor substrate and exposing a side surface of the semiconductor substrate in the vicinity of the semiconductor element of the pattern on the bottom surface, an insulating layer covering the side wall surface, and a semiconductor of the pattern The pad is filled with a columnar conductor made of metal having one end connected to the side of the substrate, and the pad connected to the other end of the columnar conductor is formed to cover the recess. Are, the columnar conductor part is formed by a metal wire, in the semiconductor device, wherein the resin is filled insulating layer is formed between the metal wire and recess walls.

また、本発明は、半導体素子が一面側に造り込まれた半導体基板の半導体素子形成面側には、前記半導体素子の電極端子から前記半導体基板と電気的に絶縁されて延出されたパターンと、前記半導体素子及びパターンを覆う絶縁層とが形成され、前記半導体基板の他面側には、前記パターンと電気的に接続された外部接続端子用のパッドが形成された半導体装置を製造する際に、該半導体基板の他面側に開口され且つ前記パターンの半導体素子近傍の半導体基板側面が底面に露出する凹部を、前記半導体基板に形成した後、前記凹部内に、前記パターンの半導体基板側面に一端部が接続されている金属から成る柱状導体部を金属ワイヤによって形成した後、前記金属ワイヤと凹部内壁面との間に樹脂を充填して絶縁層を形成し、次いで、前記柱状導体部の他端部に接続する外部接続用のパッドをめっきで形成することを特徴とする半導体装置の製造方法にある。 Further, according to the present invention, on the semiconductor element forming surface side of the semiconductor substrate in which the semiconductor element is formed on one surface side, a pattern that is electrically insulated from the semiconductor substrate and extended from the electrode terminal of the semiconductor element; And an insulating layer covering the semiconductor element and the pattern, and a semiconductor device having a pad for an external connection terminal electrically connected to the pattern formed on the other surface of the semiconductor substrate. in a recess other side is open to and semiconductor substrate side of the semiconductor element near the pattern of the semiconductor substrate is exposed to the bottom surface, after forming the semiconductor substrate, in the recess, the semiconductor substrate side of the pattern after the columnar conductor part made of a metal having one end connected to form a metal wire, a resin is filled to form an insulating layer between the metal wire and the recess inner wall surface, then the Lying in a method of manufacturing a semiconductor device according to claim forming by plating the pad for external connection for connecting the other end of the conductor-body.

かかる本発明において、柱状導体部を、金属ワイヤによって形成した後、前記金属ワイヤと凹部内壁面との間に樹脂を充填して絶縁層を形成し、次いで、めっきによってパッドを形成することによって、半導体基板の一面側に形成された半導体素子の電極端子と外部接続端子用のパッドとを最短距離で接続する柱状導体部を容易に形成できる。
また、半導体基板の一面側に、ＳｉＯ2又はＳｉＮから成る絶縁層を形成することにより、凹部の内壁面に絶縁層を容易に形成でき、半導体基板と柱状導体部とを確実に絶縁できる。
更に、半導体基板に形成する凹部を、反応性イオンエッチングによって形成することによって、レーザ加工による場合に比較して、開口径と底面径とが略同一径で且つアスペクト比の大きな凹部を容易に形成できる。 In such present invention, the pillar-shaped conductor portions, after forming the metal wires, the metal wires and by filling a resin between the recess wall to form an insulating layer, then by forming the pad by plating The columnar conductor portion for connecting the electrode terminal of the semiconductor element formed on the one surface side of the semiconductor substrate and the pad for the external connection terminal at the shortest distance can be easily formed.
Also, by forming an insulating layer made of SiO 2 or SiN on one surface side of the semiconductor substrate, the insulating layer can be easily formed on the inner wall surface of the recess, and the semiconductor substrate and the columnar conductor can be reliably insulated.
Furthermore, by forming the recesses to be formed in the semiconductor substrate by reactive ion etching, it is easy to form recesses with substantially the same opening diameter and bottom diameter and a large aspect ratio compared to the case of laser processing. it can.

本発明によれば、半導体基板の一面側に形成された半導体素子の外周縁近傍に、半導体基板の他面側に開口する凹部が、この凹部の底面に露出する半導体素子の電極端子から延出されたパターンの半導体基板側面に一端部が接続された金属から成る柱状導体部と、この凹部の側壁面を覆う絶縁層とによって充填され、且つ半導体基板の他面側には、凹部を覆うように形成された外部接続端子が装着されるパッドが柱状導体部の他端部に接続されている。
このため、半導体素子の電極端子とパッドとは、可及的に最短距離で電気的に接続することができ、高周波用の半導体装置に適している。
更に、半導体基板の半導体素子の形成面側は、絶縁層によって覆われているため、半導体基板の半導体素子形成面側に放熱板等の放熱手段を設けることができ、半導体装置の放熱性を向上できる。 According to the present invention, in the vicinity of the outer peripheral edge of the semiconductor element formed on one surface side of the semiconductor substrate, the recess opening on the other surface side of the semiconductor substrate extends from the electrode terminal of the semiconductor element exposed on the bottom surface of the recess. It is filled with a columnar conductor portion made of metal having one end connected to the side surface of the semiconductor substrate of the pattern and an insulating layer covering the side wall surface of the recess, and the other surface side of the semiconductor substrate covers the recess. A pad to which the external connection terminal formed on the pad is attached is connected to the other end of the columnar conductor.
For this reason, the electrode terminal and the pad of the semiconductor element can be electrically connected at the shortest possible distance, and are suitable for a high-frequency semiconductor device.
Furthermore, since the semiconductor element forming surface side of the semiconductor substrate is covered with an insulating layer, a heat radiating means such as a heat sink can be provided on the semiconductor element forming surface side of the semiconductor substrate, thereby improving the heat dissipation of the semiconductor device. I can .

本発明に係る半導体装置の製造方法についての一例を図１及び図２に示す。
先ず、図１（ａ）に示す様に、一面側に半導体素子１２，１２が造り込まれた半導体基板としてのシリコン基板１０を準備する。このシリコン基板１０には、半導体素子１２の各電極端子１２ａからアルミ製のパターン１４が、半導体素子１２の外周縁近傍まで延出されている。かかる半導体素子１２及びパターン１４は、ＳｉＯ2から成る絶縁層１６によって覆われていると共に、パターン１４とシリコン基板１０の一面側面との間もＳｉＯ2から成る絶縁層１６によって、半導体であるシリコン基板１０と確実に絶縁されている。
このシリコン基板１０の他面側にフォトレジスト１８を塗布し、凹部２０を開口するシリコン基板１０の他面側の部分２０ａを露出し［図１（ｂ）］、反応性イオンエッチングによって凹部２０を形成する［図１（ｃ）］。
かかる反応性イオンエッチングは、いわゆるＤ−ＲＩＥと称されているエッチング方法であって、例えばＳＦ6プラズマによるエッチングとＣ4Ｆ8プラズマによる凹部内周面の薄膜形成（デポジット）とを交互にシリコン基板１０の部分２０ａに施すことによって、シリコン基板１０に凹部２０を形成するものである。この反応性イオンエッチングを、シリコン基板１０の一面側に形成したＳｉＯ2から成る絶縁層１６に到達した時点で終了することによって、開口径と底面径とが略同一径で且つアスペクト比の大きな凹部を形成できる。
一方、レーザ加工によってシリコン基板１０に凹部を形成すると、開口径が底面径よりも大きいすり鉢形状の凹部が形成され易いため、形成する凹部の深さに限界が存在する。 An example of a method for manufacturing a semiconductor device according to the present invention is shown in FIGS.
First, as shown in FIG. 1A, a silicon substrate 10 is prepared as a semiconductor substrate in which semiconductor elements 12 and 12 are formed on one side. On the silicon substrate 10, an aluminum pattern 14 extends from each electrode terminal 12 a of the semiconductor element 12 to the vicinity of the outer peripheral edge of the semiconductor element 12. Such semiconductor element 12 and the pattern 14, as well covered with an insulating layer 16 made of SiO 2, the insulating layer 16 is also made of SiO 2 between the one face side of the pattern 14 and the silicon substrate 10, a silicon substrate is a semiconductor 10 is surely insulated.
Photoresist 18 is applied to the other surface side of the silicon substrate 10 to expose a portion 20a on the other surface side of the silicon substrate 10 that opens the recess 20 [FIG. 1B], and the recess 20 is formed by reactive ion etching. Form [FIG. 1 (c)].
Such reactive ion etching is a so-called D-RIE etching method in which, for example, etching with SF 6 plasma and formation of a thin film (deposit) on the inner peripheral surface of a recess with C 4 F 8 plasma are performed alternately in silicon. The recess 20 is formed in the silicon substrate 10 by being applied to the portion 20 a of the substrate 10. The reactive ion etching, a large recess and an aspect ratio by ending upon reaching the insulating layer 16 made of SiO 2 formed on one side, opening diameter and the bottom diameter substantially the same size of the silicon substrate 10 Can be formed.
On the other hand, when the concave portion is formed in the silicon substrate 10 by laser processing, a mortar-shaped concave portion having an opening diameter larger than the bottom surface diameter is easily formed, and thus there is a limit to the depth of the concave portion to be formed.

この様にして形成した凹部２０が開口するシリコン基板１０の他面側に塗布したフォトレジスト１８を除去した後［図１（ｄ）］、凹部２０の内壁面を含むシリコン基板１０の他面側の全面にＳｉＯ2から成る絶縁層２２を形成する［図１（ｅ）］。この絶縁層２２は、ＣＶＤ（化学気相蒸着）法によって形成できる。
更に、凹部２０の底部を形成する絶縁層１６、２２には、エキシマレーザ等のレーザ加工を施し、凹部２０の底面に開口する凹部２４を形成する［図１（ｆ）］。この凹部２４の開口径は、凹部２０の底面径よりも小径であって、凹部２０，２４から成る二段凹部２５の底面には、パターン１４のシリコン基板側面が露出する。
尚、絶縁層１６、２２の合計厚さは、シリコン基板１０よりも充分に薄く、レーザ加工によっても実質的に円筒状の凹部２４を形成できる。 After removing the photoresist 18 applied to the other surface side of the silicon substrate 10 where the recess 20 formed in this way is opened [FIG. 1D], the other surface side of the silicon substrate 10 including the inner wall surface of the recess 20 is formed. An insulating layer 22 made of SiO 2 is formed on the entire surface [FIG. 1 (e)]. The insulating layer 22 can be formed by a CVD (chemical vapor deposition) method.
Further, the insulating layers 16 and 22 that form the bottom of the recess 20 are subjected to laser processing such as excimer laser to form a recess 24 that opens to the bottom surface of the recess 20 [FIG. 1 (f)]. The opening diameter of the recessed portion 24 is smaller than the bottom surface diameter of the recessed portion 20, and the side surface of the silicon substrate of the pattern 14 is exposed on the bottom surface of the two-step recessed portion 25 including the recessed portions 20 and 24.
In addition, the total thickness of the insulating layers 16 and 22 is sufficiently thinner than the silicon substrate 10, and the substantially cylindrical recess 24 can be formed by laser processing.

次いで、二段凹部２５の内壁面を含むシリコン基板１０の他面側には、薄い金属層２６をスパッタリング又はＣＶＤ（化学気相蒸着）法によって形成する［図２（ｇ）］。この金属層２６は、Ｔｉ層上にＣｕ層が形成されている。
かかる金属層２６上に積層したドライフィルム２８に、二段凹部２５及びその外周縁近傍の金属層２６が露出するようにパターニングを施した後［図２（ｈ）］、金属層２６を給電層とする電解銅めっきによって、二段凹部２５を銅で充填してパターン１４のシリコン基板側面に一端部が接続された柱状導体部３０を形成すると共に、金属層２６の露出面に柱状導体部３０の他端部に接続されたパッド３２を形成する［図２（ｉ）］。この電解銅めっきとしては、例えば特開２００１−２９１９５４号公報に記載されている電解銅めっきを採用できる。
形成したパッド３２，３２・・には、その各々の厚さや表面の平坦性を均一化すべく、図２（ｊ）に示す様に、酸系研磨剤を用いた研磨［ＣＭＰ（Chemical Mechanical Polishing）］を施す。
かかる研磨を施したパッド３２，３２・・の各面には、電解ニッケルめっきで形成したＮｉ層上に、電解金めっきによって形成した薄膜状のＡｕ層から成る保護層３４を形成した後、ドライフィルム２８を剥離する［図２（ｋ）（ｌ）］。
その後、パッド３２，３２・・の一部を形成する部分を除く薄膜状の金属層２６をエッチングによって剥離し、図３（ｍ）に示す半導体装置を形成できる。 Next, a thin metal layer 26 is formed on the other surface side of the silicon substrate 10 including the inner wall surface of the two-step recess 25 by sputtering or CVD (chemical vapor deposition) [FIG. 2 (g)]. In the metal layer 26, a Cu layer is formed on the Ti layer.
After patterning the dry film 28 laminated on the metal layer 26 so that the two-step recess 25 and the metal layer 26 in the vicinity of the outer periphery thereof are exposed [FIG. 2 (h)], the metal layer 26 is applied to the power feeding layer. The columnar conductor portion 30 having one end connected to the side surface of the silicon substrate of the pattern 14 is formed by filling the two-step recessed portion 25 with copper by electrolytic copper plating, and the columnar conductor portion 30 is formed on the exposed surface of the metal layer 26. A pad 32 connected to the other end of the substrate is formed [FIG. 2 (i)]. As this electrolytic copper plating, for example, electrolytic copper plating described in JP-A-2001-291554 can be employed.
In order to make the thickness and surface flatness of each of the formed pads 32, 32,... Uniform as shown in FIG. 2 (j), polishing using an acid-based abrasive [CMP (Chemical Mechanical Polishing) ] Is applied.
On each surface of the polished pads 32, 32,..., A protective layer 34 made of a thin Au layer formed by electrolytic gold plating is formed on a Ni layer formed by electrolytic nickel plating, and then dried. The film 28 is peeled [FIG. 2 (k) (l)].
After that, the thin metal layer 26 excluding a portion where the pads 32, 32,... Are partially formed is removed by etching, so that the semiconductor device shown in FIG.

図３（ｍ）に示す半導体装置は、シリコン基板１０の一面側に形成された半導体素子１２，１２と、半導体素子１２の各電極端子１２ａから半導体素子１２の外周縁近傍まで延出されたパターン１４とは、ＳｉＯ2から成る絶縁層１６によって覆われている。
更に、パターン１４は、シリコン基板１０の他面側に形成されたパッド３２と柱状導体部３０によって電気的に接続され、パッド３２には、はんだボール３６等の外部接続端子を装着できる。
したがって、図２（ｍ）に示す半導体装置は、シリコン基板１０の他面側を実装基板に向けて実装されるため、半導体素子１２，１２が設けられたシリコン基板１０の一面側には、放熱フィン等の放熱手段を装着でき、その放熱性を向上できる。
また、シリコン基板１０の一面側に形成されたパターン１４とシリコン基板１０の他面側に形成されたパッド３２との電気的な接続は、シリコン基板１０の他面側に開口され、側壁面が絶縁層２２によって覆われ且つ底面にパターン１４の半導体素子近傍のシリコン基板側面が露出する二段凹部２５内に形成された銅から成る柱状導体部３０によってなされる。この柱状導体部３０は、二段凹部２５内にめっきによって金属を充填して形成したものであって、その一端部がパターン１４の半導体素子近傍のシリコン基板側面に接続されていると共に、その他端部にパッド３２が一体に形成されている。
かかるパッド３２は、絶縁層２２及び柱状導体部３０によって充填された二段凹部２５の開口部上に形成されており、パッド３２の表面にはんだボール３６等の外部接続端子を装着できる。
この様に、図２（ｍ）に示す半導体装置では、シリコン基板１０の一面側に形成された半導体素子１２の電極端子１２ａとシリコン基板１０の他面側に形成されたパッド３２との間を可及的に最短距離で電気的に接続することができる。このため、図２（ｍ）に示す半導体装置は高周波用の半導体装置に適している。 The semiconductor device shown in FIG. 3M includes semiconductor elements 12 and 12 formed on one surface side of the silicon substrate 10 and a pattern extending from each electrode terminal 12a of the semiconductor element 12 to the vicinity of the outer peripheral edge of the semiconductor element 12. 14 is covered with an insulating layer 16 made of SiO 2 .
Further, the pattern 14 is electrically connected to the pad 32 formed on the other surface side of the silicon substrate 10 by the columnar conductor portion 30, and an external connection terminal such as a solder ball 36 can be attached to the pad 32.
Therefore, since the semiconductor device shown in FIG. 2 (m) is mounted with the other surface side of the silicon substrate 10 facing the mounting substrate, heat radiation is not performed on one surface side of the silicon substrate 10 on which the semiconductor elements 12 and 12 are provided. A heat dissipating means such as a fin can be attached, and the heat dissipating property can be improved.
Further, the electrical connection between the pattern 14 formed on the one surface side of the silicon substrate 10 and the pad 32 formed on the other surface side of the silicon substrate 10 is opened on the other surface side of the silicon substrate 10, and the side wall surface is It is made by a columnar conductor portion 30 made of copper formed in a two-step recess 25 covered with an insulating layer 22 and exposed on the bottom surface of a silicon substrate side surface in the vicinity of the semiconductor element of the pattern 14. The columnar conductor 30 is formed by filling a metal in the two-step recess 25 by plating, and one end thereof is connected to the side surface of the silicon substrate near the semiconductor element of the pattern 14 and the other end. A pad 32 is formed integrally with the part.
The pad 32 is formed on the opening of the two-step recess 25 filled with the insulating layer 22 and the columnar conductor portion 30, and an external connection terminal such as a solder ball 36 can be mounted on the surface of the pad 32.
As described above, in the semiconductor device shown in FIG. 2M, the gap between the electrode terminal 12a of the semiconductor element 12 formed on the one surface side of the silicon substrate 10 and the pad 32 formed on the other surface side of the silicon substrate 10 is obtained. Electrical connection can be made with the shortest possible distance. For this reason, the semiconductor device shown in FIG. 2M is suitable for a high-frequency semiconductor device.

図１及び図２に示す半導体装置の製造方法では、レーザ加工を用いたり、凹部を電解めっきによって充填するため、その工程がやや複雑である。このため、図３及び図４に示す半導体装置の製造方法によれば、レーザ加工や凹部を電解めっきによって充填することをなく半導体装置を製造できる。この図３及び図４においては、図１及び図２に示す部材と同一部材は同一番号を付した。
先ず、図３（ａ）に示す様に、一面側に半導体素子１２，１２が造り込まれた半導体基板としてのシリコン基板１０を準備する。このシリコン基板１０には、半導体素子１２の各電極端子１２ａからアルミ製のパターン１４が、半導体素子１２の外周縁近傍まで延出されている。かかるパターン１４の半導体素子１２の外周縁から延出された延出部分の一部がシリコン基板１０の一面側に当接している当接部１４ａである。
この半導体素子１２及びパターン１４は、ＳｉＯ2から成る絶縁層１６によって覆われていると共に、パターン１４の当接部１４ａを除く部分とシリコン基板１０の一面側面との間もＳｉＯ2から成る絶縁層１６によって、半導体であるシリコン基板１０と絶縁されている。
このシリコン基板１０の他面側にフォトレジスト１８を塗布し、パターン１４の当接部１４ａに対応する部分２０ａのシリコン基板１０の他面側を露出し［図３（ｂ）］、反応性イオンエッチングによって凹部２０を形成する［図３（ｃ）］。この凹部２０の底面には、パターン１４の当接部１４ａが露出する。
尚、この反応性イオンエッチングは、図１（ｃ）で凹部２０を形成した反応性イオンエッチングと同一のものである。 In the method of manufacturing the semiconductor device shown in FIGS. 1 and 2, the process is somewhat complicated because laser processing is used or the recesses are filled by electrolytic plating. For this reason, according to the manufacturing method of the semiconductor device shown in FIG.3 and FIG.4, a semiconductor device can be manufactured, without filling a laser processing or a recessed part with electrolytic plating. In FIG. 3 and FIG. 4, the same members as those shown in FIG. 1 and FIG.
First, as shown in FIG. 3A, a silicon substrate 10 is prepared as a semiconductor substrate in which semiconductor elements 12 and 12 are formed on one side. On the silicon substrate 10, an aluminum pattern 14 extends from each electrode terminal 12 a of the semiconductor element 12 to the vicinity of the outer peripheral edge of the semiconductor element 12. A part of the extended portion of the pattern 14 extending from the outer peripheral edge of the semiconductor element 12 is a contact portion 14 a that is in contact with one surface side of the silicon substrate 10.
The semiconductor element 12 and the pattern 14, as well covered with an insulating layer 16 made of SiO 2, an insulating layer is also made of SiO 2 between the one face side portion and the silicon substrate 10 except for the contact portion 14a of the pattern 14 16 is insulated from the silicon substrate 10 which is a semiconductor.
Photoresist 18 is applied to the other surface side of the silicon substrate 10 to expose the other surface side of the silicon substrate 10 in the portion 20a corresponding to the contact portion 14a of the pattern 14 [FIG. A recess 20 is formed by etching [FIG. 3 (c)]. The contact portion 14 a of the pattern 14 is exposed on the bottom surface of the recess 20.
This reactive ion etching is the same as the reactive ion etching in which the recess 20 is formed in FIG.

凹部２０の底面に露出するパターン１４の当接部１４ａの露出面には、金属ワイヤによって柱状導体部３８を立設する［図３（ｄ）］。この柱状導体部３８は、シリコン基板１０の他面側から先端部が突出する高さとする。かかる金属ワイヤから成る柱状導体部３８は、例えば米国特許第５４７６２１１号明細書に記載されている様に、ワイヤーボンディング装置を用いて形成できる。
この様に、柱状導体部３８が立設されている凹部２０内には、ポッティングによって樹脂を充填し、キュア等を施して樹脂層４０を形成する［図３（ｅ）］。この柱状導体部３８及び樹脂層４０によって凹部２０を充填できる。
更に、シリコン基板１０の他面側には、柱状導体部３８の先端部が突出しているため、シリコン基板１０の他面側に研磨を施して平坦面に形成した後［図３（ｆ）］、研磨面にソルダ−レジストを塗布して絶縁層４２を形成する［図３（ｇ）］。 A columnar conductor 38 is erected on the exposed surface of the contact portion 14a of the pattern 14 exposed on the bottom surface of the recess 20 by a metal wire [FIG. 3 (d)]. The columnar conductor 38 has a height at which the tip protrudes from the other surface side of the silicon substrate 10. The columnar conductor portion 38 made of such a metal wire can be formed using a wire bonding apparatus as described in, for example, US Pat. No. 5,472,211.
In this manner, the recess 20 in which the columnar conductor portions 38 are erected is filled with resin by potting and cured to form the resin layer 40 [FIG. 3 (e)]. The recess 20 can be filled with the columnar conductor 38 and the resin layer 40.
Furthermore, since the tip of the columnar conductor 38 protrudes on the other surface side of the silicon substrate 10, the other surface side of the silicon substrate 10 is polished to form a flat surface [FIG. 3 (f)]. Then, a solder resist is applied to the polished surface to form an insulating layer 42 [FIG. 3 (g)].

この絶縁層４２にパターニングを施し、凹部２０の外周縁及びその近傍の絶縁層４２を残し、残部を除去する［図４（ｈ）］。
次いで、シリコン基板１０の他面側の全面に、薄い金属層２６をスパッタリング又はＣＶＤ（化学気相蒸着）法によって形成する［図４（ｉ）］。この金属層２６は、Ｔｉ層上にＣｕ層が形成されている。
かかる金属層２６上に積層したドライフィルム２８に、凹部２０の外周縁及びその近傍の絶縁層４２及び凹部２０の開口部に対応する金属層２６が露出するするようにパターニングを施した後［図４（ｊ）］、金属層２６を給電層とする電解めっきによって、金属層２６が露出する露出面に金属層４４を形成する。この金属層４４は、Ｎｉ層上にＡｕ層が形成されている。
その後、ドライフィルム２８を除去した後［図４（ｌ）］、金属層４４をマスクとして金属層２６の露出している部分をエッチングで除去し、柱状導体部３８の端部に接続されたパッド４６を形成できる［図４（ｍ）］。 The insulating layer 42 is patterned to leave the outer peripheral edge of the recess 20 and the insulating layer 42 in the vicinity thereof, and the remaining portion is removed [FIG. 4 (h)].
Next, a thin metal layer 26 is formed on the entire other surface of the silicon substrate 10 by sputtering or CVD (chemical vapor deposition) [FIG. 4 (i)]. In the metal layer 26, a Cu layer is formed on the Ti layer.
The dry film 28 laminated on the metal layer 26 is patterned so that the outer peripheral edge of the recess 20 and the insulating layer 42 in the vicinity thereof and the metal layer 26 corresponding to the opening of the recess 20 are exposed [FIG. 4 (j)], the metal layer 44 is formed on the exposed surface where the metal layer 26 is exposed by electrolytic plating using the metal layer 26 as a power feeding layer. In the metal layer 44, an Au layer is formed on the Ni layer.
Thereafter, after the dry film 28 is removed [FIG. 4 (l)], the exposed portion of the metal layer 26 is removed by etching using the metal layer 44 as a mask, and the pad connected to the end of the columnar conductor portion 38 is removed. 46 can be formed [FIG. 4 (m)].

図４（ｍ）に示す半導体装置においても、図２（ｍ）に示す半導体装置と同様に、半導体素子１２，１２が設けられたシリコン基板１０の一面側には、放熱フィン等の放熱手段を装着でき、その放熱性を向上できる。
また、図４（ｍ）に示す半導体装置においても、シリコン基板１０の一面側に形成された半導体素子１２の電極端子１２ａとシリコン基板１０の他面側に形成されたパッド４６との間を可及的に最短距離で電気的に接続することができる。
以上、説明してきた半導体基板としては、シリコン基板１０を用いたが、ＧａＡｓ基板を用いることができる。
更に、絶縁層１６，２２としては、ＳｉＯ2から成る絶縁層を形成していたが、ＳｉＮから成る絶縁層を形成してもよい。
尚、図２（ｍ）及び図４（ｍ）に示す半導体装置は、シリコンウェーハに複数個の半導体装置を形成し、個変に切り分けて得てもよい。 Also in the semiconductor device shown in FIG. 4 (m), similarly to the semiconductor device shown in FIG. 2 (m), a heat radiating means such as a heat radiating fin is provided on one surface side of the silicon substrate 10 provided with the semiconductor elements 12 and 12. It can be installed and its heat dissipation can be improved.
Also, in the semiconductor device shown in FIG. 4 (m), the gap between the electrode terminal 12a of the semiconductor element 12 formed on the one surface side of the silicon substrate 10 and the pad 46 formed on the other surface side of the silicon substrate 10 is acceptable. Electrical connection can be made at the shortest distance.
As described above, the silicon substrate 10 is used as the semiconductor substrate described above, but a GaAs substrate can be used.
Further, as the insulating layers 16 and 22, an insulating layer made of SiO 2 is formed, but an insulating layer made of SiN may be formed.
Note that the semiconductor devices shown in FIGS. 2 (m) and 4 (m) may be obtained by forming a plurality of semiconductor devices on a silicon wafer and dividing them into individual pieces.

本発明に係る半導体装置の製造方法の一例について、その前半部分を説明する部分工程図である。It is a partial process figure explaining the first half part about an example of a manufacturing method of a semiconductor device concerning the present invention. 本発明に係る半導体装置の製造方法の一例について、その後半部分を説明する部分工程図である。It is a partial process figure explaining the latter half part about an example of the manufacturing method of the semiconductor device concerning the present invention. 本発明に係る半導体装置の製造方法の他の例について、その前半部分を説明する部分工程図である。It is a partial process figure explaining the first half part about other examples of the manufacturing method of the semiconductor device concerning the present invention. 本発明に係る半導体装置の製造方法の他の例について、その後半部分を説明する部分工程図である。It is a partial process figure explaining the latter half part about other examples of the manufacturing method of the semiconductor device concerning the present invention. 従来の半導体装置の製造方法を説明する工程図である。It is process drawing explaining the manufacturing method of the conventional semiconductor device.

符号の説明Explanation of symbols

１０ シリコン基板
１２ａ 電極端子
１２ 半導体素子
１４ パターン
１４ａ 当接部
１６，２２，４２ 絶縁層
２０，２４ 凹部
２５ 二段凹部
２６ 金属層
３０，３８ 柱状導体部
３２，４６ パッド
４０ 樹脂層 DESCRIPTION OF SYMBOLS 10 Silicon substrate 12a Electrode terminal 12 Semiconductor element 14 Pattern 14a Abutting part 16,22,42 Insulating layer 20,24 Recessed part 25 Two-step recessed part 26 Metal layer 30,38 Columnar conductor part 32,46 Pad 40 Resin layer

Claims (6)

半導体素子が一面側に造り込まれた半導体基板の半導体素子形成面側には、前記半導体素子の電極端子から前記半導体基板と電気的に絶縁されて延出されたパターンと、前記半導体素子及びパターンを覆う絶縁層とが形成され、
前記半導体基板の他面側には、前記パターンと電気的に接続された外部接続端子用のパッドが形成された半導体装置であって、
該半導体基板に形成された、前記半導体基板の他面側に開口され且つ底面に前記パターンの半導体素子近傍の半導体基板側面が露出する凹部は、その側壁面を覆う絶縁層と、前記パターンの半導体基板側面に一端部が接続された金属から成る柱状導体部とによって充填されていると共に、
前記柱状導体部の他端部に接続された前記パッドが、前記凹部を覆うように形成されており、
前記柱状導体部が金属ワイヤによって形成され、
前記金属ワイヤと凹部内壁面との間に樹脂が充填されて絶縁層が形成されていることを特徴とする半導体装置。 On the semiconductor element forming surface side of the semiconductor substrate in which the semiconductor element is formed on one side, a pattern that is electrically insulated from the semiconductor substrate and extended from the electrode terminal of the semiconductor element, and the semiconductor element and the pattern And an insulating layer covering the
On the other surface side of the semiconductor substrate is a semiconductor device in which pads for external connection terminals electrically connected to the pattern are formed,
A recess formed in the semiconductor substrate and opened to the other surface of the semiconductor substrate and exposing a side surface of the semiconductor substrate in the vicinity of the semiconductor element of the pattern on the bottom surface, an insulating layer covering the side wall surface, and a semiconductor of the pattern And filled with a columnar conductor made of metal having one end connected to the side surface of the substrate,
The pad connected to the other end of the columnar conductor is formed to cover the recess ,
The columnar conductor is formed of a metal wire;
Wherein a resin is filled insulating layer is formed between the metal wire and recess walls. 前記凹部が、反応性イオンエッチング加工によって形成された凹部である請求項１記載の半導体装置。 The semiconductor device according to claim 1 , wherein the recess is a recess formed by reactive ion etching. 前記半導体基板の半導体素子形成面側に形成された絶縁層が、ＳｉＯ2又はＳｉＮから成る絶縁層である請求項１又は２記載の半導体装置。 The insulating layer formed on the semiconductor element formation surface side of the semiconductor substrate, the semiconductor device according to claim 1 or 2, wherein an insulating layer made of SiO 2 or SiN. 半導体素子が一面側に造り込まれた半導体基板の半導体素子形成面側には、前記半導体素子の電極端子から前記半導体基板と電気的に絶縁されて延出されたパターンと、前記半導体素子及びパターンを覆う絶縁層とが形成され、前記半導体基板の他面側には、前記パターンと電気的に接続された外部接続端子用のパッドが形成された半導体装置を製造する際に、
該半導体基板の他面側に開口され且つ前記パターンの半導体素子近傍の半導体基板側面が底面に露出する凹部を、前記半導体基板に形成した後、
前記凹部内に、前記パターンの半導体基板側面に一端部が接続されている金属から成る柱状導体部を金属ワイヤによって形成した後、前記金属ワイヤと凹部内壁面との間に樹脂を充填して絶縁層を形成し、
次いで、前記柱状導体部の他端部に接続する外部接続用のパッドをめっきで形成することを特徴とする半導体装置の製造方法。 On the semiconductor element forming surface side of the semiconductor substrate in which the semiconductor element is formed on one side, a pattern that is electrically insulated from the semiconductor substrate and extended from the electrode terminal of the semiconductor element, and the semiconductor element and the pattern When manufacturing a semiconductor device in which a pad for an external connection terminal electrically connected to the pattern is formed on the other surface side of the semiconductor substrate is formed on the other surface side of the semiconductor substrate.
After forming in the semiconductor substrate a recess that is open on the other surface side of the semiconductor substrate and the side surface of the semiconductor substrate near the semiconductor element of the pattern is exposed to the bottom surface,
In the recess, the insulation by filling a resin between the after the columnar conductor portion made of a metal having one end portion to the semiconductor substrate side of the pattern is connected to form a metal wire, the metal wire and the recess inner wall Forming a layer,
Then, a method of manufacturing a semiconductor device and forming a pad for external connection connected to the other end of the columnar guide body by plating. 前記半導体基板に形成する凹部を、反応性イオンエッチングによって形成する請求項４記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 4 , wherein the recess formed in the semiconductor substrate is formed by reactive ion etching. 前記半導体基板の半導体素子形成面側に形成された絶縁層として、ＳｉＯ2又はＳｉＮから成る絶縁層を形成する請求項４又は５記載の半導体装置の製造方法。 Wherein the insulating layer formed on the semiconductor element formation surface side of the semiconductor substrate, The method according to claim 4 or 5, wherein an insulating layer made of SiO 2 or SiN.
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