WO2008083284A3 - Front-end processed wafer having through-chip connections - Google Patents

Front-end processed wafer having through-chip connections Download PDF

Info

Publication number
WO2008083284A3
WO2008083284A3 PCT/US2007/089061 US2007089061W WO2008083284A3 WO 2008083284 A3 WO2008083284 A3 WO 2008083284A3 US 2007089061 W US2007089061 W US 2007089061W WO 2008083284 A3 WO2008083284 A3 WO 2008083284A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor wafer
electrically conductive
bearing semiconductor
vias
processed wafer
Prior art date
Application number
PCT/US2007/089061
Other languages
French (fr)
Other versions
WO2008083284A2 (en
Inventor
John Trezza
Original Assignee
Cubic Wafer Inc
John Trezza
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cubic Wafer Inc, John Trezza filed Critical Cubic Wafer Inc
Priority to CN2007800479122A priority Critical patent/CN101663742B/en
Priority to EP07870039A priority patent/EP2097924A4/en
Priority to KR1020097014823A priority patent/KR101088926B1/en
Priority to JP2009544291A priority patent/JP2010515275A/en
Publication of WO2008083284A2 publication Critical patent/WO2008083284A2/en
Publication of WO2008083284A3 publication Critical patent/WO2008083284A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and performing back-end processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a metalization layer. An alternative method involves forming vias in a device-bearing semiconductor wafer, making at least some of the vias in the device-bearing semiconductor wafer electrically conductive, and processing the device-bearing semiconductor wafer so as to create electrical connections between an electrically conductive via and a conductive semiconductor layer.
PCT/US2007/089061 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections WO2008083284A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2007800479122A CN101663742B (en) 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections
EP07870039A EP2097924A4 (en) 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections
KR1020097014823A KR101088926B1 (en) 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections
JP2009544291A JP2010515275A (en) 2006-12-29 2007-12-28 Front-end processed wafer with through-chip connection

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88267106P 2006-12-29 2006-12-29
US60/882,671 2006-12-29

Publications (2)

Publication Number Publication Date
WO2008083284A2 WO2008083284A2 (en) 2008-07-10
WO2008083284A3 true WO2008083284A3 (en) 2008-08-21

Family

ID=39589215

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/089061 WO2008083284A2 (en) 2006-12-29 2007-12-28 Front-end processed wafer having through-chip connections

Country Status (5)

Country Link
EP (1) EP2097924A4 (en)
JP (2) JP2010515275A (en)
KR (1) KR101088926B1 (en)
CN (1) CN101663742B (en)
WO (1) WO2008083284A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007044685B3 (en) * 2007-09-19 2009-04-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Electronic system and method for manufacturing a three-dimensional electronic system
FR2987937B1 (en) * 2012-03-12 2014-03-28 Altatech Semiconductor METHOD FOR MAKING SEMICONDUCTOR WAFERS
JP5925006B2 (en) * 2012-03-26 2016-05-25 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor integrated circuit device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060035563A1 (en) * 2004-07-02 2006-02-16 Strasbaugh Method, apparatus and system for use in processing wafers
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03218653A (en) * 1989-11-13 1991-09-26 Mitsubishi Electric Corp Semiconductor device provided with air bridge metal wiring and manufacture thereof
JP3979791B2 (en) 2000-03-08 2007-09-19 株式会社ルネサステクノロジ Semiconductor device and manufacturing method thereof
EP2560199B1 (en) * 2002-04-05 2016-08-03 STMicroelectronics S.r.l. Process for manufacturing a through insulated interconnection in a body of semiconductor material
JP4285629B2 (en) * 2002-04-25 2009-06-24 富士通株式会社 Method for manufacturing interposer substrate mounting integrated circuit
JP3748844B2 (en) * 2002-09-25 2006-02-22 Ｎｅｃエレクトロニクス株式会社 Semiconductor integrated circuit and test method thereof
JP4322508B2 (en) * 2003-01-15 2009-09-02 新光電気工業株式会社 Manufacturing method of semiconductor device
JP4145301B2 (en) * 2003-01-15 2008-09-03 富士通株式会社 Semiconductor device and three-dimensional mounting semiconductor device
SE526366C3 (en) * 2003-03-21 2005-10-26 Silex Microsystems Ab Electrical connections in substrate
JP3891299B2 (en) * 2003-05-06 2007-03-14 セイコーエプソン株式会社 Semiconductor device manufacturing method, semiconductor device, semiconductor device, electronic device
JP4340517B2 (en) * 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
TWI228295B (en) * 2003-11-10 2005-02-21 Shih-Hsien Tseng IC structure and a manufacturing method
JP4114660B2 (en) * 2003-12-16 2008-07-09 セイコーエプソン株式会社 Semiconductor device manufacturing method, semiconductor device, circuit board, electronic device
KR100569590B1 (en) * 2003-12-30 2006-04-10 매그나칩 반도체 유한회사 Radio frequency semiconductor device and method of manufacturing the same
WO2005086216A1 (en) * 2004-03-09 2005-09-15 Japan Science And Technology Agency Semiconductor element and semiconductor element manufacturing method
JP3875240B2 (en) 2004-03-31 2007-01-31 株式会社東芝 Manufacturing method of electronic parts
JP4492196B2 (en) * 2004-04-16 2010-06-30 セイコーエプソン株式会社 Semiconductor device manufacturing method, circuit board, and electronic apparatus
JP2006049557A (en) * 2004-08-04 2006-02-16 Seiko Epson Corp Semiconductor device
US7906363B2 (en) * 2004-08-20 2011-03-15 Zycube Co., Ltd. Method of fabricating semiconductor device having three-dimensional stacked structure
JP4524156B2 (en) * 2004-08-30 2010-08-11 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US7767493B2 (en) * 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
US7488680B2 (en) 2005-08-30 2009-02-10 International Business Machines Corporation Conductive through via process for electronic device carriers

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060035563A1 (en) * 2004-07-02 2006-02-16 Strasbaugh Method, apparatus and system for use in processing wafers
US20060281363A1 (en) * 2005-06-14 2006-12-14 John Trezza Remote chip attachment

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP2097924A4 *

Also Published As

Publication number Publication date
CN101663742A (en) 2010-03-03
JP2010515275A (en) 2010-05-06
WO2008083284A2 (en) 2008-07-10
JP5686851B2 (en) 2015-03-18
EP2097924A2 (en) 2009-09-09
CN101663742B (en) 2013-11-06
KR101088926B1 (en) 2011-12-01
EP2097924A4 (en) 2012-01-04
KR20090094371A (en) 2009-09-04
JP2013175786A (en) 2013-09-05

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