CN108122889A - TSV pinboards based on transverse diode - Google Patents
TSV pinboards based on transverse diode Download PDFInfo
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- CN108122889A CN108122889A CN201711351292.3A CN201711351292A CN108122889A CN 108122889 A CN108122889 A CN 108122889A CN 201711351292 A CN201711351292 A CN 201711351292A CN 108122889 A CN108122889 A CN 108122889A
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- 239000000758 substrate Substances 0.000 claims abstract description 83
- 239000010949 copper Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 23
- 229910052802 copper Inorganic materials 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 239000012535 impurity Substances 0.000 claims description 14
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 229910052681 coesite Inorganic materials 0.000 claims description 10
- 229910052906 cristobalite Inorganic materials 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052682 stishovite Inorganic materials 0.000 claims description 10
- 229910052905 tridymite Inorganic materials 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 74
- 230000000694 effects Effects 0.000 abstract description 11
- 238000005538 encapsulation Methods 0.000 abstract description 4
- 230000008569 process Effects 0.000 description 30
- 238000001259 photo etching Methods 0.000 description 28
- 239000010410 layer Substances 0.000 description 23
- 238000005516 engineering process Methods 0.000 description 17
- 238000000151 deposition Methods 0.000 description 10
- 238000004026 adhesive bonding Methods 0.000 description 9
- 238000011161 development Methods 0.000 description 9
- 230000018109 developmental process Effects 0.000 description 9
- 238000002360 preparation method Methods 0.000 description 9
- 239000000126 substance Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 7
- 238000011065 in-situ storage Methods 0.000 description 6
- 238000011049 filling Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000000708 deep reactive-ion etching Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000011946 reduction process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000012190 activator Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a kind of TSV pinboards based on transverse diode, including：Si substrates (101)；At least two TSV areas (102) are arranged in the Si substrates (101)；At least three isolated areas (103) are arranged in the Si substrates (101) and between TSV areas (102) described in each two；Transverse diode (104) is arranged in the Si substrates (101) and between the two neighboring isolated area (103)；Interconnection line (105) is connected in series the first end face and the transverse diode (104) of the TSV areas (102).TSV pinboards provided by the invention are used as ESD protection device by processing diode on TSV pinboards, solve the problems, such as that the IC system grade encapsulation antistatic effect based on TSV techniques is weak, enhance the antistatic effect of IC system grade encapsulation.
Description
Technical field
The invention belongs to semiconductor integrated circuit technology field, more particularly to a kind of TSV switchings based on transverse diode
Plate.
Background technology
One of target of semiconductor integrated circuit be with relatively low cost manufacture miniaturization, multi-functional, large capacity and/or
The semiconductor product of high reliability.Semiconductor packaging plays an important role in target as realization.With half
Integrated level and the memory capacity increase of conductor device have developed to stack three-dimensional (3D) encapsulation of one single chip.For example,
Employed be formed with the through hole for penetrating substrate and in through-holes formed electrode silicon hole (Through-Silicon Via,
Abbreviation TSV) contact technique as can replace existing Wire Bonding Technology a kind of 3D encapsulating structures.
TSV technology is a kind of new technical solution that stacked chips realize interconnection in 3D integrated circuits.Due to TSV skills
Art can make that the density that chip stacks in three-dimensional is maximum, the interconnection line between chip is most short, appearance and size is minimum, Ke Yiyou
This 3D chip laminates are realized on effect ground, produce that structure is more complicated, performance is more powerful, more cost-efficient chip, are become
Most noticeable a kind of technology in Electronic Encapsulating Technology at present.
Pinboard typically refers to the functional layer of the interconnection and pin redistribution between chip and package substrate.Pinboard can be with
Intensive I/O leads are redistributed, the high density interconnection of multi-chip is realized, it is grand with grade to become nanometer-grade IC
Electric signal connects one of most effective means between seeing the world.When realizing that multifunction chip is integrated using pinboard, not same core
The antistatic effect of piece is different, and the weak chip of antistatic effect influences whether the anti-quiet of whole system after encapsulation when three-dimensional stacked
Electric energy power, therefore it is urgently to be resolved hurrily as semicon industry how to improve the antistatic effect of the system in package based on TSV techniques
The problem of.
The content of the invention
In order to improve the antistatic effect of the system in package based on TSV techniques, the present invention provides one kind based on laterally
The TSV pinboards of diode；The technical problem to be solved in the present invention is achieved through the following technical solutions：
The embodiment provides a kind of TSV pinboards based on transverse diode, including：
Si substrates 101；
TSV areas 102 are arranged in Si substrates 101；
Isolated area 103 is arranged in Si substrates 101 and between TSV areas 102；
Transverse diode 104 is arranged in Si substrates 101 and in the transverse seal region that isolated area 103 is formed；
Interconnection line 105, first end face and transverse diode 104 to TSV areas 102 are connected in series.
In one embodiment of the invention, the material in TSV areas 102 is polysilicon, the doping concentration of polysilicon for 2 ×
1021cm-3, impurity is phosphorus.
In one embodiment of the invention, 103 equal up/down perforation Si substrates 101 of TSV areas 102 and isolated area.
In one embodiment of the invention, the material in isolated area 103 is SiO2Or undoped polycrystalline silicon.
In one embodiment of the invention, the first end face in TSV areas 102 and transverse diode 104 and copper interconnecting line
Tungsten plug is provided between 105.
In one embodiment of the invention, tungsten plug and metal salient point 106 are provided in the second end face in TSV areas 102.
In one embodiment of the invention, the material of metal salient point 106 is copper.
In one embodiment of the invention, TSV pinboards further include the upper and lower surface for being arranged at Si substrates 101
Insulating layer.
In one embodiment of the invention, the depth of TSV areas 102 and isolated area 103 is 40~80 μm.
Compared with prior art, the invention has the advantages that：
1st, TSV pinboards provided by the invention are enhanced by setting ESD protection device diode on TSV pinboards
The antistatic effect of laminate packaging chip；
2nd, the present invention, using the higher heat-sinking capability of pinboard, improves device by setting diode on TSV pinboards
High current handling capacity in part work；
3rd, the isolated groove of up/down perforation is utilized around the diode of TSV pinboards provided by the invention, is had smaller
Leakage current and parasitic capacitance.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for this
For the those of ordinary skill of field, without creative efforts, others are can also be obtained according to these attached drawings
Attached drawing.
Fig. 1 is a kind of TSV adapter plate structure schematic diagrames based on transverse diode provided in an embodiment of the present invention；
Fig. 2 is a kind of preparation method flow chart of the TSV pinboards based on transverse diode provided in an embodiment of the present invention；
Fig. 3 a- Fig. 3 i are the preparation side of another TSV pinboards based on transverse diode provided in an embodiment of the present invention
Method flow chart；
Fig. 4 is another TSV adapter plate structure schematic diagrames based on transverse diode provided in an embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 shows for a kind of TSV adapter plate structures based on transverse diode provided in an embodiment of the present invention
It is intended to, including：
Si substrates 101；
TSV areas 102 are arranged in Si substrates 101；
Isolated area 103 is arranged in Si substrates 101 and between TSV areas 102；
Transverse diode 104 is arranged in Si substrates 101 and in the transverse seal region that isolated area 103 is formed；
Interconnection line 105, first end face and transverse diode 104 to TSV areas 102 are connected in series.
Preferably, the material in TSV areas 102 is polysilicon, and the doping concentration of polysilicon is 2 × 1021cm-3, adulterate miscellaneous
Matter is phosphorus.
Preferably, 103 equal up/down perforation Si substrates 101 of TSV areas 102 and isolated area.
Preferably, the material in isolated area 103 is SiO2Or undoped polycrystalline silicon.
Preferably, tungsten is provided between the first end face in TSV areas 102 and transverse diode 104 and copper interconnecting line 105 to insert
Plug.
Preferably, tungsten plug and metal salient point 106 are provided in the second end face in TSV areas 102.
Preferably, the material of metal salient point 106 is copper.
Preferably, TSV pinboards further include the insulating layer for the upper and lower surface for being arranged at Si substrates 101.
Further, isolated area 103 is used for the SiO with Si substrate top surfaces and lower surface2Insulating layer formed closing every
From region to isolate transverse diode 104.
Preferably, the depth of TSV areas 102 and isolated area 103 is 40~80 μm.
TSV pinboards provided in this embodiment, by processing static discharge (Electro-Static on TSV pinboards
Discharge, abbreviation ESD) protective device --- diode, the antistatic effect of system in package is enhanced, solves three-dimensional
The weak chip of antistatic effect influences whether the problem of antistatic effect of whole system after encapsulating during stacking；Meanwhile this implementation
Example provides the isolated area that up/down perforation is utilized around the diode of TSV pinboards, has smaller leakage current and parasitic capacitance.
Embodiment two
Fig. 2 is refer to, Fig. 2 is a kind of preparation of the TSV pinboards based on transverse diode provided in an embodiment of the present invention
Method flow diagram, the present embodiment is on the basis of above-described embodiment, to the TSV pinboards based on transverse diode of the invention
Preparation method is described in detail as follows.Specifically, include the following steps：
S201, Si substrates are chosen；
S202, multiple TSV and multiple isolated grooves are prepared on a si substrate using etching technics；
S203, multiple device trenches are prepared on a si substrate using etching technics；
S204, using chemical vapor deposition (Chemical Vapor Deposition, abbreviation CVD) technique, in Si substrates
Upper deposit SiO2Or undoped polycrystalline silicon is filled isolated groove to form isolated area；
S205, using CVD techniques, depositing polysilicon material is filled TSV to form TSV areas on a si substrate；
S206, using CVD techniques, depositing polysilicon material is filled device trenches on a si substrate, and prepares horizontal stroke
To the diode of structure；
S207, using electroplating technology, surface prepares copper interconnecting line on a si substrate；
S208, using chemically mechanical polishing (Chemical Mechanical Polishing, abbreviation CMP) technique, it is right
Si substrates are thinned, until leaking out TSV；
S209, in Si substrates lower surface electric plating method is utilized to form copper bump to complete the preparation of TSV pinboards.
Wherein, choose Si substrates the reason for be, the thermodynamic property of Si is identical with chip, by the use of Si materials as turn
Fishplate bar can reduce the bending of chip caused by the difference and residual stress of coefficient of thermal expansion to the full extent and chip should
Power.The crystal orientation of Si substrates can be (100), (110) or (111), in addition, the doping type of substrate can be N-type, it can also
For p-type.
Preferably, S202 may include steps of：
S2021, TSV and isolated groove figure are etched using photoetching process；
S2022, deep reaction ion etching method (Deep Reactive Ion Etching, abbreviation DRIE) work is utilized
Skill, etching Si substrates form TSV and isolated groove.
Wherein, the quantity of TSV is one or more, and the depth of TSV is less than the thickness of Si substrates；The quantity of isolated groove is
Multiple, the depth of isolated groove is less than Si substrate thickness；
Preferably, the depth of TSV is equal to the depth of isolated groove.
Preferably, S103 can include：
S2031, using photoetching process, form the etched features of device trenches in Si substrates；
S2032, dry etch process, etching Si substrate formation device trenches are utilized；
Wherein, for device trenches between isolated groove, the depth of device trenches is less than the depth of TSV and isolated groove.
Further, S204 may include steps of：
S2041, thermal oxide TSV and isolated groove make the inner wall of blind hole form oxide layer；
S2042, the oxide layer of TSV and isolated groove inner wall is etched using wet-etching technology to complete the flat of blind hole inner wall
Integralization.
Wherein, the protrusion that can prevent blind hole side wall by the planarizing of blind hole inner wall forms electric field concentrated area.
S2043, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete isolated groove and fill figure；
S2044, CVD techniques, deposit SiO are utilized2Isolated groove is filled to form isolated area.
Wherein, isolated area run through entire pinboard, effectively device can be isolated with substrate, reduce active area and
Parasitic capacitance between substrate.
Preferably, S205 may include steps of：
S2051, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and fill figure
S2052, using CVD techniques, depositing polysilicon material is filled TSV, at the same be passed through impurity gas carry out it is former
Position doping realizes the activation in situ of doped chemical, forms highly doped polysilicon TSV areas.
Wherein, filled by carrying out highly doped polysilicon in TSV areas, it is uniformly and highly doped that Impurity Distribution can be formed
The conductive material of concentration is conducive to reduce the resistance of TSV.
Preferably, S206 may include steps of：
S2061, the filling figure that device trenches are formed using photoetching process；
S2062, using CVD techniques, fill polycrystalline silicon material in device trenches；
S2063, photoetching P+Active area carries out P using band glue ion implantation technology+Injection removes photoresist, is formed laterally
The anode of diode；
S2064, photoetching N+Active area carries out N using band glue ion implantation technology+Injection removes photoresist, is formed laterally
The cathode of diode；
S2065, high annealing, activator impurity are carried out.
Preferably, S207 may include steps of：
S2071, sputtering or CVD techniques, on a si substrate surface formation laying and barrier layer, and utilize CVD works are utilized
The first end in Yi TSV areas and the anode and cathode of diode form tungsten plug；
S2072, deposition insulating layer, photoetching copper-connection figure deposit copper using electrochemical plating process for copper, pass through chemical machinery
Grinding technics removes extra copper, forms the copper interconnecting line that the first end in TSV areas is concatenated with diode.
Further, when preparing copper interconnecting line, surround spiral using metal interconnecting wires and make it have inductance
Characteristic to be more particularly for the electrostatic protection of RF IC.
Preferably, S208 may include steps of：
S2081, by the use of high molecular material as interlayer, by Si substrate top surfaces and auxiliary wafer bonding, pass through auxiliary
Disk supports Si substrate top surfaces；
S2082, Si substrates lower surface is thinned using mechanical grinding reduction process, is slightly larger than TSV depths until reducing to
The thickness of degree；
S2083, smooth, the second end until exposing TSV areas is carried out to Si substrates lower surface using CMP process.
Preferably, S209 may include steps of：
S2091, laying and barrier layer are formed in Si substrates lower surface using sputtering or CVD techniques, is existed using CVD techniques
The second end in TSV areas forms tungsten plug；
S2092, deposition insulating layer, the second end photoetching copper bump figure in TSV areas are deposited using electrochemical plating process for copper
Copper removes extra copper by chemical mechanical milling tech, and the second end in TSV areas forms copper bump.
S2093, the auxiliary disk being bonded temporarily using the technique dismounting of heated mechanical.
The preparation method of TSV pinboards provided in this embodiment, it is mutually compatible with typical CMOS technology, be conducive to industry
Change；Using the diode component of transversary, parasitic capacitance is small, RF IC is influenced small.
Embodiment three
The present embodiment is on the basis of above-described embodiment, to the system of the TSV pinboards based on transverse diode of the present invention
Design parameter citing is described as follows in Preparation Method.Specifically, Fig. 3 a- Fig. 3 i, Fig. 3 a- Fig. 3 i are refer to carry for the embodiment of the present invention
The preparation method flow chart of another TSV pinboards based on transverse diode of confession,
S301, Si substrates 301 are chosen, as shown in Figure 3a；
Preferably, the doping concentration of Si substrates is 1014~1017cm-3, thickness is 150~250 μm.
S302, as shown in Figure 3b；Prepare two TSV302 and three isolated grooves on a si substrate using etching technics
303, it may include steps of：
S3021, at a temperature of 1050 DEG C~1100 DEG C, utilize thermal oxidation technology on a si substrate surface grow one layer
The SiO of 800nm~1000nm2Layer；
S3022, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and isolated groove etched features；
S3023, Si substrates are etched using DRIE techniques, forms the TSV and isolated groove of 40~80 μm of depths.
S3024, using CMP process, remove the SiO on Si substrates2, substrate surface is planarized.
S303, as shown in Figure 3c；It prepares two device trenches 304 on a si substrate using etching technics, can specifically wrap
Include following steps：
S3031, CVD techniques deposit silicon nitride layer on a si substrate is utilized；
S3032, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete device trenches etched features；
S3033, device trenches are formed using dry etch process, etch nitride silicon layer and Si substrates；The depth of device trenches
It spends for 15~25 μm；
S3034, using CMP process, remove the silicon nitride layer on Si substrates, substrate surface planarized.
S304, as shown in Figure 3d；Using CVD techniques, SiO is deposited on a si substrate2Shape is filled to isolated groove 303
Into isolated area, specifically may include steps of：
S3041, at a temperature of 1050 DEG C~1100 DEG C, the inner wall of thermal oxide TSV, isolated groove and device trenches are formed
Thickness is the oxide layer of 200nm~300nm；
S3042, using wet-etching technology, the oxide layer of the inner wall of etching TSV, isolated groove and device trenches is to complete
The planarizing of TSV and isolated groove inner wall.To prevent the protrusion of TSV, isolated groove and device trenches side wall form electric field from concentrating
Region.
S3043, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete isolated groove and fill figure；
S3044, at a temperature of 690 DEG C~710 DEG C, utilize low-pressure chemical vapor deposition (Low Pressure
Chemical Vapor Deposition, LPCVD) technique, deposit SiO2Isolated groove is filled, forms isolated area；It can
With understanding, the SiO2Material is mainly used for isolating, and can be substituted by other materials such as undoped polycrystalline silicons.
S3045, using CMP process, substrate surface is planarized.
S305, as shown in Figure 3 e；Using CVD techniques, depositing polysilicon material is filled TSV302 on a si substrate,
Impurity gas is passed through simultaneously, TSV areas are formed to polysilicon progress doping in situ, specifically may include steps of：
S3051, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and fill figure；
S3052, at a temperature of 600 DEG C~620 DEG C, TSV is filled using CVD technique depositing polysilicon materials,
Impurity gas is passed through simultaneously and carries out doping in situ, and realizes the activation in situ of doped chemical, forms highly doped polysilicon filling.
Impurity Distribution can be so formed when being filled to TSV uniformly and the conductive material of high-dopant concentration is filled, beneficial to reduction TSV
Resistance.Polysilicon doping concentration preferably 2 × 1021cm-3, the preferred phosphorus of impurity；
S3054, substrate surface is planarized using CMP process.
S306, as illustrated in figure 3f；Using CVD techniques, depositing polysilicon material carries out device trenches 304 on a si substrate
Filling, and the anode 305 of diode and cathode 306 are formed using ion implantation technology, the diode of transversary is formed, specifically
It may include steps of：
S3061, using photoetching process, between two adjacent isolated areas, pass through the techniques shape such as gluing, photoetching, development
Into the filling figure of device trenches.
S3062, using LPCVD techniques, at a temperature of 600 DEG C~950 DEG C, selective epitaxial growth polysilicon, simultaneously
It is passed through impurity gas and carries out doping in situ, and realize the activation in situ of doped chemical, form N-The polysilicon filling of doping.Doping
Concentration is 5 × 1014cm-3, the preferred phosphorus of impurity.
S3063, using CMP process, substrate surface is planarized.
S3064, photoetching P+Active area carries out P using band glue ion implantation technology+Injection removes photoresist, forms two poles
The anode of pipe.Doping concentration is 5 × 1018cm-3, impurity is boron.
S3065, photoetching N+Active area carries out N using band glue ion implantation technology+Injection removes photoresist, forms two poles
The cathode of pipe.Doping concentration preferably 5 × 1018cm-3, the preferred phosphorus of impurity.
S3066, by substrate at a temperature of 950~1100 DEG C, anneal 15~120s, carry out impurity activation.
S307, as shown in figure 3g；Using electroplating technology, surface forms copper interconnecting line 307 on a si substrate, can specifically wrap
Include following steps：
S3071, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor are utilized
Deposition, PECVD) technique, deposit SiO in substrate surface2Layer；
S3072, in the first end in TSV areas and the anode of diode and cathode, using photoetching process, pass through gluing, light
The techniques such as quarter, development complete contact hole graph；
S3073, using CVD techniques, in the first end in TSV areas and the anode of diode and cathode deposition Ti films, TiN film
With tungsten to form tungsten plug；
S3074, substrate surface is planarized using CMP process.
S3075, deposit SiO2Insulating layer, photoetching copper-connection figure deposit copper, passing through using the method for Cu electroplating
The method for learning mechanical lapping removes extra copper, and the first end for forming TSV areas concatenates copper interconnecting line with diode；
S3076, substrate surface is planarized using CMP process.
S3077, using pecvd process, deposit SiO in substrate surface2Layer；
S308, as illustrated in figure 3h；Si substrates are thinned using CMP process, leak out TSV areas, specifically
It may include steps of：
S3081, by the use of high molecular material as interlayer, by Si substrate top surfaces and auxiliary wafer bonding, pass through auxiliary
Being thinned for Si substrates is completed in the support of disk；
S3082, Si substrates lower surface is thinned using mechanical grinding reduction process, is slightly larger than TSV areas until reducing to
The thickness of depth, preferably greater than 10 μm of TSV depth；
S3083, Si substrates lower surface is carried out using CMP process it is smooth, until exposing TSV areas；
S309, as shown in figure 3i；Copper bump 308 is formed using electric plating method in Si substrates lower surface, can specifically be wrapped
Include following steps：
S3091, using pecvd process, deposit SiO in substrate lower surface2Layer；
Using photoetching process, contact hole is completed by techniques such as gluing, photoetching, developments for S3092, the second end in TSV areas
Figure；
S3093, using CVD techniques, in second end face deposit Ti films, TiN film and the tungsten in TSV areas to form tungsten plug；
S3094, substrate surface is planarized using CMP process；
S3095, deposit SiO2Insulating layer, the second end photoetching copper bump figure in TSV areas, utilizes electrochemical plating process for copper
Copper is deposited, extra copper is removed by chemical mechanical milling tech, etches SiO2Layer, the second end in TSV areas form copper bump；
S3096, the auxiliary disk being bonded temporarily using the method dismounting of heated mechanical.
The preparation method of TSV pinboards provided in this embodiment, using diode component periphery by SiO2Insulating layer surrounds
Technique, the parasitic capacitance between active area and substrate can be effectively reduced.The present invention passes through on the basis of technological feasibility is considered
The TSV holes of optimal design-aside certain length and the doping concentration using given range, and consider the electric current handling capacity of device, subtract
Small parasitic capacitance and resistance, and a degree of tuning is carried out to the parasitic capacitance of device using the inductance that TSV holes introduce,
The working range of esd protection circuit is expanded while improving system in package anti-ESD abilities.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to assert
The specific implementation of the present invention is confined to these explanations.For example, the multiple isolated areas referred in the present invention are only according to this hair
The device architecture sectional view of bright offer illustrates, wherein, multiple isolated areas can also be such as ring bodies in some entirety
The first portion that shows of sectional view and second portion, for those of ordinary skill in the art to which the present invention belongs, no
These explanations should be confined to, without departing from the inventive concept of the premise, several simple deduction or replace can also be made, all should
It is enclosed when being considered as belonging to protection scope of the present invention.
Claims (9)
1. a kind of TSV pinboards based on transverse diode, which is characterized in that including：
Si substrates (101)；
TSV areas (102) are arranged in the Si substrates (101)；
Isolated area (103) is arranged in the Si substrates (101) and between the TSV areas (102)；
Transverse diode (104), the horizontal envelope for being arranged in the Si substrates (101) and being formed positioned at the isolated area (103)
In closed region；
Interconnection line (105) is connected in series the first end face and the transverse diode (104) of the TSV areas (102).
2. TSV pinboards according to claim 1, which is characterized in that the material in the TSV areas (102) is polysilicon,
The doping concentration of the polysilicon is 2 × 1021cm-3, impurity is phosphorus.
3. TSV pinboards according to claim 1, which is characterized in that the TSV areas (102) and the isolated area (103)
Si substrates (101) described in equal up/down perforation.
4. TSV pinboards according to claim 1, which is characterized in that the material in the isolated area (103) is SiO2Or
Undoped polycrystalline silicon.
5. TSV pinboards according to claim 1, which is characterized in that the first end face of the TSV areas (102) and described
Tungsten plug is provided between transverse diode (104) and interconnection line (105).
6. TSV pinboards according to claim 1, which is characterized in that set in the second end face of the TSV areas (102)
There are tungsten plug and metal salient point (106).
7. TSV pinboards according to claim 6, which is characterized in that the material of the metal salient point (106) is copper.
8. TSV pinboards according to claim 1, which is characterized in that the TSV pinboards, which further include, is arranged at the Si
The insulating layer of the upper and lower surface of substrate (101).
9. TSV pinboards according to claim 1, which is characterized in that the TSV areas (102) and the isolated area (103)
Depth be 40~80 μm.
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