CN108122818A - Anti-static device for system in package and preparation method thereof - Google Patents

Anti-static device for system in package and preparation method thereof Download PDF

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Publication number
CN108122818A
CN108122818A CN201711351048.7A CN201711351048A CN108122818A CN 108122818 A CN108122818 A CN 108122818A CN 201711351048 A CN201711351048 A CN 201711351048A CN 108122818 A CN108122818 A CN 108122818A
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China
Prior art keywords
tsv
substrates
preparation
areas
diode
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Inventor
李妤晨
岳改丽
童军
刘树林
张超
徐大庆
张岩
刘宁庄
杨波
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Xian University of Science and Technology
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Xian University of Science and Technology
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Priority to CN201711351048.7A priority Critical patent/CN108122818A/en
Publication of CN108122818A publication Critical patent/CN108122818A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The present invention relates to a kind of for anti-static device of system in package and preparation method thereof, this method includes：Choose Si substrates；At least three diodes are prepared in the Si substrates；It etches the Si substrates and forms isolated groove and TSV in the diode both sides respectively；The isolated groove is filled respectively and the TSV forms isolated area and TSV areas；The first end face in the TSV areas and the interconnection line of the diode are prepared in the Si substrate top surfaces；Second end face in the TSV areas prepares metal salient point to complete the preparation of the TSV pinboards.Anti-static device provided by the invention is used as ESD protection device by processing diode on TSV pinboards, solves the problems, such as that the IC system grade encapsulation antistatic effect based on TSV techniques is weak, enhances the antistatic effect power of IC system grade encapsulation.

Description

Anti-static device for system in package and preparation method thereof
Technical field
The invention belongs to semiconductor integrated circuit technology fields, more particularly to a kind of anti-static device for system in package And preparation method thereof.
Background technology
With the continuous development of science and technology, the requirement of size and power consumption to semiconductor chip is continuously improved, need smaller, Thinner and lighter, highly reliable, multi-functional, low-power consumption and the chip of low cost, in this background three-dimensional packaging technology meet the tendency of and It is raw.In the case where the packaging density of two-dimensional package technology has reached the limit, the advantage of more highdensity three-dimensional packaging technology is not sayed And it explains.
An important kind in three-dimensional packaging technology is lamination-type three-dimension packaging, in the art, by multiple chips or Multi-chip module (MCM) is stacked arrangement along Z axis and interconnects to form three-dimension packaging structure each other.Lamination-type 3D encapsulation is due to being applicable in The advantages that scope is wide, simple for process, at low cost and as the core manufacturing technology of the famous chip manufacturer such as IBM, Intel.
Silicon hole (Through-Silicon Via, abbreviation TSV) is one that interconnection is realized in lamination-type three-dimensional packaging technology Kind solution, has many advantages, such as shorter interconnection distance and faster speed.
Pinboard typically refers to the functional layer of the interconnection and pin redistribution between chip and package substrate.Pinboard can be with Intensive I/O leads are redistributed, the high density interconnection of multi-chip is realized, it is grand with grade to become nanometer-grade IC Electric signal connects one of most effective means between seeing the world.When realizing that multifunction chip is integrated using pinboard, not same core The antistatic effect of piece is different, and the weak chip of antistatic effect influences whether the anti-quiet of whole system after encapsulation when three-dimensional stacked Electric energy power, therefore it is urgently to be resolved hurrily as semicon industry how to improve the antistatic effect of the system in package based on TSV techniques The problem of.
The content of the invention
In order to improve the antistatic effect of the system in package based on TSV techniques, the present invention provides one kind to be used for system Anti-static device of grade encapsulation and preparation method thereof；The technical problem to be solved in the present invention is achieved through the following technical solutions：
The embodiment provides a kind of preparation method of the anti-static device for system in package, including：
S101, Si substrates are chosen；
S102, at least three diodes are prepared in Si substrates；
S103, etching Si substrates form isolated groove and TSV in diode both sides respectively；
S104, isolated groove and TSV formation isolated areas and TSV areas are filled respectively；
S105, on a si substrate surface prepare the first end face in TSV areas and the interconnection line of diode；
S106, the second end face in TSV areas prepare metal salient point to complete the preparation of TSV pinboards.
In one embodiment of the invention, Si substrates be N-type or p-type, doping concentration 1014~1017cm-3, thickness is 150~250 μm.
In one embodiment of the invention, S102 includes：
S1021, device trenches are prepared in Si substrates；
S1022, device trenches inner wall is planarized；
S1023, the filling figure that device trenches are formed using photoetching process；
S1024, using chemical vapor deposition (Chemical Vapor Deposition, abbreviation CVD) technique, in device Trench fill polycrystalline silicon material；
S1025, photoetching P+Active area carries out P using band glue ion implantation technology+Ion implanting removes photoresist, is formed The anode of diode；
S1026, photoetching N+Active area carries out N using band glue ion implantation technology+Ion implanting removes photoresist, is formed The cathode of diode；
S1027, high annealing, activator impurity are carried out.
In one embodiment of the invention, the depth of device trenches is 15~25 μm.
In one embodiment of the invention, S103 includes：
S1031, using photoetching process, form the etched features of TSV and isolated groove in the upper surface of Si substrates；
S1032, deep reaction ion etching (Deep Reactive Ion Etching, abbreviation DRIE) technique, quarter are utilized It loses Si substrates and forms TSV and isolated groove.
In one embodiment of the invention, S104 includes：
The inner wall of S1041, planarizing TSV and isolated groove；
S1042, the filling figure that isolated groove is formed using photoetching process；
S1043, using CVD techniques, SiO is filled in isolated groove2Form isolated area；
S1044, the filling figure that TSV is formed using photoetching process；
S1045, adhesion layer and Seed Layer are made using physical vapor deposition methods；
S1046, TSV is filled by the method for electrochemical deposition to form TSV areas.
In one embodiment of the invention, S105 includes：
S1051, sputtering or CVD techniques, on a si substrate surface formation laying and barrier layer, and utilize CVD works are utilized Skill forms tungsten plug in the anode and cathode of diode；
S1052, deposition insulating layer, photoetching copper-connection figure deposit copper using electrochemical plating process for copper, pass through chemical machinery Grinding technics removes extra copper, forms the copper interconnecting line that the first end in TSV areas is concatenated with diode.
In one embodiment of the invention, further included before S106：
X1, by the use of aiding in supporting item of the disk as Si substrate top surfaces；
X2, Si substrates lower surface is thinned using mechanical grinding reduction process, recycles chemically mechanical polishing (Chemical Mechanical Polishing, abbreviation CMP) technique carries out planarizing process, directly to the lower surface of Si substrates To the second end face for exposing TSV areas.
In one embodiment of the invention, the depth of TSV areas and isolated area is 40~80 μm.
Compared with prior art, the invention has the advantages that：
1st, the anti-static device that the present invention forms system in package by processing diode on pinboard, enhances stacking Encapsulate the antistatic effect of chip；
2nd, the present invention, using the higher heat-sinking capability of pinboard, improves device by processing diode on TSV pinboards High current handling capacity in part work；
3rd, the isolated groove of up/down perforation is utilized around the diode of anti-static device provided by the invention, is had smaller Leakage current and parasitic capacitance；
It 4th, can be in existing TSV techniques provided by the present invention for the preparation method of the TSV pinboards of system in package It is realized in platform, therefore compatibility is strong, it is applied widely.
Description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment Attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for this For the those of ordinary skill of field, without creative efforts, others are can also be obtained according to these attached drawings Attached drawing.
Fig. 1 is that a kind of preparation method flow of anti-static device for system in package provided in an embodiment of the present invention is shown It is intended to；
Fig. 2 a- Fig. 2 i are the preparation side of another anti-static device for system in package provided in an embodiment of the present invention Method flow chart；
Fig. 3 is a kind of anti-static device structure diagram for system in package provided in an embodiment of the present invention.
Specific embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of preparation of anti-static device for system in package provided in an embodiment of the present invention Method flow schematic diagram, including：
S101, Si substrates are chosen；
S102, at least three diodes are prepared in Si substrates；
S103, etching Si substrates form isolated groove and TSV in diode both sides respectively；
S104, isolated groove and TSV formation isolated areas and TSV areas are filled respectively；
S105, on a si substrate surface prepare the first end face in TSV areas and the interconnection line of diode；
S106, the second end face in TSV areas prepare metal salient point to complete the preparation of TSV pinboards.
Preferably, Si substrates be N-type or p-type, doping concentration 1014~1017cm-3, thickness is 150~250 μm.
Preferably, S102 can include：
S1021, device trenches are prepared in Si substrates；
S1022, device trenches inner wall is planarized；
S1023, the filling figure that device trenches are formed using photoetching process；
S1024, using CVD techniques, fill polycrystalline silicon material in device trenches；
S1025, photoetching P+Active area carries out P using band glue ion implantation technology+Ion implanting removes photoresist, is formed The anode of diode；
S1026, photoetching N+Active area carries out N using band glue ion implantation technology+Ion implanting removes photoresist, is formed The cathode of diode；
S1027, high annealing, activator impurity are carried out.
Preferably, the depth of device trenches is 15~25 μm.
Preferably, S103 can include：
S1031, using photoetching process, form the etched features of TSV and isolated groove in the upper surface of Si substrates；
S1032, DRIE techniques, etching Si substrates formation TSV and isolated groove are utilized.
Preferably, S104 can include：
The inner wall of S1041, planarizing TSV and isolated groove；
S1042, the filling figure that isolated groove is formed using photoetching process；
S1043, using CVD techniques, SiO is filled in isolated groove2Form isolated area；
S1044, the filling figure that TSV is formed using photoetching process；
S1045, adhesion layer and Seed Layer are made using physical vapor deposition methods；
S1046, TSV is filled by the method for electrochemical deposition to form TSV areas.
Preferably, S105 can include：
S1051, sputtering or CVD techniques, on a si substrate surface formation laying and barrier layer, and utilize CVD works are utilized Skill forms tungsten plug in the anode and cathode of diode；
S1052, deposition insulating layer, photoetching copper-connection figure deposit copper using electrochemical plating process for copper, pass through chemical machinery Grinding technics removes extra copper, forms the copper interconnecting line that the first end in TSV areas is concatenated with diode.
Specifically, further included before S106：
X1, by the use of aiding in supporting item of the disk as Si substrate top surfaces；
X2, Si substrates lower surface is thinned using mechanical grinding reduction process, CMP process is recycled, to Si substrates Lower surface carry out planarizing process, the second end face until exposing TSV areas.
Preferably, the depth of TSV areas and isolated area is 40~80 μm.
The preparation method of anti-static device provided in this embodiment, by processing ESD static discharges on TSV pinboards (Electro-Static Discharge, abbreviation ESD) protective device --- diode, enhances the antistatic of system in package Ability, antistatic effect weak chip influences whether that the antistatic effect of whole system after encapsulation is asked when solving three-dimensional stacked Topic；Meanwhile the isolated area of up/down perforation is utilized around the diode of anti-static device provided in this embodiment, there is smaller leakage Electric current and parasitic capacitance.
Embodiment two
The present embodiment is on the basis of above-described embodiment, to design parameter in the preparation method of the TSV pinboards of the present invention Citing is described as follows.Specifically, Fig. 2 a- Fig. 2 i, Fig. 2 a- Fig. 2 i be refer to be provided in an embodiment of the present invention another for being The preparation method flow chart of the anti-static device of irrespective of size encapsulation.
Specifically, include the following steps：
S201, as shown in Figure 2 a chooses Si substrates 201；
Preferably, the crystal orientation of Si substrates can be (100), (110) or (111), and the doping concentration of Si substrates is 1014~ 1017cm-3, thickness is 150~250 μm.
S202, as shown in Figure 2 b, forms device trenches 202 using etching technics on a si substrate；
S2021, using CVD techniques, deposit silicon nitride layer on a si substrate；
S2022, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete device trenches etched features；
S2023, device trenches are formed using dry etch process etch nitride silicon layer and Si substrates；
S2024, at a temperature of 1050 DEG C~1100 DEG C thermal oxide device trenches so that inner wall formed 200nm~300nm Thick oxide layer；
S2025, using the oxide layer of wet-etching technology etched features trench wall to complete the planarizing of inner wall；Pass through Planarizing can prevent the protrusion of blind hole side wall from forming electric field concentrated area.
S2026, using CMP process, substrate surface is planarized.
Preferably, the depth of device trenches is 15~25 μm.
S203, as shown in Figure 2 c, using CVD techniques, depositing polysilicon material fills out device trenches on a si substrate It fills, the anode 203 of diode and cathode 204 is formed using the mode of ion implanting；
S2031, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete device trenches and fill figure；
S2032, using low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) technique in 600 DEG C~950 DEG C of temperature, utilizes selective polysilicon epitaxial growing method selective epitaxial growth silicon Material, while be passed through impurity gas and carry out doping in situ, and realize the activation in situ of doped chemical, form N-The polysilicon of doping Filling.Doping concentration preferably 5 × 1014cm-3, the preferred phosphorus of impurity；
S2033, using CMP process, substrate surface is planarized；
S2034, photoetching P+ active areas, carry out P by the way of with glue ion implanting+Injection removes photoresist, forms two The anode of pole pipe；Doping concentration preferably 5 × 1018cm-3, the preferred boron of impurity；
S2035, photoetching N+ active areas, carry out N by the way of with glue ion implanting+Injection removes photoresist, forms two The cathode of pole pipe.Doping concentration preferably 5 × 1018cm-3, the preferred phosphorus of impurity；
S2036, by substrate at a temperature of 950~1100 DEG C, anneal 15~120s, carry out impurity activation.
S204, as shown in Figure 2 d；It prepares isolated groove 205 and TSV206 on a si substrate using etching technics, can wrap Include following steps：
S2041, at a temperature of 950 DEG C~1100 DEG C, utilize thermal oxidation technology one layer of surface deposition on a si substrate The SiO of 800nm~1000nm2Layer；
S2042, using photoetching process, by gluing, photoetching, development and etc. complete TSV and isolated groove etched features；
S2043, Si substrates are etched using DRIE techniques, forms the TSV and isolated groove of 40~80 μm of depths；
S2044, using CMP process, remove the SiO on Si substrates2, substrate surface is planarized.
Specifically, each diode both sides respectively prepare an isolated groove, three diodes and its isolated groove both sides system Standby two TSV；By setting three diodes between two TSV, the antistatic effect of pinboard can be effectively improved.
S205, as shown in Figure 2 e；Using CVD techniques, SiO is deposited on a si substrate2Isolated groove is filled to be formed Isolated area specifically may include steps of：
S2051, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor are utilized Deposition, PECVD) technique, in TSV and isolated groove surface deposition SiO2, the inner wall of TSV and isolated groove is made to form thickness It spends for 200nm~300nm oxide layers；
S2052, using wet-etching technology, etch the oxide layer of inner wall of TSV and isolated groove to complete TSV and isolation The planarizing of trench wall.To prevent the protrusion of TSV and isolated groove side wall from forming electric field concentrated area.
S2053, using photoetching process, by gluing, photoetching, development and etc. complete isolated groove and fill figure；
S2054, at a temperature of 690 DEG C~710 DEG C, utilize LPCVD techniques, deposit SiO2Isolated groove is filled out It fills, forms isolated area；Wherein, the SiO2Material is mainly used for isolating, and can be substituted by other materials such as undoped polycrystalline silicons.
S2055, using CMP process, substrate surface is planarized.
S206, as shown in figure 2f；Using copper plating process, deposit copper product is filled TSV to form TSV areas, specifically It may include steps of：
S2061, one layer of adhesion layer and one layer of Seed Layer are made using physical vapor deposition methods, the material of adhesion layer is titanium Or tantalum, the material of Seed Layer is copper；
S2062, copper product is filled in TSV by the method for electrochemical deposition；
S2063, CMP process, the extra metal layer of removal substrate surface are utilized.
S207, as shown in Figure 2 g；Using electroplating technology, surface forms copper interconnecting line 207 on a si substrate, can specifically wrap Include following steps：
S2071, using pecvd process, deposit SiO in substrate surface2Layer；
S2072, anode and cathode in diode, using photoetching process, by gluing, photoetching, development and etc. completion Contact hole graph；
S2073, using CVD techniques, anode and cathode deposition Ti films, TiN film and tungsten in diode are to form tungsten plug 207；
S2074, substrate surface is planarized using CMP process.
S2075, deposit SiO2Insulating layer, photoetching copper-connection figure deposit copper, passing through using the method for Cu electroplating The method for learning mechanical lapping removes extra copper, and the first end for forming TSV areas concatenates copper interconnecting line with diode；
S2076, substrate surface is planarized using CMP process.
Further, when preparing copper interconnecting line, surround spiral using metal interconnecting wires and make it have inductance Characteristic to be more particularly for the electrostatic protection of RF IC.
S208, as shown in fig. 2h；Si substrates are thinned using CMP process, TSV areas is leaked out, specifically may be used To include the following steps：
S2081, by the use of high molecular material as interlayer, by Si substrate top surfaces and auxiliary wafer bonding, pass through auxiliary Being thinned for Si substrates is completed in the support of disk；
S2082, Si substrates lower surface is thinned using mechanical grinding reduction process, is slightly larger than TSV areas until reducing to The thickness of depth, preferably greater than 10 μm of TSV depth；
S2083, Si substrates lower surface is carried out using CMP process it is smooth, until exposing TSV areas；
S209, as shown in fig. 2i；Copper bump 208 is formed using electric plating method in Si substrates lower surface, can specifically be wrapped Include following steps：
S2091, deposit SiO2Insulating layer, the second end photoetching copper bump figure in TSV areas, utilizes electrochemical plating process for copper Copper is deposited, extra copper is removed by chemical mechanical milling tech, etches SiO2Layer, the second end in TSV areas form copper bump；
S2092, the auxiliary disk being bonded temporarily using the method dismounting of heated mechanical.
The preparation method of anti-static device provided in this embodiment, it is mutually compatible with existing process, be conducive to industrialization；Using The diode component of transversary, parasitic capacitance is small, RF IC is influenced small.
The preparation method of anti-static device provided in this embodiment, using diode component periphery by SiO2Insulating layer surrounds Technique, the parasitic capacitance between active area and substrate can be effectively reduced.The present invention passes through on the basis of technological feasibility is considered The TSV holes of optimal design-aside certain length and the doping concentration using given range, and consider the electric current handling capacity of device, subtract Small parasitic capacitance and resistance, and a degree of tuning is carried out to the parasitic capacitance of device using the inductance that TSV holes introduce, The working range of esd protection circuit is expanded while improving system in package anti-ESD abilities.
Embodiment three
It refer to Fig. 3, Fig. 3 a kind of shows to be provided in an embodiment of the present invention for the anti-static device structure of system in package It is intended to；The TSV pinboards are made using the above-mentioned preparation process as shown in Fig. 2 a- Fig. 2 i.
Specifically, TSV pinboards include：
Si substrates 301；
At least two TSV areas 302, are arranged in Si substrates 301；
At least three isolated areas 303 are arranged in Si substrates 301 and between each two TSV areas 302；
Transverse diode 304 is arranged in Si substrates 301 and between two neighboring isolated area 303；
Interconnection line 305, first end face and transverse diode 304 to TSV areas 302 are connected in series.
Preferably, the doping type of Si substrates 301 be N-type or p-type, doping concentration 1014~1017cm-3, thickness 150 ~250 μm.
Preferably, 303 equal up/down perforation Si substrates 301 of TSV areas 302 and isolated area.
Preferably, the material in isolated area 303 is SiO2Or undoped polycrystalline silicon.
Preferably, tungsten is provided between the first end face in TSV areas 302 and transverse diode 304 and copper interconnecting line 305 to insert Plug.
Preferably, tungsten plug and metal salient point 306 are provided in the second end face in TSV areas 302.
Preferably, the material of metal salient point 306 is copper.
Preferably, TSV pinboards further include the insulating layer for the upper and lower surface for being arranged at Si substrates 301.
Specifically, isolated area 303 be used for and 301 upper and lower surface of Si substrates insulating layer formed closing area of isolation with every From diode 304.
Preferably, the depth of TSV areas 302 and isolated area 303 is 40~80 μm.
Anti-static device provided in this embodiment, it is simple in structure, very big ESD electric currents can be born and be unlikely to make partly to lead Body device heating fails；Using the higher heat-sinking capability of pinboard, the high current handling capacity in device work is improved； The isolated groove of up/down perforation around the diode of TSV pinboards is set, there is smaller leakage current and parasitic capacitance.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to assert The specific implementation of the present invention is confined to these explanations.For example, the multiple isolated areas referred in the present invention are only according to this hair The device architecture sectional view of bright offer illustrates, wherein, multiple isolated areas can also be such as ring bodies in some entirety The first portion that shows of sectional view and second portion, for those of ordinary skill in the art to which the present invention belongs, no These explanations should be confined to, without departing from the inventive concept of the premise, several simple deduction or replace can also be made, all should When being considered as belonging to protection scope of the present invention.

Claims (10)

1. a kind of preparation method of anti-static device for system in package, which is characterized in that including：
S101, Si substrates are chosen；
S102, at least three diodes are prepared in the Si substrates；
S103, the etching Si substrates form isolated groove and TSV in the diode both sides respectively；
S104, the isolated groove and TSV formation isolated areas and TSV areas are filled respectively；
S105, the first end face that the TSV areas are prepared in the Si substrate top surfaces and the interconnection line of the diode；
S106, the second end face in the TSV areas prepare metal salient point to complete the preparation of the TSV pinboards.
2. preparation method according to claim 1, which is characterized in that the Si substrates are N-type or p-type, and doping concentration is 1014~1017cm-3, thickness is 150~250 μm.
3. preparation method according to claim 1, which is characterized in that S102 includes：
S1021, device trenches are prepared in the Si substrates；
S1022, the device trenches inner wall is planarized；
S1023, the filling figure that the device trenches are formed using photoetching process；
S1024, using CVD techniques, fill polycrystalline silicon material in the device trenches；
S1025, photoetching P+Active area carries out P using band glue ion implantation technology+Ion implanting removes photoresist, forms two poles The anode of pipe；
S1026, photoetching N+Active area carries out N using band glue ion implantation technology+Ion implanting removes photoresist, forms two poles The cathode of pipe；
S1027, high annealing, activator impurity are carried out.
4. preparation method according to claim 3, which is characterized in that the depth of the device trenches is 15~25 μm.
5. preparation method according to claim 1, which is characterized in that S103 includes：
S1031, using photoetching process, form the etching figure of the TSV and the isolated groove in the upper surface of the Si substrates Shape；
S1032, using DRIE techniques, etch the Si substrates and form the TSV and the isolated groove.
6. preparation method according to claim 1, which is characterized in that S104 includes：
S1041, the inner wall for planarizing the TSV and the isolated groove；
S1042, the filling figure that the isolated groove is formed using photoetching process；
S1043, using CVD techniques, fill SiO in the isolated groove2Form the isolated area；
S1044, the filling figure that the TSV is formed using photoetching process；
S1045, adhesion layer and Seed Layer are made using physical vapor deposition methods；
S1046, the TSV is filled by the method for electrochemical deposition to form the TSV areas.
7. preparation method according to claim 1, which is characterized in that S105 includes：
S1051, sputtering or CVD techniques, on a si substrate surface formation laying and barrier layer, and exist using CVD techniques are utilized The anode and cathode of diode form tungsten plug；
S1052, deposition insulating layer, photoetching copper-connection figure deposit copper using electrochemical plating process for copper, pass through chemical mechanical grinding Technique removes extra copper, forms the copper interconnecting line that the first end in TSV areas is concatenated with diode.
8. preparation method according to claim 1, which is characterized in that further included before S106：
X1, by the use of aiding in supporting item of the disk as the Si substrate top surfaces；
X2, the Si substrates lower surface is thinned using mechanical grinding reduction process, CMP process is recycled, to the Si The lower surface of substrate carries out planarizing process, the second end face until exposing the TSV areas.
9. preparation method according to claim 1, which is characterized in that the depth of the TSV areas and the isolated area is 40 ~80 μm.
10. a kind of anti-static device for system in package, which is characterized in that the TSV pinboards are by claim 1~9 Any one of them method prepares to be formed.
CN201711351048.7A 2017-12-15 2017-12-15 Anti-static device for system in package and preparation method thereof Pending CN108122818A (en)

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US20130119502A1 (en) * 2011-11-16 2013-05-16 Analog Devices, Inc. Electrical overstress protection using through-silicon-via (tsv)
CN105264660A (en) * 2013-05-21 2016-01-20 吉林克斯公司 Charge damage protection on an interposer for a stacked die assembly

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