CN107946240A - TSV pinboards and preparation method thereof - Google Patents
TSV pinboards and preparation method thereof Download PDFInfo
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- CN107946240A CN107946240A CN201711349187.6A CN201711349187A CN107946240A CN 107946240 A CN107946240 A CN 107946240A CN 201711349187 A CN201711349187 A CN 201711349187A CN 107946240 A CN107946240 A CN 107946240A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 238000000034 method Methods 0.000 claims abstract description 100
- 239000000463 material Substances 0.000 claims abstract description 66
- 239000010949 copper Substances 0.000 claims abstract description 28
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052802 copper Inorganic materials 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000008569 process Effects 0.000 claims description 50
- 238000001259 photo etching Methods 0.000 claims description 40
- 238000005516 engineering process Methods 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000012535 impurity Substances 0.000 claims description 16
- 238000011049 filling Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 14
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 229910052681 coesite Inorganic materials 0.000 claims description 13
- 229910052906 cristobalite Inorganic materials 0.000 claims description 13
- 229910052682 stishovite Inorganic materials 0.000 claims description 13
- 229910052905 tridymite Inorganic materials 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 10
- 239000003292 glue Substances 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 9
- 238000011065 in-situ storage Methods 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 8
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 238000003701 mechanical milling Methods 0.000 claims description 5
- 238000011946 reduction process Methods 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 239000012190 activator Substances 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 10
- 238000005538 encapsulation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 28
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- 238000011161 development Methods 0.000 description 8
- 230000018109 developmental process Effects 0.000 description 8
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- 238000004026 adhesive bonding Methods 0.000 description 7
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- 230000004913 activation Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
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- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 241000969106 Megalaima haemacephala Species 0.000 description 2
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
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- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a kind of TSV pinboards and preparation method thereof, this method includes：Choose substrate material；The upper surface for etching the substrate material forms multiple TSV and multiple isolated grooves respectively；Fill the isolated groove and the TSV；ESD protection device is prepared between the isolated groove；The first end in the TSV areas and the copper interconnecting line of the ESD protection device are prepared in the substrate material upper surface；The lower surface of the substrate material is thinned the second end until leaking out the TSV areas；Second end in the TSV areas prepares copper bump to complete the preparation of the TSV pinboards.TSV pinboards provided by the invention are used as ESD protection device by processing diode on TSV pinboards, solve the problems, such as that the IC system level encapsulation antistatic effect based on TSV techniques is weak, enhance the antistatic effect of IC system level encapsulation.
Description
Technical field
The invention belongs to semiconductor integrated circuit technical field, more particularly to a kind of TSV pinboards and preparation method thereof.
Background technology
The characteristic size of integrated circuit as low as 7nm so far, integrated number of transistors has been on a single chip
Through reaching 10,000,000,000 ranks, with the requirement of the number of transistors of 10,000,000,000 ranks, Resources on Chip and interconnection length problem become existing
The bottleneck of modern integrated circuit fields development, 3D integrated circuits are considered as the developing direction of future integrated circuits, it is in original electricity
On the basis of road, it is laminated on Z axis, in the hope of integrating more functions on minimum area, this method overcomes original collection
The limitation of Cheng Du, using emerging technology silicon hole (Through-Silicon Via, abbreviation TSV), is greatly improved integrated
The performance of circuit, reduces and postpones on line, reduces chip power-consumption.
Inside semicon industry, with the raising of integrated circuit integrated level and the reduction of device feature size, integrate
Potentiality damage has become more next caused by static discharge (Electro-Static Discharge, abbreviation ESD) in circuit
It is more obvious.According to relevant report, the failure for having nearly 35% in the failure of integrated circuit fields is triggered by ESD, therefore chip
Inside is all designed with esd protection structure to improve the reliability of device.
Pinboard typically refers to the functional layer of the interconnection and pin redistribution between chip and package substrate.Pinboard can be with
Intensive I/O leads are redistributed, the high density interconnection of multi-chip is realized, it is grand with grade to become nanometer-grade IC
Electric signal connects one of most effective means between seeing the world.When realizing that multifunction chip integrates using pinboard, not same core
The antistatic effect of piece is different, and the weak chip of antistatic effect influences whether the anti-quiet of whole system after encapsulation when three-dimensional stacked
Electric energy power, therefore the antistatic effect for how improving the system in package based on TSV techniques is urgently to be resolved hurrily as semicon industry
The problem of.
The content of the invention
In order to improve the antistatic effect of the 3D integrated circuits based on TSV techniques, the present invention provides a kind of TSV pinboards
And preparation method thereof；The technical problem to be solved in the present invention is achieved through the following technical solutions：
The embodiment provides a kind of preparation method of TSV pinboards, including：
S101, choose substrate material；
S102, the upper surface of etched substrate material form multiple TSV and multiple isolated grooves respectively；
S103, filling isolated groove and TSV form isolated area and TSV areas respectively；
S104, prepare ESD protection device in the closed area that isolated area and substrate material are formed；
S105, the first end face for preparing in substrate material upper surface TSV areas and the interconnection line of ESD protection device；
The second end face until leaking out TSV areas is thinned in S106, the lower surface to substrate material；
S107, the second end face in TSV areas prepare metal salient point to complete the preparation of TSV pinboards.
In one embodiment of the invention, substrate material is Si materials, and crystal orientation is (100), (110) or (111), doping
Concentration is 1014~1017cm-3, and thickness is 150~250 μm.
In one embodiment of the invention, S102 includes：
S1021, using photoetching process form the etched features of TSV and isolated groove in the upper surface of substrate material；
S1022, utilize deep reaction ion etching (Deep Reactive Ion Etching, abbreviation DRIE) technique, quarter
Lose substrate material and form TSV and isolated groove；
Wherein, the depth of TSV and isolated groove is less than the thickness of substrate material.
In one embodiment of the invention, S103 includes：
S1031, thermal oxide TSV and isolated groove are with the inner wall of TSV and isolated groove formation oxide layer；
S1032, using wet-etching technology, etching oxidation layer is to complete the planarizing of TSV and isolated groove inner wall；
S1033, the filling figure using photoetching process formation isolated groove；
S1034, using chemical vapor deposition (Chemical Vapor Deposition, abbreviation CVD) technique, isolating
Filling SiO2 forms isolated area in groove；
S1035, the filling figure using photoetching process formation TSV；
S1036, using CVD techniques, polysilicon is filled in TSV, and be passed through impurity gas and carry out doping in situ and form TSV
Area.
In one embodiment of the invention, ESD protection device is diode.
In one embodiment of the invention, S104 includes：
S1041, using chemically mechanical polishing (Chemical Mechanical Polishing, abbreviation CMP) technique, it is right
The upper surface of substrate material carries out smooth；
S1042, using photoetching process form P+ active area figures in the closed area that isolated area and substrate material are formed,
P+ injections are carried out using band glue ion implantation technology, photoresist is removed, forms the anode of diode；
S1043, using photoetching process form N+ active area figures in the closed area that isolated area and substrate material are formed,
N+ injections are carried out using band glue ion implantation technology, photoresist is removed, forms the cathode of diode；
S1044, carry out high annealing, activator impurity.
In one embodiment of the invention, S106 includes：
S1061, by the use of aiding in supporting item of the disk as substrate material upper surface；
S1062, using mechanical grinding reduction process be thinned substrate material lower surface, recycles CMP process, to lining
The lower surface of bottom material carries out planarizing process, the second end face until exposing TSV areas.
In one embodiment of the invention, S107 includes：
S1071, using sputtering technology, form laying and barrier layer in the lower surface of substrate material, existed using CVD techniques
The second end face in TSV areas forms tungsten plug；
S1072, deposition insulating layer, in the figure of the second end face photolithographic salient point in TSV areas, utilize electrochemical plating coppersmith
Skill deposits metal, and unnecessary metal is removed by chemical mechanical milling tech, and the second end face in TSV areas forms metal salient point；
S1073, remove auxiliary disk.
In one embodiment of the invention, metal is copper.
Compared with prior art, the invention has the advantages that：
1st, TSV pinboards provided by the invention are increased by processing ESD protection device --- diode on TSV pinboards
The strong antistatic effect of system in package chip；
2nd, the present invention, using the higher heat-sinking capability of pinboard, improves device by processing diode on TSV pinboards
High current handling capacity in part work；
3rd, the isolated groove of up/down perforation is utilized around the diode of TSV pinboards provided by the invention, is had less
Leakage current and parasitic capacitance；
4th, the preparation method of TSV pinboards provided by the invention can be realized in existing TSV technique platforms, therefore simultaneous
Capacitive is strong, applied widely.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill of field, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of preparation method flow diagram of TSV pinboards provided in an embodiment of the present invention；
Fig. 2 is the preparation method flow chart of another kind TSV pinboards provided in an embodiment of the present invention；
Fig. 3 a- Fig. 3 i are the preparation method flow chart of another TSV pinboard provided in an embodiment of the present invention；
Fig. 4 is a kind of TSV adapter plate structures schematic diagram provided in an embodiment of the present invention.
Embodiment
Further detailed description is done to the present invention with reference to specific embodiment, but embodiments of the present invention are not limited to
This.
Embodiment one
Fig. 1 is referred to, Fig. 1 is a kind of preparation method flow diagram of TSV pinboards provided in an embodiment of the present invention, bag
Include：
S101, choose substrate material；
S102, the upper surface of etched substrate material form multiple TSV and multiple isolated grooves respectively；
S103, filling isolated groove and TSV form isolated area and TSV areas respectively；
S104, prepare ESD protection device in the closed area that isolated area and substrate material are formed；
S105, the first end face for preparing in substrate material upper surface TSV areas and the interconnection line of ESD protection device；
The second end face until leaking out TSV areas is thinned in S106, the lower surface to substrate material；
S107, the second end face in TSV areas prepare metal salient point to complete the preparation of TSV pinboards.
Preferably, substrate material is Si materials, and crystal orientation is (100), (110) or (111), doping concentration for 1014~
1017cm-3, thickness are 150~250 μm.
Preferably, S102 can include：
S1021, using photoetching process form the etched features of TSV and isolated groove in the upper surface of substrate material；
S1022, utilize DRIE techniques, etched substrate material formation TSV and isolated groove；
Wherein, the depth of TSV and isolated groove is less than the thickness of substrate material.
Preferably, S103 can include：
S1031, thermal oxide TSV and isolated groove are with the inner wall of TSV and isolated groove formation oxide layer；
S1032, using wet-etching technology, etching oxidation layer is to complete the planarizing of TSV and isolated groove inner wall；
S1033, the filling figure using photoetching process formation isolated groove；
S1034, using CVD techniques, in isolated groove filling SiO2 forms isolated area；
S1035, the filling figure using photoetching process formation TSV；
S1036, using CVD techniques, polysilicon is filled in TSV, and be passed through impurity gas and carry out doping in situ and form TSV
Area.
Preferably, ESD protection device is diode, triode or MOS device.
Further, S104 can include：
S1041, using CMP process, the upper surface of substrate material is carried out smooth；
S1042, using photoetching process form P+ active area figures in the closed area that isolated area and substrate material are formed,
P+ injections are carried out using band glue ion implantation technology, photoresist is removed, forms the anode of diode；
S1043, using photoetching process form N+ active area figures in the closed area that isolated area and substrate material are formed,
N+ injections are carried out using band glue ion implantation technology, photoresist is removed, forms the cathode of diode；
S1044, carry out high annealing, activator impurity.
Preferably, S106 can include：
S1061, by the use of aiding in supporting item of the disk as substrate material upper surface；
S1062, using mechanical grinding reduction process be thinned substrate material lower surface, recycles CMP process, to lining
The lower surface of bottom material carries out planarizing process, the second end face until exposing TSV areas.
Further, S107 can include：
S1071, using sputtering technology, form laying and barrier layer in the lower surface of substrate material, existed using CVD techniques
The second end face in TSV areas forms tungsten plug；
S1072, deposition insulating layer, in the figure of the second end face photolithographic salient point in TSV areas, utilize electrochemical plating coppersmith
Skill deposits metal, and unnecessary metal is removed by chemical mechanical milling tech, and the second end face in TSV areas forms metal salient point；
S1073, remove auxiliary disk.
Preferably, metal is copper.
The preparation method of TSV pinboards provided in this embodiment, by processing ESD protection device on TSV pinboards
Part --- diode, enhances the antistatic effect of system in package, antistatic effect weak chip when solving three-dimensional stacked
The problem of influencing whether the antistatic effect of whole system after encapsulating；Meanwhile the present embodiment provides the diode week of TSV pinboards
The isolated area using up/down perforation is enclosed, there is less leakage current and parasitic capacitance.
Embodiment two
It refer to Fig. 2, Fig. 2 is the preparation method flow chart of another kind TSV pinboards provided in an embodiment of the present invention, this reality
Example is applied on the basis of above-described embodiment, to the present invention TSV pinboards preparation method be described in detail it is as follows.Specifically
Ground, includes the following steps：
S201, choose Si substrates；
S202, using etching technics prepare TSV and isolated groove on a si substrate；
S203, using CVD techniques, deposit SiO on a si substrate2Isolated groove is filled to form isolated area；
S204, using CVD techniques, depositing polysilicon material is filled TSV on a si substrate, while is passed through doping gas
Body carries out polysilicon doping in situ and forms TSV areas；
S205, the anode for preparing using ion implantation technology diode on a si substrate；
S206, the cathode for preparing using ion implantation technology diode on a si substrate；
S207, using electroplating technology, surface prepares copper interconnecting line on a si substrate；
S208, using CMP process, Si substrates are thinned, until leaking out TSV；
S209, in Si substrates lower surface form copper bump to complete the preparation of TSV pinboards using electric plating method.
Wherein, the reason for choosing Si substrates is that the thermodynamic property of Si is identical with chip, and switching is used as by the use of Si materials
Plate can reduce the bending of chip and die stress caused by the difference and residual stress of thermal coefficient of expansion to the full extent.
The crystal orientation of Si substrates can be (100), (110) or (111), in addition, the doping type of substrate can be N-type, or P
Type.
Preferably, S202 may include steps of：
S2021, utilize photoetching process etching TSV and isolated groove figure；
S2022, utilize DRIE techniques, etching Si substrates formation TSV and isolated groove.
Wherein, the quantity of TSV is one or more, and the depth of TSV is less than the thickness of Si substrates；The quantity of isolated groove is
Multiple, the depth of isolated groove is less than Si substrate thickness.
Specifically, S203 may include steps of：
S2031, thermal oxide TSV and isolated groove make the inner wall of blind hole form oxide layer；
S2032, etch using wet-etching technology the oxide layer of TSV and isolated groove inner wall to complete the flat of blind hole inner wall
Integralization.
Wherein, the projection that can prevent blind hole side wall by the planarizing of blind hole inner wall forms electric field concentrated area.
S2033, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete isolated groove and fill figure；
S2034, utilize CVD techniques, deposit SiO2Isolated groove is filled to form isolated area.
Wherein, isolated area runs through whole pinboard, effectively can be isolated device with substrate, reduce active area with
Parasitic capacitance between substrate.
Preferably, S204 may include steps of：
S2041, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and fill figure；
S2042, using CVD techniques, depositing polysilicon material be filled TSV, at the same be passed through impurity gas carry out it is former
Position doping, realizes the activation in situ of doped chemical, forms highly doped polysilicon TSV areas.
Wherein, filled by carrying out highly doped polysilicon in TSV areas, it is uniformly and highly doped that Impurity Distribution can be formed
The conductive material of concentration, is conducive to reduce the resistance of TSV.
Preferably, S205 may include steps of：
S2051, using CMP process, planarizing process is carried out to Si substrate surfaces；
S2052, the photoetching P between two adjacent isolated areas+Active area, P is carried out using the mode with glue ion implanting+
Injection, removes photoresist, forms the anode of diode.
Preferably, S206 may include steps of：
S2061, the photoetching N between two adjacent isolated areas+Active area, N is carried out using the mode with glue ion implanting+
Injection, removes photoresist, forms the cathode of diode；
S2062, carry out high annealing, makes the impurity activation of ion implanting.
Preferably, S207 may include steps of：
S2071, utilize sputtering or CVD techniques, on a si substrate surface formation laying and barrier layer, and utilize CVD works
The first end in Yi TSV areas and the anode and cathode of diode form tungsten plug；
S2072, deposition insulating layer, photoetching copper-connection figure, deposits copper using electrochemical plating process for copper, passes through chemical machinery
Grinding technics removes unnecessary copper, forms the copper interconnecting line that the first end in TSV areas is concatenated with diode.
Further, when preparing copper interconnecting line, inductance is made it have around curl using metal interconnecting wires
Characteristic to be more particularly for the electrostatic protection of RF IC.
Preferably, S208 may include steps of：
S2081, by the use of high molecular material as intermediate layer, by Si substrate top surfaces and auxiliary wafer bonding, pass through auxiliary
Disk supports Si substrate top surfaces；
S2082, using mechanical grinding reduction process be thinned Si substrates lower surface, and until reducing to, to be slightly larger than TSV deep
The thickness of degree；
S2083, using CMP process to Si substrates lower surface carry out smooth, the second end until exposing TSV areas.
Preferably, S209 may include steps of：
S2091, using sputtering or CVD techniques form laying and barrier layer in Si substrates lower surface, is existed using CVD techniques
The second end in TSV areas forms tungsten plug；
S2092, deposition insulating layer, the second end photoetching copper bump figure in TSV areas, is deposited using electrochemical plating process for copper
Copper, unnecessary copper is removed by chemical mechanical milling tech, and the second end in TSV areas forms copper bump；
S2093, remove the auxiliary disk being bonded temporarily using the technique of heated mechanical.
The preparation method of TSV pinboards provided in this embodiment, it is mutually compatible with existing process, be conducive to industrialization；Using
The diode component of transversary, parasitic capacitance is small, RF IC is influenced small.
Embodiment three
The present embodiment is on the basis of above-described embodiment, to design parameter in the preparation method of the TSV pinboards of the present invention
Citing is described as follows.Specifically, Fig. 3 a- Fig. 3 i, Fig. 3 a- Fig. 3 i are refer to for another TSV provided in an embodiment of the present invention to turn
The preparation method flow chart of fishplate bar,
S301, choose Si substrates 301, as shown in Figure 3a；
Preferably, the doping concentration of Si substrates is 1014~1017cm-3, thickness is 150~250 μm.
S302, as shown in Figure 3b；Prepare two TSV302 and three isolated grooves on a si substrate using etching technics
303, it may include steps of：
S3021, at a temperature of 1050 DEG C~1100 DEG C, utilize thermal oxidation technology on a si substrate surface grow one layer
The SiO of 800nm~1000nm2Layer；
S3022, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and isolated groove etched features；
S3023, etch Si substrates, the TSV and isolated groove of 40~80 μm of depths of formation using DRIE techniques；
S3024, using CMP process, remove the SiO on Si substrates2, substrate surface is planarized.
S303, as shown in Figure 3c；Using CVD techniques, SiO is deposited on a si substrate2304 pairs of isolated grooves are filled shape
Into isolated area, specifically may include steps of：
S3031, at a temperature of 1050 DEG C~1100 DEG C, the inner wall of thermal oxide TSV and isolated groove forms thickness and is
The oxide layer of 200nm~300nm；
S3032, using wet-etching technology, etch the oxide layer of inner wall of TSV and isolated groove to complete TSV and isolation
The planarizing of trench wall.To prevent the projection of TSV and isolated groove side wall from forming electric field concentrated area；
S3033, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete isolated groove and fill figure；
S3034, at a temperature of 690 DEG C~710 DEG C, utilize low-pressure chemical vapor deposition (Low Pressure
Chemical Vapor Deposition, LPCVD) technique, deposit SiO2Isolated groove is filled, forms isolated area；Can
With understanding, the SiO2Material is mainly used for isolating, it can be substituted by other materials such as undoped polycrystalline silicons；
S3035, using CMP process, substrate surface is planarized.
S304, as shown in Figure 3d；Using CVD techniques, depositing polysilicon material 305 is filled TSV on a si substrate,
Impurity gas is passed through at the same time TSV areas are formed to polysilicon progress doping in situ, specifically may include steps of：
S3041, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and fill figure；
S3042, at a temperature of 600 DEG C~620 DEG C, TSV is filled using CVD technique depositing polysilicon materials,
Impurity gas is passed through at the same time and carries out doping in situ, and realizes the activation in situ of doped chemical, forms highly doped polysilicon filling.
Can so be formed when being filled to TSV Impurity Distribution uniformly and high-dopant concentration conductive material filling, beneficial to reduce TSV
Resistance.Polysilicon doping concentration preferably 2 × 1021cm-3, the preferred phosphorus of impurity.
S305, as shown in Figure 3 e；Using ion implantation technology, the anode 306 of diode is formed on a si substrate, specifically may be used
To include the following steps：
S3051, using CMP process planarize substrate surface；
S3052, the photoetching P between two adjacent isolated areas+Active area, P is carried out using band glue ion implantation technology+Note
Enter, remove photoresist, form the anode of diode.Doping concentration preferably 5 × 1018cm-3, the preferred boron of impurity.
S306, as illustrated in figure 3f；The cathode 307 of diode is formed using ion implantation technology on a si substrate, specifically may be used
To include the following steps：
S3061, the photoetching N between two adjacent isolated areas+Active area, N is carried out using band glue ion implantation technology+Note
Enter, remove photoresist, form the cathode of diode.Doping concentration preferably 5 × 1018cm-3, the preferred phosphorus of impurity；
S3062, by substrate at a temperature of 950~1100 DEG C, anneal 15~120s, carry out impurity activation.
S307, as shown in figure 3g；Using electroplating technology, surface forms copper interconnecting line 308 on a si substrate, can specifically wrap
Include following steps：
S3071, utilize plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor
Deposition, PECVD) technique, deposit SiO in substrate surface2Layer；
S3072, in the first end in TSV areas and the anode of diode and cathode, using photoetching process, pass through gluing, light
The techniques such as quarter, development complete contact hole graph；
S3073, using CVD techniques, in the first end in TSV areas and the anode of diode and cathode deposition Ti films, TiN film
With tungsten to form tungsten plug 309；
S3074, using CMP process planarize substrate surface；
S3075, deposit SiO2Insulating layer, photoetching copper-connection figure, copper, passing through are deposited using the method for Cu electroplating
The method for learning mechanical lapping removes unnecessary copper, and the first end for forming TSV areas concatenates copper interconnecting line with diode；
S3076, using CMP process planarize substrate surface；
S3077, using pecvd process, deposit SiO in substrate surface2Layer；
S308, as illustrated in figure 3h；Si substrates are thinned using CMP process, TSV areas is leaked out, specifically may be used
To include the following steps：
S3081, by the use of high molecular material as intermediate layer, by Si substrate top surfaces and auxiliary wafer bonding, pass through auxiliary
Being thinned for Si substrates is completed in the support of disk；
S3082, using mechanical grinding reduction process be thinned Si substrates lower surface, is slightly larger than TSV areas until reducing to
The thickness of depth, preferably greater than 10 μm of TSV depth；
S3083, using CMP process to Si substrates lower surface carry out it is smooth, until exposing TSV areas；
S309, as shown in figure 3i；Copper bump 310 is formed using electric plating method in Si substrates lower surface, can specifically be wrapped
Include following steps：
S3091, using pecvd process, deposit SiO in substrate lower surface2Layer；
S3092, the second end in TSV areas, using photoetching process, contact hole is completed by techniques such as gluing, photoetching, developments
Figure；
S3093, using CVD techniques, in second end face deposit Ti films, TiN film and the tungsten in TSV areas to form tungsten plug；
S3094, using CMP process planarize substrate surface；
S3095, deposit SiO2Insulating layer, the second end photoetching copper bump figure in TSV areas, utilizes electrochemical plating process for copper
Copper is deposited, unnecessary copper is removed by chemical mechanical milling tech, etches SiO2Layer, the second end in TSV areas form copper bump；
S3096, remove the auxiliary disk being bonded temporarily using the method for heated mechanical.
The preparation method of TSV pinboards provided in this embodiment, using diode component periphery by SiO2Insulating layer surrounds
Technique, the parasitic capacitance between active area and substrate can be effectively reduced.The present invention passes through on the basis of technological feasibility is considered
The TSV holes of optimal design-aside certain length and the doping concentration using given range, and consider the electric current handling capacity of device, subtract
Small parasitic capacitance and resistance, and a degree of tuning is carried out to the parasitic capacitance of device using the inductance that TSV holes introduce,
The working range of esd protection circuit is expanded while improving system in package anti-ESD abilities.
Example IV
Fig. 4 is refer to, Fig. 4 is a kind of TSV adapter plate structures schematic diagram provided in an embodiment of the present invention；The TSV pinboards
It is made using the above-mentioned preparation process as shown in Fig. 3 a- Fig. 3 i.
Specifically, TSV pinboards include：Si substrates 40, horizontal the first TSV areas 401 being set in turn in Si substrates, the
One isolated area 402, the first transverse diode 403, the second isolated area 404, the second transverse diode 405, the 3rd isolated area 406 with
And the 2nd TSV areas 407.
Further, the first TSV areas 401, the first isolated area 402, the second isolated area 404, the 3rd isolated area 406 and
Two TSV areas, the 407 equal whole Si substrates of up/down perforation.
Preferably, the material of 407 interior filling of the first TSV areas 401 and the 2nd TSV areas is polysilicon；First isolated area 402,
The material of filling is SiO in second isolated area 404 and the 3rd isolated area 4062。
Wherein, the first TSV areas 401, the first transverse diode 403, the second transverse diode 405 and the 2nd TSV areas 407
It is connected in series successively；
Specifically, the first end in the first TSV areas 401 and anode, the first transverse diode of the first transverse diode 403
The anode of 403 cathode and the second transverse diode 405, the of the cathode of the second transverse diode 405 and the 2nd TSV areas 407
One end is connected by copper interconnecting line 408 respectively.
Wherein, the first end in the first TSV areas 401 and and the first end in the 2nd TSV areas 407 on be disposed with tungsten plug and
Copper interconnecting line；Tungsten plug and copper bump are disposed with the second end in the first TSV areas 401 and the second end in the 2nd TSV areas 407
409。
Further, TSV pinboards further include the SiO for being arranged at Si substrate top surfaces and lower surface2Insulating layer 410.
Further, the first isolated area 402, the second isolated area 404 and the 3rd isolated area 406 are used to be formed in Si substrates
Area of isolation is to isolate the first transverse diode 403 and the second transverse diode 405.
TSV pinboards provided in this embodiment, it is simple in structure, very big ESD electric currents can be born and be unlikely to make partly to lead
Body device heating fails；Using the higher heat-sinking capability of pinboard, the high current handling capacity in device work is improved；
The isolated groove of up/down perforation is set around the diode of TSV pinboards, there is less leakage current and parasitic capacitance.
Above content is that a further detailed description of the present invention in conjunction with specific preferred embodiments, it is impossible to is assert
The specific implementation of the present invention is confined to these explanations.For example, the multiple isolated areas referred in the present invention are only according to this hair
The device architecture sectional view of bright offer illustrates, wherein, multiple isolated areas can also be such as ring bodies in some entirety
The sectional view Part I and Part II that show, for general technical staff of the technical field of the invention, no
These explanations should be confined to, without departing from the inventive concept of the premise, some simple deduction or replace can also be made, all should
When being considered as belonging to protection scope of the present invention.
Claims (10)
- A kind of 1. preparation method of TSV pinboards, it is characterised in that including：S101, choose substrate material；S102, the upper surface of the etching substrate material form multiple TSV and multiple isolated grooves respectively；S103, the filling isolated groove and the TSV form isolated area and TSV areas respectively；S104, prepare ESD protection device in the closed area that the isolated area and the substrate material are formed；S105, the first end face for preparing in the substrate material upper surface TSV areas and the interconnection of the ESD protection device Line；The second end face until leaking out the TSV areas is thinned in S106, the lower surface to the substrate material；S107, the second end face in the TSV areas prepare metal salient point to complete the preparation of the TSV pinboards.
- 2. preparation method according to claim 1, it is characterised in that the substrate material is Si materials, and doping concentration is 1014~1017cm-3, thickness is 150~250 μm.
- 3. preparation method according to claim 1, it is characterised in that S102 includes：S1021, the etching figure that the TSV and the isolated groove are formed using photoetching process in the upper surface of the substrate material Shape；S1022, using DRIE techniques, etch the substrate material and form the TSV and the isolated groove；The TSV and institute The depth for stating isolated groove is less than the thickness of the substrate material.
- 4. preparation method according to claim 1, it is characterised in that S103 includes：TSV described in S1031, thermal oxide and the isolated groove are aoxidized with being formed in the inner wall of the TSV and the isolated groove Layer；S1032, using wet-etching technology, etch the oxide layer to complete the flat of the TSV and the isolated groove inner wall Integralization；S1033, the filling figure for forming using photoetching process the isolated groove；S1034, using CVD techniques, fill SiO in the isolated groove2Form the isolated area；S1035, the filling figure for forming using photoetching process the TSV；S1036, using CVD techniques, polysilicon is filled in the TSV, and be passed through impurity gas and carry out doping in situ and form institute State TSV areas.
- 5. preparation method according to claim 1, it is characterised in that the ESD protection device is diode.
- 6. preparation method according to claim 5, it is characterised in that S104 includes：S1041, using CMP process, the upper surface of the substrate material is carried out smooth；S1042, using photoetching process in the closed area that the isolated area and the substrate material are formed photoetching P+Active area figure Shape, P is carried out using band glue ion implantation technology+Injection, removes photoresist, forms the anode of the diode；S1043, using photoetching process in the closed area that the isolated area and the substrate material are formed photoetching N+Active area figure Shape, N is carried out using band glue ion implantation technology+Injection, removes photoresist, forms the cathode of the diode；S1044, carry out high annealing, activator impurity.
- 7. preparation method according to claim 1, it is characterised in that S106 includes：S1061, by the use of aiding in supporting item of the disk as the substrate material upper surface；S1062, using mechanical grinding reduction process be thinned the substrate material lower surface, CMP process is recycled, to institute The lower surface for stating substrate material carries out planarizing process, the second end face until exposing the TSV areas.
- 8. preparation method according to claim 7, it is characterised in that S107 includes：S1071, using sputtering technology, form laying and barrier layer in the lower surface of the substrate material, existed using CVD techniques The second end face in the TSV areas forms tungsten plug；S1072, deposition insulating layer, the figure of metal salient point, utilizes electrochemical plating described in the second end face photoetching in the TSV areas Process for copper deposits metal, and unnecessary metal is removed by chemical mechanical milling tech, and the second end face in the TSV areas forms institute State metal salient point；S1073, remove the auxiliary disk.
- 9. preparation method according to claim 8, it is characterised in that the metal is copper.
- 10. a kind of TSV pinboards, it is characterised in that the TSV pinboards are by claim 1~9 any one of them method system It is standby to be formed.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109638011A (en) * | 2018-11-30 | 2019-04-16 | 昆山锐芯微电子有限公司 | The electrostatic protection structure and imaging sensor of imaging sensor |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841651A (en) * | 2005-03-29 | 2006-10-04 | 三洋电机株式会社 | Semiconductor device manufacturing method |
| CN101540320A (en) * | 2009-04-21 | 2009-09-23 | 上海宏力半导体制造有限公司 | Static discharge protection diode |
| CN102362349A (en) * | 2009-03-26 | 2012-02-22 | 国际商业机器公司 | Esd network circuit with a through wafer via structure and a method of manufacture |
| CN102598254A (en) * | 2009-10-23 | 2012-07-18 | 新思科技有限公司 | ESD/antenna diodes for through-silicon vias |
| US20130119502A1 (en) * | 2011-11-16 | 2013-05-16 | Analog Devices, Inc. | Electrical overstress protection using through-silicon-via (tsv) |
| US20140203367A1 (en) * | 2013-01-21 | 2014-07-24 | United Microelectronics Corp. | Transistor Structure for Electrostatic Discharge Protection |
| US20150048497A1 (en) * | 2013-08-16 | 2015-02-19 | Qualcomm Incorporated | Interposer with electrostatic discharge protection |
| CN105190888A (en) * | 2013-05-06 | 2015-12-23 | 高通股份有限公司 | Electrostatic discharge diode |
| CN106816684A (en) * | 2016-12-20 | 2017-06-09 | 西安科锐盛创新科技有限公司 | For the Ge base plasma pin diode preparation methods of restructural multilayer holographic antenna |
-
2017
- 2017-12-15 CN CN201711349187.6A patent/CN107946240A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1841651A (en) * | 2005-03-29 | 2006-10-04 | 三洋电机株式会社 | Semiconductor device manufacturing method |
| CN102362349A (en) * | 2009-03-26 | 2012-02-22 | 国际商业机器公司 | Esd network circuit with a through wafer via structure and a method of manufacture |
| CN101540320A (en) * | 2009-04-21 | 2009-09-23 | 上海宏力半导体制造有限公司 | Static discharge protection diode |
| CN102598254A (en) * | 2009-10-23 | 2012-07-18 | 新思科技有限公司 | ESD/antenna diodes for through-silicon vias |
| US20130119502A1 (en) * | 2011-11-16 | 2013-05-16 | Analog Devices, Inc. | Electrical overstress protection using through-silicon-via (tsv) |
| US20140203367A1 (en) * | 2013-01-21 | 2014-07-24 | United Microelectronics Corp. | Transistor Structure for Electrostatic Discharge Protection |
| CN105190888A (en) * | 2013-05-06 | 2015-12-23 | 高通股份有限公司 | Electrostatic discharge diode |
| US20150048497A1 (en) * | 2013-08-16 | 2015-02-19 | Qualcomm Incorporated | Interposer with electrostatic discharge protection |
| CN106816684A (en) * | 2016-12-20 | 2017-06-09 | 西安科锐盛创新科技有限公司 | For the Ge base plasma pin diode preparation methods of restructural multilayer holographic antenna |
Non-Patent Citations (1)
| Title |
|---|
| 菲利普•加罗: "《3D集成手册 3D集成电路技术与应用》", 31 May 2017 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109638011A (en) * | 2018-11-30 | 2019-04-16 | 昆山锐芯微电子有限公司 | The electrostatic protection structure and imaging sensor of imaging sensor |
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