CN208256668U

CN208256668U - Anti-static device for system in package

Info

Publication number: CN208256668U
Application number: CN201721773194.4U
Authority: CN
Inventors: 张捷
Original assignee: Xian Cresun Innovation Technology Co Ltd
Current assignee: Xian Cresun Innovation Technology Co Ltd
Priority date: 2017-12-15
Filing date: 2017-12-15
Publication date: 2018-12-18
Anticipated expiration: 2027-12-15

Abstract

The utility model relates to a kind of anti-static devices for system in package, comprising: Si substrate (101), SCR pipe (102), isolated area (103), the area TSV (104), interconnection line (105) and metal salient point (106)；Wherein, the isolated area (103) and the area TSV (104) the Si substrate (101) up and down；The SCR pipe (102) is set in the Si substrate (101)；The isolated area (103) is set to the two sides of the SCR pipe (102)；The area TSV (104) is set to by the two sides of SCR pipe (102) and the isolated area (103) forming region；The interconnection line (105) is set on the Si substrate (101), for connecting the first end face and SCR pipe (102) of the area TSV (104)；The metal salient point (106) is set in the first end face of the area TSV (104).The utility model solves the problems, such as that IC system grade encapsulation antistatic effect is weak, enhances the antistatic effect of IC system grade encapsulation by the way that SCR pipe is arranged on through silicon via pinboard as anti-static device.

Description

Anti-static device for system in package

Technical field

The utility model category semiconductor integrated circuit technology field, in particular to a kind of antistatic for system in package Device.

Background technique

Static discharge (Electro-Static Discharge, abbreviation ESD) event is common in daily life, and some Larger electric discharge can detect by human sensory, smaller electric discharge not by human sensory notice because of strength of discharge with put The ratio of the surface area of electricity is very small.ESD is that device and its integrated circuit (Integrated Circuit, abbreviation IC) fail Principal element works as people this is because there may be electrostatic in manufacture, encapsulation, test and use process for device or product Under conditions of not knowing situation, these objects is made to contact with each other, form discharge path, so as to cause product function failure, or forever Long property is damaged.It follows that ESD protection problem is always one of important topic of IC design field.With integrated electricity Road scale is continuously increased, and the difficulty of ESD design protection is also increasing.

With computer, communication, the development of automotive electronics, aerospace industry and other consumer system regions, half-and-half The requirement of the size and power consumption of conductor chip is continuously improved, needs smaller, thinner and lighter, highly reliable, multi-functional, low-power consumption With the chip of low cost, three-dimensional packaging technology is come into being in this background.It has been reached in the packaging density of two-dimensional package technology In the case where the limit, the advantage of more highdensity three-dimensional (3D) encapsulation technology is self-evident.

Through silicon via (Through-Silicon Via, abbreviation TSV) technology is that stacked chips realize interconnection in 3D integrated circuit The new technical solution of one kind.Due to TSV technology can make chip density that three-dimensional stacks is maximum, between chip Interconnection line is most short, outer dimension is minimum, this 3D chip laminate can be effectively realized, produce that structure is more complicated, performance More powerful, more cost-efficient chip becomes most noticeable a kind of technology in current Electronic Encapsulating Technology.

Pinboard typically refers to the functional layer of interconnection and pin redistribution between chip and package substrate.Pinboard can be with Intensive I/O lead is redistributed, realizes the high density interconnection of multi-chip, it is macro with grade to become nanometer-grade IC It sees electric signal between the world and connects one of most effective means.When realizing that multifunction chip is integrated using pinboard, not same core The antistatic effect of piece is different, and the weak chip of antistatic effect influences whether that resisting for whole system after encapsulation is quiet when three-dimensional stacked Electric energy power；Therefore the system in package antistatic effect for how improving the 3D-IC based on TSV technique becomes semicon industry urgently It solves the problems, such as.

Utility model content

In order to improve the antistatic effect of 3D integrated circuit, the utility model provides a kind of for the anti-of system in package Electrostatic equipment；The technical problems to be solved in the utility model is achieved through the following technical solutions:

The embodiments of the present invention provide a kind of anti-static device for system in package, comprising: Si substrate 101, thyristor be called silicon-controlled (Silicon Controlled Rectifier, SCR) 102, isolated area 103, the area TSV 104, Interconnection line 105 and metal salient point 106；Wherein,

Isolated area 103 and the area TSV 104 Si substrate 101 up and down；SCR pipe 102 is set in Si substrate 101；Isolation Area 103 is set to the two sides of SCR pipe 102；The area TSV 104 is set to by the two sides of 103 forming region of SCR pipe 102 and isolated area； Interconnection line 105 is set on Si substrate 101 for connecting the first end face and SCR pipe 102 in the area TSV 104；Metal salient point 106 is set It is placed in the first end face in the area TSV 104.

In one embodiment of the utility model, SCR pipe includes: N well region and p-well region；Wherein, N well region includes that N trap connects Touch area 2021 and anode 2022；P-well region includes cathode 2023 and p-well contact zone 2024.

In one embodiment of the utility model, the first end face and SCR pipe 102 in the area TSV 104 and interconnection line 105 it Between be provided with tungsten plug.

In one embodiment of the utility model, anti-static device further includes the SiO for being set to 101 surface of Si substrate₂ Insulating layer.

In one embodiment of the utility model, it is provided between the second end face and metal salient point 106 in the area TSV 104 Tungsten plug.

In one embodiment of the utility model, the material of interconnection line 105 and metal salient point 106 is copper.

Compared with prior art, the utility model has the following beneficial effects:

1, the utility model on TSV pinboard by processing ESD protection device --- and SCR pipe forms system in package Anti-static device enhances the antistatic effect of laminate packaging chip；

2, the utility model is managed by the way that SCR is arranged on anti-static device, using the higher heat-sinking capability of pinboard, is improved High current handling capacity in device work；

3, have smaller around the SCR pipe of anti-static device provided by the utility model using isolated area up and down Leakage current and parasitic capacitance.

Detailed description of the invention

It, below will be to required in embodiment description in order to illustrate more clearly of the technical solution of the utility model embodiment The attached drawing used is briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the utility model Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings Obtain other attached drawings.

Fig. 1 is a kind of anti-static device structural schematic diagram for system in package provided by the embodiment of the utility model；

Fig. 2 is a kind of preparation method stream of the anti-static device for system in package provided by the embodiment of the utility model Journey schematic diagram；

Fig. 3 a- Fig. 3 i is the preparation method flow chart of another anti-static device provided by the embodiment of the utility model.

Specific embodiment

Further detailed description, but the embodiment party of the utility model are done to the utility model combined with specific embodiments below Formula is without being limited thereto.

Embodiment one

Referring to Figure 1, Fig. 1 is a kind of anti-static device knot for system in package provided by the embodiment of the utility model Structure schematic diagram, comprising:

Si substrate 101, SCR pipe 102, isolated area 103, the area TSV 104, interconnection line 105 and metal salient point 106；Wherein,

Further, SCR pipe includes: N well region and p-well region；Wherein, N well region includes N trap contact zone 2021 and anode 2022；P-well region includes cathode 2023 and p-well contact zone 2024.

Preferably, the impurity of N well region is phosphorus, doping concentration preferably 1 × 10¹⁷cm^-3；The impurity of p-well region is Boron, doping concentration preferably 1 × 10¹⁸cm^-3。

Preferably, the doping type of Si substrate 101 is p-type, and doping concentration is 1 × 10¹⁴cm^-3, with a thickness of 80~120 μm.

Preferably, tungsten plug is provided between the first end face in the area TSV 104 and SCR pipe 102 and interconnection line 105.

Specifically, anti-static device further includes the SiO for being set to 101 upper and lower surface of Si substrate₂Insulating layer.

Preferably, the packing material in the area TSV 104 is polysilicon, and the doping concentration of polysilicon is 2 × 10²¹cm^-3, doping Material is phosphorus.

Specifically, tungsten plug is provided between the second end face in the area TSV 104 and metal salient point 106.

Preferably, the material of interconnection line 105 and metal salient point 106 is copper.

Preferably, isolated area 103 and the depth in the area TSV 104 are 80~120 μm.

Anti-static device provided in this embodiment is managed by the way that ESD protection device SCR is arranged on anti-static device, is enhanced The antistatic effect of laminate packaging chip, the weak chip of antistatic effect influences whether entire after encapsulating when solving three-dimensional stacked The problem of antistatic effect of system；Meanwhile the present embodiment provides anti-static devices be arranged around SCR pipe up and down every From area, there is lesser leakage current and parasitic capacitance.

Embodiment two

Referring to figure 2., Fig. 2 is a kind of anti-static device for system in package provided by the embodiment of the utility model Preparation method flow diagram, the present embodiment on the basis of the above embodiments, to the system of the anti-static device of the utility model Preparation Method is described in detail as follows.Specifically, include the following steps:

S101, Si substrate is chosen；

S102, etching Si substrate are respectively formed the hole TSV and isolated groove；

S103, filling isolated groove and TSV are respectively formed multiple isolated areas and the area TSV；

S104, the N well region and p-well region that SCR pipe is prepared between two isolated areas；

S105, N trap contact zone, cathode, p-well contact zone and the anode for preparing SCR pipe；

S106, interconnection line is formed between the first end face and SCR pipe in the area TSV；

S107, the second end face in the area TSV prepare metal salient point to complete the preparation of anti-static device.

Preferably, S102 may include:

S1021, using photoetching process, form the etched features of TSV and isolated groove in the upper surface of Si substrate；

S1022, deep reaction ion etching (Deep Reactive Ion Etching, abbreviation DRIE) technique, quarter are utilized It loses Si substrate and forms TSV and isolated groove；

Wherein, the depth of TSV and isolated groove is less than the thickness of Si substrate.

Preferably, S103 can include:

S1031, thermal oxide TSV and isolated groove are to form oxide layer in the inner wall of TSV and isolated groove；

S1032, using wet-etching technology, etching oxidation layer is to complete the planarizing of TSV and isolated groove inner wall；

S1033, the filling figure that isolated groove is formed using photoetching process；

S1034, using chemical vapor deposition (Chemical Vapor Deposition, abbreviation CVD) technique, be isolated SiO is filled in groove₂Form isolated area；

S1035, the filling figure that TSV is formed using photoetching process；

S1036, using CVD technique, polycrystalline silicon material is filled in TSV, and be passed through impurity gas and carry out doping shape in situ At the area TSV.

Preferably, S104 may include:

S1041, masking layer is prepared using CVD technique；

S1042, between two isolated areas photoetching SCR pipe N well region figure, using ion implantation technology carry out N⁺Note Enter, remove photoresist, forms the N well region of SCR pipe；

S1043, between two isolated areas photoetching SCR pipe p-well region figure, using ion implantation technology carry out P⁺Note Enter, remove photoresist, forms the p-well region of SCR pipe.

Preferably, S105 may include:

S1051, photoetching N trap contact zone and cathode pattern carry out N using ion implantation technology⁺Injection removes photoresist, Form the N trap contact zone and cathode of SCR pipe；

S1052, photoetching p-well contact zone and cathode pattern carry out P using ion implantation technology⁺Injection removes photoresist, Form the p-well contact zone and anode of SCR pipe.

Specifically, before S107 further include:

X1, using auxiliary disk as the supporting element of Si upper surface of substrate；

X2, Si substrate lower surface is carried out using mechanical grinding reduction process it is thinned；

X3, using chemically mechanical polishing (Chemical Mechanical Polishing, abbreviation CMP) technique, Si is served as a contrast The lower surface at bottom carries out planarizing process, the second end face until exposing the area TSV.

Preferably, S107 may include:

S1071, using sputtering technology, form laying and barrier layer in the lower surface of Si substrate, existed using CVD technique The second end face in the area TSV forms tungsten plug；

S1072, deposition insulating layer utilize electrochemical plating coppersmith in the figure of the second end face photolithographic salient point in the area TSV Skill deposits metal, and extra metal is removed by chemical mechanical milling tech, and the second end face in the area TSV forms metal salient point；

S1073, auxiliary disk is removed.

Preferably, the doping concentration of Si substrate is 1 × 10¹⁴cm^-3, with a thickness of 150~250 μm.

Preferably, the depth of the area TSV and isolated area is 80~120 μm.

The preparation method of anti-static device provided in this embodiment can realize in existing TSV technique platform, therefore It is compatible strong, it is applied widely；Maintenance voltage using SCR pipe is low, is able to bear very high ESD electric current, naturally has high ESD robustness feature prepares SCR pipe, the antistatic energy of integrated circuit when greatly improving system in package in pinboard Power.

Embodiment three

The present embodiment on the basis of the above embodiments, to specific in the preparation method of the anti-static device of the utility model Parameter citing is described as follows.Specifically, a- Fig. 3 i, Fig. 3 a- Fig. 3 i are provided by the embodiment of the utility model another referring to figure 3. The preparation method flow chart of kind anti-static device.

S201, as shown in Figure 3a, selection Si substrate 201；

Preferably, the doping type of Si substrate is p-type, and doping concentration is 1 × 10¹⁴, with a thickness of 150~250 μm.

S202, as shown in Figure 3b, prepare TSV202 and isolated groove 203 on a si substrate using etching technics, can wrap Include following steps:

S2021,1050 DEG C~1100 DEG C at a temperature of, utilize thermal oxidation technology on a si substrate surface grow one layer The SiO of 800nm~1000nm₂Layer；

S2022, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and isolated groove etched features；

S2023, Si substrate is etched using DRIE technique, forms TSV and isolated groove that depth is 80~120 μm；

S2024, using CMP process, remove the SiO on Si substrate₂, substrate surface is planarized.

Preferably, two isolated grooves are located between two TSV.

S203, as shown in Figure 3c；Using CVD technique, SiO is deposited on a si substrate₂Isolated groove is filled to be formed Isolated area can specifically include following steps:

S2031,1050 DEG C~1100 DEG C at a temperature of, the inner wall of thermal oxide TSV and isolated groove formed with a thickness of The oxide layer of 200nm~300nm；

S2032, using wet-etching technology, etch the oxide layer of the inner wall of TSV and isolated groove to complete TSV and isolation The planarizing of trench wall.To prevent the protrusion of TSV and isolated groove side wall from forming electric field concentrated area；

S2033, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete isolated groove and fill figure；

S2034,690 DEG C~710 DEG C at a temperature of, utilize low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD) technique, deposit SiO₂Isolated groove is filled, isolated area is formed；It can With understanding, the SiO₂Material is mainly used for isolating, and can be substituted by other materials such as undoped polycrystalline silicons；

S2035, using CMP process, substrate surface is planarized.

S204, as shown in Figure 3d；Using CVD technique, depositing polysilicon material is filled TSV on a si substrate, together When is passed through impurity gas, and to polysilicon progress, doping forms the area TSV in situ, can specifically include following steps:

S2041, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and fill figure；

S2042,600 DEG C~620 DEG C at a temperature of, TSV is filled using CVD technique depositing polysilicon material, It is passed through impurity gas simultaneously and carries out doping in situ, and realizes the activation in situ of doped chemical, forms highly doped polysilicon filling. Impurity Distribution can be formed when filling to TSV so uniformly and the conductive material of high-dopant concentration is filled, is conducive to reduce TSV Resistance.Polysilicon doping concentration preferably 2 × 10²¹cm^-3, the preferred phosphorus of impurity；

S2043, substrate surface is planarized using CMP process.

S205, as shown in Figure 3 e；The N well region 204 and p-well region 205 of SCR pipe processed between two isolated areas, specifically can be with Include the following steps:

S2051,1050 DEG C~1100 DEG C at a temperature of, using thermal oxidation technology, form SiO in Si substrate surface₂It is slow Rush layer；

S2052,700 DEG C~800 DEG C at a temperature of, using LPCVD technique, deposit Si in Si substrate surface₃N₄Layer；

S2053, photoetching N well region carry out phosphorus injection using band glue ion implantation technology, remove photoresist, form SCR pipe N well region, doping concentration preferably 1 × 10¹⁷cm^-3；

S2054, by substrate at a temperature of 950 DEG C, anneal 2.5h, carry out N trap propulsion；

S2055, using wet-etching technology, remove the Si of substrate surface₃N₄Layer；

S2056, photoetching p-well region carry out boron injection using band glue ion implantation technology, remove photoresist, form SCR pipe P-well region, doping concentration preferably 1 × 10¹⁸cm^-3；

S2057, by substrate at a temperature of 950 DEG C, anneal 2.5h, carry out the propulsion of p-well.

S206, as illustrated in figure 3f；Prepare N trap contact zone 206, cathode 207, anode 208 and the p-well contact zone of SCR pipe 209, it can specifically include following steps:

S2061, photoetching N trap contact zone and cathode carry out N using band glue ion implantation technology⁺Injection removes photoresist, Form the N trap contact zone and N of SCR pipe⁺Cathode.Doping concentration preferably 1.5 × 10²⁰cm^-3, the preferred phosphorus of impurity；

S2062, photoetching p-well contact zone and cathode carry out P using band glue ion implantation technology⁺Injection removes photoresist, Form the p-well contact zone and P of SCR pipe⁺Anode.Doping concentration preferably 1.5 × 10²⁰cm^-3, the preferred boron of impurity；

S2063, by substrate at a temperature of 950~1100 DEG C, anneal 15~120s, carry out impurity activation.

S207, as shown in figure 3g；Using electroplating technology, surface forms copper interconnecting line 210 on a si substrate, specifically can wrap Include following steps:

S2071, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor is utilized Deposition, PECVD) technique, SiO is deposited in substrate surface₂Layer；

S2072, in the first end in the area TSV and N trap contact zone, cathode, p-well contact zone and the anode of SCR pipe, utilize light Carving technology completes contact hole graph by techniques such as gluing, photoetching, developments；

S2073, using CVD technique, in the first end in the area TSV and N trap contact zone, cathode, the p-well contact zone of SCR pipe With anode deposit Ti film, TiN film and tungsten to form tungsten plug；

S2074, substrate surface is planarized using CMP process；

S2075, deposit SiO₂Insulating layer, photoetching copper-connection figure deposit copper, passing through using the method for Cu electroplating The method for learning mechanical lapping removes extra copper, and the first end for forming the area TSV concatenates copper interconnecting line with metal-oxide-semiconductor；

S2076, substrate surface is planarized using CMP process.

Further, it when preparing copper interconnecting line, surrounds spiral using metal interconnecting wires and makes it have inductance Characteristic to be more particularly for the electrostatic protection of RF IC.

S208, as illustrated in figure 3h；Si substrate is carried out using CMP process it is thinned, leak out the area TSV, specifically may be used To include the following steps:

S2081, Si upper surface of substrate and auxiliary wafer bonding are passed through into auxiliary using high molecular material as middle layer Being thinned for Si substrate is completed in the support of disk；

S2082, Si substrate lower surface is carried out using mechanical grinding reduction process it is thinned, until reduce to be slightly larger than the area TSV The thickness of depth, preferably greater than 10 μm of TSV depth；

S2083, using CMP process to Si substrate lower surface carry out it is smooth, until expose the area TSV；

S209, as shown in figure 3i；Copper bump 211 is formed using the method for electro-coppering in Si substrate lower surface, it specifically can be with Include the following steps:

S2091, using pecvd process, deposit SiO in substrate lower surface₂Layer；

S2092, the second end in the area TSV complete contact hole by techniques such as gluing, photoetching, developments using photoetching process Figure；

S2093, using CVD technique, the area TSV second end deposit Ti film, TiN film and tungsten to form tungsten plug；

S2094, substrate surface is planarized using CMP process；

S2095, deposit SiO₂Insulating layer, the second end photoetching copper bump figure in the area TSV, utilizes electrochemical plating process for copper Copper is deposited, extra copper is removed by chemical mechanical milling tech, etches SiO₂Layer, the second end in the area TSV form copper bump；

S2096, the auxiliary disk being temporarily bonded is removed using the method for heated mechanical.

The preparation method of anti-static device provided in this embodiment for system in package, using SCR tube device periphery By SiO₂The technique that insulating layer surrounds, can effectively reduce the parasitic capacitance between active area and substrate.The utility model is considering work By the hole TSV of optimal setting certain length and using the doping concentration of given range on the basis of skill feasibility, and consider The electric current handling capacity of device reduces parasitic capacitance and resistance, and using the inductance of the hole TSV introducing to the parasitic capacitance of device A degree of tuning is carried out, the working range of esd protection circuit is expanded while raising system in package anti-ESD ability

It, cannot the above content is specific preferred embodiment further detailed description of the utility model is combined Assert that the specific implementation of the utility model is only limited to these instructions.For example, the multiple isolated areas referred in the utility model are only It is only to be illustrated according to device architecture sectional view provided by the utility model, wherein multiple isolated areas are also possible to some The first part and second part that the sectional view of such as ring bodies is shown in entirety, for the utility model technical field It for those of ordinary skill, should not be limited to these explanations, without departing from the concept of the premise utility, can also make Several simple deduction or replace, all shall be regarded as belonging to the protection scope of the utility model.

Claims

1. a kind of anti-static device for system in package characterized by comprising Si substrate (101), SCR pipe (102), Isolated area (103), the area TSV (104), interconnection line (105) and metal salient point (106)；Wherein,

The isolated area (103) and the area TSV (104) the Si substrate (101) up and down；The SCR pipe (102) sets It is placed in the Si substrate (101)；The isolated area (103) is set to the two sides of the SCR pipe (102)；The area TSV (104) it is set to by the two sides of SCR pipe (102) and the isolated area (103) forming region；The interconnection line (105) sets The first end face being placed on the Si substrate (101) for connecting the area TSV (104) and SCR pipe (102)；The gold Belong to salient point (106) to be set in the first end face of the area TSV (104).

2. anti-static device according to claim 1, which is characterized in that the SCR pipe includes: N well region and p-well region；Its In, the N well region includes N trap contact zone (2021) and anode (2022)；The p-well region includes cathode (2023) and p-well contact Area (2024).

3. anti-static device according to claim 1, which is characterized in that the first end face of the area TSV (104) and described Tungsten plug is provided between SCR pipe (102) and the interconnection line (105).

4. anti-static device according to claim 1, which is characterized in that the anti-static device further include be set to it is described The SiO on Si substrate (101) surface₂Insulating layer.

5. anti-static device according to claim 1, which is characterized in that the second end face of the area TSV (104) and described Metal salient point is provided with tungsten plug between (106).

6. anti-static device according to claim 1, which is characterized in that the interconnection line (105) and the metal salient point (106) material is copper.