CN108109988B

CN108109988B - Antistatic device for system-in-package

Info

Publication number: CN108109988B
Application number: CN201711349100.5A
Authority: CN
Inventors: 张捷
Original assignee: Institute of Flexible Electronics Technology of THU Zhejiang
Current assignee: Institute of Flexible Electronics Technology of THU Zhejiang
Priority date: 2017-12-15
Filing date: 2017-12-15
Publication date: 2020-12-22
Anticipated expiration: 2037-12-15
Also published as: CN108109988A

Abstract

The invention relates to an antistatic device for system-in-package, comprising: the silicon-based SOI device comprises a Si substrate (101), an SCR (silicon controlled rectifier) tube (102), an isolation region (103), a TSV region (104), an interconnection line (105) and a metal bump (106); wherein the isolation region (103) and the TSV region (104) both penetrate the Si substrate (101) up and down; the SCR tube (102) is arranged in the Si substrate (101); the isolation regions (103) are arranged on two sides of the SCR tube (102); the TSV region (104) is arranged on two sides of a region formed by the SCR tube (102) and the isolation region (103); the interconnecting wire (105) is arranged on the Si substrate (101) and is used for connecting the first end face of the TSV region (104) and the SCR tube (102); the metal bump (106) is arranged on the first end face of the TSV region (104). According to the invention, the SCR tube is arranged on the silicon through hole adapter plate to serve as an anti-static device, so that the problem of weak anti-static capability of the integrated circuit system-in-package is solved, and the anti-static capability of the integrated circuit system-in-package is enhanced.

Description

Antistatic device for system-in-package

Technical Field

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to an antistatic device for system-in-package.

Background

Electrostatic Discharge (ESD) events are common in everyday life, and some larger discharges can be detected by human senses, and smaller discharges are not noticed by human senses because the ratio of the Discharge intensity to the surface area over which the Discharge occurs is very small. ESD is a major factor in failure of devices and Integrated Circuits (ICs) because static electricity may be generated during manufacturing, packaging, testing and using of the devices or products, and when people contact with each other under unknown conditions, discharge paths are formed, and thus the products fail to function or are permanently damaged. Therefore, the ESD protection problem is one of the important issues in the field of integrated circuit design. With the increasing scale of integrated circuits, the difficulty of ESD protection design is increasing.

With the development of the computer, communication, automotive electronics, aerospace industry and other consumer systems, the size and power consumption of semiconductor chips are continuously increasing, i.e., smaller, thinner, lighter, highly reliable, multifunctional, low power and low cost chips are required. In the case where the packing density of the two-dimensional packing technology has reached the limit, the advantages of the higher density three-dimensional (3D) packing technology are self-evident.

The Through-Silicon Via (TSV) technology is a new technical solution for realizing interconnection of stacked chips in a 3D integrated circuit. Due to the TSV technology, the stacking density of the chips in the three-dimensional direction can be maximized, the interconnection lines among the chips are shortest, and the overall dimension is minimized, so that the 3D chip stacking can be effectively realized, the manufactured chips with more complex structures, stronger performance and more cost efficiency are manufactured, and the TSV technology becomes the most attractive technology in the existing electronic packaging technology.

An interposer generally refers to the functional layer of interconnection and pin redistribution between a chip and a package substrate. The adapter plate can redistribute dense I/O leads, high-density interconnection of multiple chips is achieved, and the adapter plate becomes one of the most effective means for electrical signal connection between a nanoscale integrated circuit and a millimeter-scale macroscopic world. When the multifunctional chip integration is realized by using the adapter plate, the antistatic capability of different chips is different, and the antistatic capability of the whole system after packaging can be influenced by the chips with weak antistatic capability during three-dimensional stacking; therefore, how to improve the antistatic capability of the system-in-package of the 3D-IC based on the TSV process becomes an urgent problem to be solved in the semiconductor industry.

Disclosure of Invention

In order to improve the antistatic capability of a 3D integrated circuit, the invention provides an antistatic device for system-in-package; the technical problem to be solved by the invention is realized by the following technical scheme:

an embodiment of the present invention provides an anti-static device for system in package, including: a Si substrate 101, a thyristor (SCR) 102, an isolation region 103, a TSV region 104, an interconnection line 105, and a metal bump 106; wherein the content of the first and second substances,

the isolation region 103 and the TSV region 104 both penetrate the Si substrate 101 from top to bottom; the SCR tube 102 is disposed within the Si substrate 101; the isolation regions 103 are disposed on two sides of the SCR tube 102; the TSV regions 104 are disposed on two sides of the region formed by the SCR tubes 102 and the isolation region 103; the interconnection line 105 is arranged on the Si substrate 101 and used for connecting the first end face of the TSV region 104 and the SCR tube 102; the metal bump 106 is disposed on the first end surface of the TSV region 104.

In one embodiment of the invention, an SCR tube comprises: an N well region and a P well region; wherein the N-well region includes an N-well contact region 2021 and an anode 2022; the P-well region includes a cathode 2023 and a P-well contact region 2024.

In one embodiment of the present invention, the doping impurity of the N-well region is phosphorus, and the doping concentration is preferably 1 × 10¹⁷cm^-3(ii) a The doping impurity of the P well region is boron, and the doping concentration is preferably 1 multiplied by 10¹⁸cm^-3。

In one embodiment of the present invention, the doping type of the Si substrate 101 is P-type with a doping concentration of 1 × 10¹⁴cm^-3The thickness is 80 to 120 μm.

In one embodiment of the present invention, tungsten plugs are disposed between the first end surface of the TSV region 104 and the SCR tube 102 and the interconnect line 105.

In one embodiment of the present invention, the anti-static device further comprises SiO disposed on the surface of the Si substrate 101₂An insulating layer.

In one embodiment of the present invention, the filling material in the TSV region 104 is polysilicon, and the doping concentration of the polysilicon is 2 × 10²¹cm^-3The doping material is phosphorus.

In an embodiment of the present invention, a tungsten plug is disposed between the second end surface of the TSV region 104 and the metal bump 106.

In one embodiment of the present invention, the material of the interconnect lines 105 and the metal bumps 106 is copper.

In one embodiment of the present invention, the depth of the isolation region 103 and the TSV region 104 is 80-120 μm.

Compared with the prior art, the invention has the following beneficial effects:

1. according to the invention, the ESD protection device-SCR tube is processed on the TSV adapter plate to form the system-in-package antistatic device, so that the antistatic capability of the stacked packaged chip is enhanced;

2. according to the invention, the SCR tube is arranged on the anti-static device, and the high heat dissipation capacity of the adapter plate is utilized, so that the high-current passing capacity of the device in working is improved;

3. the periphery of the SCR tube of the anti-static device provided by the invention utilizes the vertically through isolation region, so that the anti-static device has smaller leakage current and parasitic capacitance.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an anti-static device for system in package according to an embodiment of the present invention;

fig. 2 is a schematic flow chart illustrating a method for manufacturing an anti-static device for system in package according to an embodiment of the present invention;

fig. 3a to 3i are flow charts of another method for manufacturing an anti-static device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

Referring to fig. 1, fig. 1 is a schematic structural diagram of an anti-static device for system in package according to an embodiment of the present invention, including:

the structure comprises a Si substrate 101, an SCR tube 102, an isolation region 103, a TSV region 104, an interconnection line 105 and a metal bump 106; wherein the content of the first and second substances,

Further, the SCR tube includes: an N well region and a P well region; wherein the N-well region includes an N-well contact region 2021 and an anode 2022; the P-well region includes a cathode 2023 and a P-well contact region 2024.

Preferably, the doping impurity of the N well region is phosphorus, and the doping concentration is preferably 1 × 10¹⁷cm^-3(ii) a The doping impurity of the P well region is boron, and the doping concentration is preferably 1 multiplied by 10¹⁸cm^-3。

Preferably, the doping type of the Si substrate 101 is P-type with a doping concentration of 1 × 10¹⁴cm^-3The thickness is 80 to 120 μm.

Preferably, tungsten plugs are disposed between the first end face of the TSV region 104 and the SCR tube 102 and the interconnection line 105.

Specifically, the antistatic device further includes SiO disposed on the upper and lower surfaces of the Si substrate 101₂An insulating layer.

Preferably, the filling material in the TSV region 104 is polysilicon, and the doping concentration of the polysilicon is 2 × 10²¹cm^-3The doping material is phosphorus.

Specifically, a tungsten plug is disposed between the second end face of the TSV region 104 and the metal bump 106.

Preferably, the material of the interconnection line 105 and the metal bump 106 is copper.

Preferably, the depth of the isolation region 103 and the TSV region 104 is 80-120 μm.

According to the anti-static device provided by the embodiment, the ESD protection device SCR tube is arranged on the anti-static device, so that the anti-static capability of the stacked and packaged chips is enhanced, and the problem that the anti-static capability of the packaged whole system is affected by the chips with weak anti-static capability in three-dimensional stacking is solved; meanwhile, the embodiment provides the anti-static device with the vertically-through isolation region arranged around the SCR tube, and has smaller leakage current and parasitic capacitance.

Example two

Referring to fig. 2 and fig. 2 are schematic flow charts of a method for manufacturing an anti-static device for system-in-package according to an embodiment of the present invention, and the embodiment of the present invention describes the method for manufacturing an anti-static device in detail below on the basis of the above embodiment. Specifically, the method comprises the following steps:

s101, selecting a Si substrate;

s102, etching the Si substrate to form a TSV hole and an isolation trench respectively;

s103, filling the isolation trenches and the TSVs to form a plurality of isolation regions and TSV regions respectively;

s104, preparing an N well region and a P well region of the SCR tube between the two isolation regions;

s105, preparing an N well contact area, a cathode, a P well contact area and an anode of the SCR tube;

s106, forming an interconnection line between the first end face of the TSV region and the SCR tube;

and S107, preparing a metal bump on the second end face of the TSV region to finish the preparation of the anti-static device.

Preferably, S102 may include:

s1021, forming an etching pattern of the TSV and the isolation groove on the upper surface of the Si substrate by utilizing a photoetching process;

s1022, Etching the Si substrate by utilizing a Deep Reactive Ion Etching (DRIE) process to form TSV and an isolation trench;

and the depth of the TSV and the isolation trench is less than the thickness of the Si substrate.

Preferably, S103 may include:

s1031, thermally oxidizing the TSV and the isolation trench to form an oxide layer on the inner walls of the TSV and the isolation trench;

s1032, etching the oxide layer by using a wet etching process to finish the planarization of the TSV and the inner wall of the isolation groove;

s1033, forming a filling pattern of the isolation groove by utilizing a photoetching process;

s1034, filling SiO in the isolation trench by Chemical Vapor Deposition (CVD) process₂Forming an isolation region;

s1035, forming a TSV filling pattern by utilizing a photoetching process;

s1036, filling a polysilicon material in the TSV by using a CVD (chemical vapor deposition) process, and introducing a doping gas to perform in-situ doping to form a TSV region.

Preferably, S104 may include:

s1041, preparing a masking layer by using a CVD (chemical vapor deposition) process;

s1042, at two partitionsPhotoetching N well region patterns of SCR tubes between isolated regions, and performing N by adopting an ion implantation process⁺Injecting and removing the photoresist to form an N well region of the SCR tube;

s1043, photoetching a P well region pattern of the SCR tube between the two isolation regions, and performing P by adopting an ion implantation process⁺And injecting and removing the photoresist to form a P well region of the SCR tube.

Preferably, S105 may include:

s1051, photoetching N trap contact area and cathode pattern, and carrying out N by adopting ion implantation process⁺Injecting and removing the photoresist to form an N trap contact area and a cathode of the SCR tube;

s1052, photoetching P well contact area and cathode pattern, and performing P by adopting ion implantation process⁺And injecting and removing the photoresist to form a P trap contact area and an anode of the SCR tube.

Specifically, S107 is preceded by:

x1, using the auxiliary wafer as a support of the upper surface of the Si substrate;

x2, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process;

and x3, using a Chemical Mechanical Polishing (CMP) process to planarize the lower surface of the Si substrate until the second end surface of the TSV region is exposed.

Preferably, S107 may include:

s1071, forming a liner layer and a barrier layer on the lower surface of the Si substrate by using a sputtering process, and forming a tungsten plug on the second end face of the TSV region by using a CVD process;

s1072, depositing an insulating layer, photoetching a pattern of the metal salient point on the second end face of the TSV region, depositing metal by using an electrochemical copper plating process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal salient point on the second end face of the TSV region;

s1073, removing the auxiliary wafer.

Preferably, the doping concentration of the Si substrate is 1 × 10¹⁴cm^-3The thickness is 150 to 250 μm.

Preferably, the depth of the TSV region and the isolation region is 80-120 mu m.

The preparation method of the antistatic device provided by the embodiment can be realized in the conventional TSV process platform, so that the compatibility is strong and the application range is wide; the SCR tube is prepared in the adapter plate by utilizing the characteristics that the SCR tube has low holding voltage, can bear high ESD current and naturally has high ESD robustness, so that the antistatic capability of the integrated circuit during system-level packaging is greatly improved.

EXAMPLE III

In this embodiment, specific parameters of the manufacturing method of the anti-static device of the present invention are described as follows. Specifically, referring to fig. 3a to 3i, fig. 3a to 3i are flow charts of a method for manufacturing another anti-static device according to an embodiment of the present invention.

S201, as shown in FIG. 3a, selecting a Si substrate 201;

preferably, the doping type of the Si substrate is P type, and the doping concentration is 1 multiplied by 10¹⁴The thickness is 150 to 250 μm.

S202, as shown in fig. 3b, preparing the TSV202 and the isolation trench 203 on the Si substrate by using an etching process may include the following steps:

s2021, growing a layer of SiO with the thickness of 800nm to 1000nm on the upper surface of the Si substrate by a thermal oxidation process at the temperature of 1050 ℃ to 1100 DEG C₂A layer;

s2022, completing TSV and isolation trench etching graphs by using a photoetching process through processes of gluing, photoetching, developing and the like;

s2023, etching the Si substrate by using a DRIE (deep etch etching) process to form TSV and an isolation trench with the depth of 80-120 mu m;

s2024, removing SiO on the Si substrate by using CMP process₂The substrate surface is planarized.

Preferably, two isolation trenches are located between two TSVs.

S203, as shown in FIG. 3 c; deposition of SiO on Si substrates by CVD process₂Filling the isolation trench to form an isolation region, which may specifically include the following steps:

s2031, thermally oxidizing the inner walls of the TSV and the isolation trench to form an oxide layer with the thickness of 200nm to 300nm at the temperature of 1050 ℃ to 1100 ℃;

s2032, etching the oxidation layer of the inner walls of the TSV and the isolation trench by using a wet etching process to finish the planarization of the inner walls of the TSV and the isolation trench. Preventing the TSV and the protrusion of the side wall of the isolation trench from forming an electric field concentration area;

s2033, completing the filling pattern of the isolation trench by gluing, photoetching, developing and other processes by utilizing a photoetching process;

s2034, depositing SiO by Low Pressure Chemical Vapor Deposition (LPCVD) at 690-710 deg.C₂Filling the isolation groove to form an isolation region; as can be appreciated, the SiO₂The material is mainly used for isolation and can be replaced by other materials such as undoped polysilicon and the like;

s2035, planarizing the surface of the substrate by using a CMP process.

S204, as shown in FIG. 3 d; the method comprises the following steps of depositing a polycrystalline silicon material on a Si substrate by using a CVD (chemical vapor deposition) process to fill TSV, and simultaneously introducing doping gas to carry out in-situ doping on the polycrystalline silicon to form a TSV region, wherein the method specifically comprises the following steps:

s2041, completing a TSV filling pattern through processes such as gluing, photoetching and developing by utilizing a photoetching process;

s2042, depositing a polycrystalline silicon material by using a CVD (chemical vapor deposition) process at the temperature of 600-620 ℃ to fill the TSV, introducing doping gas to carry out in-situ doping, and realizing in-situ activation of doping elements to form highly doped polycrystalline silicon filling. Therefore, when the TSV is filled, the conductive material with uniform impurity distribution and high doping concentration can be formed for filling, and the resistance of the TSV is favorably reduced. The doping concentration of polysilicon is preferably 2 × 10²¹cm^-3The doping impurity is preferably phosphorus;

and S2043, flattening the surface of the substrate by utilizing a CMP process.

S205, as shown in FIG. 3 e; the method for manufacturing the N-well region 204 and the P-well region 205 of the SCR tube between the two isolation regions may specifically include the following steps:

s2051, at 1050-1100 deg.C, using thermal oxidation process to form Si linerFormation of SiO on the bottom surface₂A buffer layer;

s2052, depositing Si on the surface of the Si substrate by LPCVD process at 700-800 DEG C₃N₄A layer;

s2053, photoetching the N well region, performing phosphorus injection by adopting an ion injection process with glue, removing the photoresist to form the N well region of the SCR tube, wherein the doping concentration is preferably 1 multiplied by 10¹⁷cm^-3；

S2054, annealing the substrate for 2.5 hours at the temperature of 950 ℃ to carry out N-well propulsion;

s2055, removing Si on the surface of the substrate by using a wet etching process₃N₄A layer;

s2056, photoetching the P well region, performing boron injection by adopting an ion injection process with glue, removing the photoresist to form the P well region of the SCR tube, wherein the doping concentration is preferably 1 multiplied by 10¹⁸cm^-3；

S2057, annealing the substrate for 2.5 hours at the temperature of 950 ℃ to carry out P well propulsion.

S206, as shown in FIG. 3 f; the preparation of the N-well contact area 206, the cathode 207, the anode 208 and the P-well contact area 209 of the SCR tube may specifically include the following steps:

s2061, photoetching N trap contact region and cathode, and performing N by adopting a glue-carrying ion implantation process⁺Injecting and removing the photoresist to form an N trap contact region and N of the SCR tube⁺And a cathode. The doping concentration is preferably 1.5X 10²⁰cm^-3The doping impurity is preferably phosphorus;

s2062, photoetching P well contact region and cathode, and performing P by adopting a photoresist ion implantation process⁺Injecting and removing the photoresist to form a P well contact region and a P of the SCR tube⁺And an anode. The doping concentration is preferably 1.5X 10²⁰cm^-3The doping impurity is preferably boron;

s2063, annealing the substrate for 15-120S at 950-1100 ℃ to activate the impurities.

S207, as shown in FIG. 3 g; the formation of the copper interconnection line 210 on the upper surface of the Si substrate by using the electroplating process may specifically include the following steps:

s2071, using plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process to deposit SiO on the substrate surface₂A layer;

s2072, completing contact hole patterns at the first end of the TSV region, the N well contact region, the cathode, the P well contact region and the anode of the SCR tube by using a photoetching process through processes of gluing, photoetching, developing and the like;

s2073, depositing a Ti film, a TiN film and tungsten on the first end of the TSV region, the N well contact region, the cathode, the P well contact region and the anode of the SCR tube by using a CVD (chemical vapor deposition) process to form a tungsten plug;

s2074, flattening the surface of the substrate by using a CMP process;

s2075, depositing SiO₂The insulating layer is used for photoetching a copper interconnection pattern, depositing copper by using an electrochemical copper plating method, removing redundant copper by using a chemical mechanical grinding method, and forming a first end of the TSV region and an MOS (metal oxide semiconductor) tube serial copper interconnection line;

and S2076, flattening the surface of the substrate by using a CMP process.

Further, when the copper interconnection line is prepared, the metal interconnection line can be used to be wound in a spiral shape so as to have the characteristic of inductance for better electrostatic protection of the radio frequency integrated circuit.

S208, as shown in FIG. 3 h; the method for thinning the Si substrate by using the chemical mechanical polishing process to leak the TSV region specifically comprises the following steps:

s2081, bonding the upper surface of the Si substrate with an auxiliary wafer by using a high polymer material as an intermediate layer, and finishing the thinning of the Si substrate through the support of the auxiliary wafer;

s2082, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process until the thickness is slightly larger than the depth of the TSV region, preferably larger than the depth of the TSV by 10 microns;

s2083, flattening the lower surface of the Si substrate by using a CMP process until the TSV region is exposed;

s209, as shown in FIG. 3 i; the copper bump 211 is formed on the lower surface of the Si substrate by an electroplating copper method, which may specifically include the following steps:

s2091, depositing SiO on the lower surface of the substrate by using a PECVD process₂A layer;

s2092, at the second end of the TSV region, completing a contact hole pattern through processes of gluing, photoetching, developing and the like by using a photoetching process;

s2093, depositing a Ti film, a TiN film and tungsten at the second end of the TSV region by using a CVD (chemical vapor deposition) process to form a tungsten plug;

s2094, flattening the surface of the substrate by using a CMP process;

s2095, depositing SiO₂An insulating layer for photoetching copper convex point pattern at the second end of the TSV region, depositing copper by electrochemical copper plating process, removing excessive copper by chemical mechanical grinding process, and etching SiO₂A layer, forming a copper bump at a second end of the TSV region;

s2096, removing the temporarily bonded auxiliary wafer by using a heating mechanical method.

In the method for manufacturing the esd protection device for system in package provided in this embodiment, the periphery of the SCR device is covered by SiO₂The process surrounded by the insulating layer can effectively reduce the parasitic capacitance between the active region and the substrate. According to the invention, on the basis of considering process feasibility, parasitic capacitance and resistance are reduced by optimally setting the TSV hole with a certain length and utilizing the doping concentration in a given range and considering the current passing capacity of a device, and the parasitic capacitance of the device is tuned to a certain degree by utilizing the inductance introduced by the TSV hole, so that the ESD (electro-static discharge) resistance of the system-in-package is improved, and the working range of the ESD protection circuit is expanded at the same time

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For example, the plurality of isolation regions mentioned in the present invention are only illustrated according to the cross-sectional view of the device structure provided in the present invention, wherein the plurality of isolation regions may also be a first portion and a second portion shown in a cross-sectional view of a ring body as a whole, and it should not be limited to these descriptions for a person skilled in the art to which the present invention pertains, and several simple deductions or replacements can be made without departing from the spirit of the present invention, and all of them should be considered as belonging to the protection scope of the present invention.

Claims

1. An anti-static apparatus for a system in package, comprising: the silicon-controlled SCR structure comprises a Si substrate (101), a silicon-controlled SCR thyristor (102), two isolation regions (103), two Through Silicon Via (TSV) regions (104), an interconnection line (105) and a metal bump (106); wherein the content of the first and second substances,

the two isolation regions (103) and the two TSV regions (104) both penetrate the Si substrate (101) up and down; the SCR tube (102) is arranged in the Si substrate (101); the two isolation regions (103) are respectively arranged at two sides of the SCR tube (102); the two TSV regions (104) are respectively arranged on two sides of a region formed by the SCR tube (102) and the two isolation regions (103); the interconnecting wire (105) is arranged on the Si substrate (101) and is used for connecting the first end face of the TSV region (104) and the SCR tube (102); the metal bump (106) is arranged on the second end face of the TSV region (104); wherein the content of the first and second substances,

the filling material in the TSV region (104) is polysilicon, and the doping concentration of the polysilicon is 2 x 10²¹cm^-3The doping material is phosphorus;

the depth of the isolation region (103), the depth of the TSV region (104) and the thickness of the Si substrate (101) are equal and are all 80-120 mu m;

further comprises SiO arranged on the surface of the Si substrate (101)₂An insulating layer;

the periphery of the SCR tube (102) is coated with SiO₂The insulating layer surrounds.

2. The anti-static device according to claim 1, wherein the SCR tube comprises: an N well region and a P well region; wherein the N-well region comprises an N-well contact region (2021) and an anode (2022); the P-well region includes a cathode (2023) and a P-well contact region (2024).

3. The device according to claim 2, wherein the doping impurity of the N well region is phosphorus with a doping concentration of 1 x 10¹⁷cm^-3(ii) a The doped impurity of the P well region is boron, and the doping concentration is 1 multiplied by 10¹⁸cm^-3。

4. The antistatic device according to claim 1, wherein the doping type of the Si substrate (101) is P-type with a doping concentration of 1 x 10¹⁴cm^-3The thickness is 80 to 120 μm.

5. The static dissipative apparatus according to claim 1, wherein a tungsten plug is disposed between the first end faces of the two TSV regions (104) and the SCR tube (102) and the interconnect line (105).

6. The anti-static device according to claim 1, wherein a tungsten plug is disposed between the second end surfaces of the two TSV regions (104) and the metal bump (106).

7. An antistatic device according to claim 1, characterized in that the material of the interconnect line (105) and the metal bump (106) is copper.