CN108063113B

CN108063113B - Anti-static device for system-in-package and preparation method thereof

Info

Publication number: CN108063113B
Application number: CN201711349123.6A
Authority: CN
Inventors: 张捷
Original assignee: Institute of Flexible Electronics Technology of THU Zhejiang
Current assignee: Institute of Flexible Electronics Technology of THU Zhejiang
Priority date: 2017-12-15
Filing date: 2017-12-15
Publication date: 2021-01-12
Anticipated expiration: 2037-12-15
Also published as: CN108063113A

Abstract

The invention relates to an antistatic device for system-in-package and a preparation method thereof, wherein the method comprises the following steps: selecting a Si substrate; etching the Si substrate to form a plurality of TSVs and a plurality of isolation grooves respectively; etching the Si substrate to form a plurality of device grooves among the isolation grooves; filling the isolation trench and the TSV to form an isolation region and a TSV region respectively; preparing a transverse SCR tube in the device groove; preparing a copper interconnection line between the first end face of the TSV region and the transverse SCR tube; and preparing copper salient points on the second end face of the TSV area to finish the preparation of the TSV adapter plate. According to the TSV adapter plate, the ESD protection device SCR tube is processed on the TSV adapter plate, so that the antistatic capacity of the stacked packaged chip is improved.

Description

Anti-static device for system-in-package and preparation method thereof

Technical Field

The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to an anti-static device for system-in-package and a preparation method thereof.

Background

Electrostatic Discharge (ESD) events are common in everyday life, and some larger discharges can be detected by human senses, and smaller discharges are not noticed by human senses because the ratio of the Discharge intensity to the surface area over which the Discharge occurs is very small. ESD is a major factor in failure of devices and Integrated Circuits (ICs) because static electricity may be generated during manufacturing, packaging, testing and using of the devices or products, and when people contact with each other under unknown conditions, discharge paths are formed, and thus the products fail to function or are permanently damaged. Therefore, the ESD protection problem is one of the important issues in the field of integrated circuit design. With the increasing scale of integrated circuits, the difficulty of ESD protection design is increasing.

With the development of the computer, communication, automotive electronics, aerospace industry and other consumer systems, the size and power consumption of semiconductor chips are continuously increasing, i.e., smaller, thinner, lighter, highly reliable, multifunctional, low power and low cost chips are required. In the case where the packing density of the two-dimensional packing technology has reached the limit, the advantages of the higher density three-dimensional (3D) packing technology are self-evident.

The Through-Silicon Via (TSV) technology is a new technical solution for realizing interconnection of stacked chips in a 3D integrated circuit. Due to the TSV technology, the stacking density of the chips in the three-dimensional direction can be maximized, the interconnection lines among the chips are shortest, and the overall dimension is minimized, so that the 3D chip stacking can be effectively realized, the manufactured chips with more complex structures, stronger performance and more cost efficiency are manufactured, and the TSV technology becomes the most attractive technology in the existing electronic packaging technology.

However, when the three-dimensionally stacked integrated circuit system is packaged, the antistatic capabilities of different chips are different, and the chips with weak antistatic capabilities during three-dimensional stacking affect the antistatic capabilities of the packaged whole system; therefore, how to improve the antistatic capability of the system-in-package of the 3D-IC based on the TSV process becomes an urgent problem to be solved in the semiconductor industry.

Disclosure of Invention

In order to improve the antistatic capability of a 3D integrated circuit based on a TSV process, the invention provides an antistatic device for system-in-package and a preparation method thereof; the technical problem to be solved by the invention is realized by the following technical scheme:

the embodiment of the invention provides a preparation method of an antistatic device for system-in-package, which comprises the following steps:

s101, selecting a Si substrate;

s102, etching the Si substrate to form a TSV hole and an isolation trench respectively;

s103, filling the isolation trench and the TSV to form an isolation region and a TSV region respectively;

s104, preparing an N well region and a P well region of a thyristor, namely a Silicon Controlled Rectifier (SCR), between the two isolation regions;

s105, preparing an N well contact area, a cathode, a P well contact area and an anode of the SCR tube;

s106, forming an interconnection line between the first end face of the TSV region and the SCR tube;

and S107, preparing a metal bump on the second end face of the TSV region to complete the preparation of the TSV adapter plate.

In one embodiment of the present invention, S102 includes:

s1021, forming an etching pattern of the TSV and the isolation groove on the upper surface of the Si substrate by utilizing a photoetching process;

s1022, Etching the Si substrate by utilizing a Deep Reactive Ion Etching (DRIE) process to form TSV and an isolation trench;

and the depth of the TSV and the isolation trench is less than the thickness of the Si substrate.

In one embodiment of the present invention, S103 includes:

s1031, thermally oxidizing the TSV and the isolation trench to form an oxide layer on the inner walls of the TSV and the isolation trench;

s1032, etching the oxide layer by using a wet etching process to finish the planarization of the TSV and the inner wall of the isolation groove;

s1033, forming a filling pattern of the isolation groove by utilizing a photoetching process;

s1034, filling SiO in the isolation trench by Chemical Vapor Deposition (CVD) process₂Forming an isolation region;

s1035, forming a TSV filling pattern by utilizing a photoetching process;

s1036, filling a polysilicon material in the TSV by using a CVD (chemical vapor deposition) process, and introducing a doping gas to perform in-situ doping to form a TSV region.

In one embodiment of the present invention, S104 includes:

s1041, preparing a masking layer by using a CVD (chemical vapor deposition) process;

s1042, photoetching an N well region pattern of the SCR tube between the two isolation regions, and performing N by adopting an ion implantation process⁺Injecting and removing the photoresist to form an N well region of the SCR tube;

s1043, photoetching a P well region pattern of the SCR tube between the two isolation regions, and performing P by adopting an ion implantation process⁺And injecting and removing the photoresist to form a P well region of the SCR tube.

In one embodiment of the present invention, S105 includes:

s1051, photoetching N trap contact area and cathode pattern, and carrying out N by adopting ion implantation process⁺Injecting and removing the photoresist to form an N trap contact region and a cathode of the SCR tubeA pole;

s1052, photoetching P well contact area and cathode pattern, and performing P by adopting ion implantation process⁺And injecting and removing the photoresist to form a P trap contact area and an anode of the SCR tube.

In an embodiment of the present invention, S107 further includes:

x1, using the auxiliary wafer as a support of the upper surface of the Si substrate;

x2, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process;

and x3, using a Chemical Mechanical Polishing (CMP) process to planarize the lower surface of the Si substrate until the second end surface of the TSV region is exposed.

In one embodiment of the present invention, S107 includes:

s1071, forming a liner layer and a barrier layer on the lower surface of the Si substrate by using a sputtering process, and forming a tungsten plug on the second end face of the TSV region by using a CVD process;

s1072, depositing an insulating layer, photoetching a pattern of the metal salient point on the second end face of the TSV region, depositing metal by using an electrochemical copper plating process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal salient point on the second end face of the TSV region;

s1073, removing the auxiliary wafer.

In one embodiment of the present invention, the doping concentration of the Si substrate is 1 × 10¹⁴cm^-3The thickness is 150 to 250 μm.

In one embodiment of the invention, the depth of the TSV region and the isolation region is 80-120 μm.

Compared with the prior art, the invention has the following beneficial effects:

1. according to the invention, the ESD protection device-SCR tube is processed on the TSV adapter plate to form the system-in-package antistatic device, so that the antistatic capability of the stacked packaged chip is enhanced;

2. according to the invention, the SCR tube is processed on the TSV adapter plate, and the high heat dissipation capacity of the adapter plate is utilized, so that the high-current passing capacity of the device in the working process is improved;

3. the TSV adapter plate provided by the invention has the advantages that the periphery of the SCR tube is provided with the vertically-through isolation grooves, so that the leakage current and the parasitic capacitance are smaller;

4. the preparation method of the antistatic device for the system-in-package can be realized in the conventional TSV process platform, so that the compatibility is strong and the application range is wide.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic flow chart illustrating a method for manufacturing an anti-static device for system in package according to an embodiment of the present invention;

fig. 2a to fig. 2i are flow charts of another TSV interposer manufacturing method according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a TSV interposer according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

Referring to fig. 1, fig. 1 is a schematic flow chart of a method for manufacturing an anti-static device for system in package according to an embodiment of the present invention, including:

s101, selecting a Si substrate;

s104, preparing an N well region and a P well region of the SCR tube between the two isolation regions;

Preferably, S102 may include:

s1022, etching the Si substrate by using a DRIE process to form a TSV and an isolation trench;

Preferably, S103 may include:

s1034, filling SiO in the isolation trench by using a CVD process₂Forming an isolation region;

s1035, forming a TSV filling pattern by utilizing a photoetching process;

Preferably, S104 may include:

Preferably, S105 may include:

s1051, photoetching N-well contact region and cathodePatterning by ion implantation to N⁺Injecting and removing the photoresist to form an N trap contact area and a cathode of the SCR tube;

Specifically, S107 is preceded by:

and x3, flattening the lower surface of the Si substrate by using a CMP process until the second end face of the TSV region is exposed.

Preferably, S107 may include:

s1073, removing the auxiliary wafer.

Preferably, the doping concentration of the Si substrate is 1 × 10¹⁴cm^-3The thickness is 150 to 250 μm.

Preferably, the depth of the TSV region and the isolation region is 80-120 mu m.

According to the preparation method of the anti-static device, the anti-static device is formed by processing the transverse SCR tube on the TSV adapter plate, so that the anti-static capability of the stacked and packaged chips is enhanced, and the problem that the anti-static capability of the packaged whole system is affected by chips with weak anti-static capability in three-dimensional stacking is solved; meanwhile, the isolation regions which are communicated up and down are arranged around the SCR tube of the TSV adapter plate, so that the TSV adapter plate has smaller leakage current and parasitic capacitance.

Example two

In this embodiment, based on the above embodiments, specific parameters in the preparation method of the TSV interposer of the present invention are described as follows. Specifically, referring to fig. 2a to fig. 2i, fig. 2a to fig. 2i are flow charts of another TSV interposer manufacturing method according to an embodiment of the present invention,

s201, as shown in FIG. 2a, selecting a Si substrate 201;

preferably, the doping type of the Si substrate is P type, and the doping concentration is 1 multiplied by 10¹⁴cm^-3The thickness is 150 to 250 μm.

S202, as shown in fig. 2b, preparing the TSV202 and the isolation trench 203 on the Si substrate by using an etching process may include the following steps:

s2021, growing a layer of SiO with the thickness of 800nm to 1000nm on the upper surface of the Si substrate by a thermal oxidation process at the temperature of 1050 ℃ to 1100 DEG C₂A layer;

s2022, completing TSV and isolation trench etching graphs by using a photoetching process through processes of gluing, photoetching, developing and the like;

s2023, etching the Si substrate by using a DRIE (deep etch etching) process to form TSV and an isolation trench with the depth of 80-120 mu m;

s2024, removing SiO on the Si substrate by using CMP process₂The substrate surface is planarized.

Preferably, two isolation trenches are located between two TSVs.

S203, as shown in FIG. 2 c; deposition of SiO on Si substrates by CVD process₂Filling the isolation trench to form an isolation region, which may specifically include the following steps:

s2031, thermally oxidizing the inner walls of the TSV and the isolation trench to form an oxide layer with the thickness of 200nm to 300nm at the temperature of 1050 ℃ to 1100 ℃;

s2032, etching the oxidation layer of the inner walls of the TSV and the isolation trench by using a wet etching process to finish the planarization of the inner walls of the TSV and the isolation trench. Preventing the TSV and the protrusion of the side wall of the isolation trench from forming an electric field concentration area;

s2033, completing the filling pattern of the isolation trench by gluing, photoetching, developing and other processes by utilizing a photoetching process;

s2034, depositing SiO by Low Pressure Chemical Vapor Deposition (LPCVD) at 690-710 deg.C₂Filling the isolation groove to form an isolation region; as can be appreciated, the SiO₂The material is mainly used for isolation and can be replaced by other materials such as undoped polysilicon and the like;

s2035, planarizing the surface of the substrate by using a CMP process.

S204, as shown in FIG. 2 d; the method comprises the following steps of depositing a polycrystalline silicon material on a Si substrate by using a CVD (chemical vapor deposition) process to fill TSV, and simultaneously introducing doping gas to carry out in-situ doping on the polycrystalline silicon to form a TSV region, wherein the method specifically comprises the following steps:

s2041, completing a TSV filling pattern through processes such as gluing, photoetching and developing by utilizing a photoetching process;

s2042, depositing a polycrystalline silicon material by using a CVD (chemical vapor deposition) process at the temperature of 600-620 ℃ to fill the TSV, introducing doping gas to carry out in-situ doping, and realizing in-situ activation of doping elements to form highly doped polycrystalline silicon filling. Therefore, when the TSV is filled, the conductive material with uniform impurity distribution and high doping concentration can be formed for filling, and the resistance of the TSV is favorably reduced. The doping concentration of polysilicon is preferably 2 × 10²¹cm^-3The doping impurity is preferably phosphorus;

and S2043, flattening the surface of the substrate by utilizing a CMP process.

S205, as shown in FIG. 2 e; preparing an N-well region 204 and a P-well region 205 of the SCR tube between the two isolation regions may specifically include the following steps:

s2051, forming SiO on the surface of the Si substrate by a thermal oxidation process at 1050-1100 DEG C₂A buffer layer;

s2052, depositing Si on the surface of the Si substrate by LPCVD process at 700-800 DEG C₃N₄A layer;

s2053, photoetching the N well region, performing phosphorus injection by adopting an ion injection process with glue, removing the photoresist to form the N well region of the SCR tube, wherein the doping concentration is preferably 1 multiplied by 10¹⁷cm^-3；

S2054, annealing the substrate for 2.5 hours at the temperature of 950 ℃ to carry out N-well propulsion;

s2055, removing Si on the surface of the substrate by using a wet etching process₃N₄A layer;

s2056, photoetching the P well region, performing boron injection by adopting an ion injection process with glue, removing the photoresist to form the P well region of the SCR tube, wherein the doping concentration is preferably 1 multiplied by 10¹⁸cm^-3；

S2057, annealing the substrate for 2.5 hours at the temperature of 950 ℃ to carry out P well propulsion.

S206, as shown in FIG. 2 f; the preparation of the N-well contact area 206, the cathode 207, the anode 208 and the P-well contact area 209 of the SCR tube may specifically include the following steps:

s2061, photoetching N trap contact region and cathode, and performing N by adopting a glue-carrying ion implantation process⁺Injecting and removing the photoresist to form an N trap contact region and N of the SCR tube⁺And a cathode. The doping concentration is preferably 1.5X 10²⁰cm^-3The doping impurity is preferably phosphorus;

s2062, photoetching P well contact region and cathode, and performing P by adopting a photoresist ion implantation process⁺Injecting and removing the photoresist to form a P well contact region and a P of the SCR tube⁺And an anode. The doping concentration is preferably 1.5X 10²⁰cm^-3The doping impurity is preferably boron;

s2063, annealing the substrate for 15-120S at 950-1100 ℃ to activate the impurities.

S207, as shown in FIG. 2 g; the formation of the copper interconnection line 210 on the upper surface of the Si substrate by using the electroplating process may specifically include the following steps:

s2071, depositing SiO on the surface of the substrate by Plasma Enhanced Chemical Vapor Deposition (PECVD) process₂A layer;

s2072, completing contact hole patterns at the first end of the TSV region, the N well contact region, the cathode, the P well contact region and the anode of the SCR tube by using a photoetching process through processes of gluing, photoetching, developing and the like;

s2073, depositing a Ti film, a TiN film and tungsten on the first end of the TSV region, the N well contact region, the cathode, the P well contact region and the anode of the SCR tube by using a CVD (chemical vapor deposition) process to form a tungsten plug;

s2074, flattening the surface of the substrate by using a CMP process;

s2075, depositing SiO₂The insulating layer is used for photoetching a copper interconnection pattern, depositing copper by using an electrochemical copper plating method, removing redundant copper by using a chemical mechanical grinding method, and forming a first end of the TSV region and an MOS (metal oxide semiconductor) tube serial copper interconnection line;

and S2076, flattening the surface of the substrate by using a CMP process.

Further, when the copper interconnection line is prepared, the metal interconnection line can be used to be wound in a spiral shape so as to have the characteristic of inductance for better electrostatic protection of the radio frequency integrated circuit.

S208, as shown in FIG. 2 h; the method for thinning the Si substrate by using the chemical mechanical polishing process to leak the TSV region specifically comprises the following steps:

s2081, bonding the upper surface of the Si substrate with an auxiliary wafer by using a high polymer material as an intermediate layer, and finishing the thinning of the Si substrate through the support of the auxiliary wafer;

s2082, thinning the lower surface of the Si substrate by using a mechanical grinding and thinning process until the thickness is slightly larger than the depth of the TSV region, preferably larger than the depth of the TSV by 10 microns;

s2083, flattening the lower surface of the Si substrate by using a CMP process until the TSV region is exposed;

s209, as shown in FIG. 2 i; the copper bump 211 is formed on the lower surface of the Si substrate by an electroplating copper method, which may specifically include the following steps:

s2091, depositing SiO on the lower surface of the substrate by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process₂A layer;

s2092, at the second end of the TSV region, completing a contact hole pattern through processes of gluing, photoetching, developing and the like by using a photoetching process;

s2093, depositing a Ti film, a TiN film and tungsten at the second end of the TSV region by using a CVD (chemical vapor deposition) process to form a tungsten plug;

s2094, flattening the surface of the substrate by using a CMP process;

s2095, depositing SiO₂An insulating layer for photoetching copper convex point pattern at the second end of the TSV region, depositing copper by electrochemical copper plating process, removing excessive copper by chemical mechanical grinding process, and etching SiO₂A layer, forming a copper bump at a second end of the TSV region;

s2096, removing the temporarily bonded auxiliary wafer by using a heating mechanical method.

In the method for manufacturing the esd protection device for system in package provided in this embodiment, the periphery of the SCR device is covered by SiO₂The process surrounded by the insulating layer can effectively reduce the parasitic capacitance between the active region and the substrate. According to the invention, on the basis of considering process feasibility, the parasitic capacitance and resistance are reduced by optimally setting the TSV holes with a certain length and utilizing the doping concentration in a given range and considering the current passing capacity of the device, and the parasitic capacitance of the device is tuned to a certain degree by utilizing the inductance introduced by the TSV holes, so that the ESD resistance of the system-in-package is improved and the working range of the ESD protection circuit is expanded.

EXAMPLE III

Referring to fig. 3, fig. 3 is a schematic structural diagram of a TSV interposer according to an embodiment of the present invention; in this embodiment, a structure of a TSV interposer is described in detail based on the above embodiments, wherein the TSV interposer is manufactured by the above manufacturing process shown in fig. 2a to fig. 2 i. Specifically, the TSV adapter plate includes:

si substrate 301, first TSV region 3021, second TSV region 3022, first isolation region 3031, second isolation region 3032, SCR tubes, first interconnect line 3101, second interconnect line 3102, and copper bump 311; wherein,

the SCR tube is located between the first isolation region 3031 and the second isolation region 3032; the region formed by the SCR tube, the first isolation region 3031 and the second isolation region 3032 is positioned between the first TSV region 3021 and the second TSV region 3022; first interconnect 3101 and second interconnect 3102 are located over a first end of first TSV region 3021, a first end of second TSV region 3022, and the SCR tube; copper bump 311 is located on the second end of first TSV region 3021 and the second end of second TSV region 3022.

Specifically, the SCR tube includes: n-well region 304, P-well region 305, N-well contact region 306 of the SCR tube, cathode 307, anode 308, and P-well contact region 309.

Further, a first interconnecting line 3101 is used to connect the first end face of the first TSV region 3021, the N-well contact region 306, and the anode 308; the second interconnection line 3102 is used to connect the first end face of the second TSV region 3021, the cathode 307, and the P-well contact region 309.

Specifically, the material filled in the TSV region 302 is polysilicon; isolation region 303 filled material SiO₂。

Specifically, tungsten plugs are disposed between the first interconnect line 3101 and the first end face of the first TSV region 3021, the N-well contact region 306, and the anode 308; tungsten plugs are arranged between the second interconnecting line 3102 and the first end face of the second TSV region 3021, the cathode 307 and the P-well contact region 309; tungsten plugs are disposed between the copper bumps 311 and the second end surfaces of the first and second TSV regions 3021 and 3022.

Further, the upper and lower surfaces of the Si substrate 301 are provided with SiO₂An insulating layer.

Specifically, the first isolation region 3031 and the second isolation region 3032 are used for contacting SiO on the upper and lower surfaces of the Si substrate 301₂The insulating layer forms a closed isolation region to isolate the SCR tubes.

Preferably, the interconnect 309 is a copper interconnect.

The anti-static device provided by the embodiment has a simple structure, can bear very high ESD current by utilizing the low maintaining voltage of the SCR tube, has the characteristic of high ESD robustness naturally, and greatly improves the anti-static capability of the integrated circuit during system-in-package by arranging the SCR tube in the adapter plate.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For example, the plurality of isolation regions mentioned in the present invention are only illustrated according to the cross-sectional view of the device structure provided in the present invention, wherein the plurality of isolation regions may also be a first portion and a second portion shown in a cross-sectional view of a ring body as a whole, and it should not be limited to these descriptions for a person skilled in the art to which the present invention pertains, and several simple deductions or replacements can be made without departing from the spirit of the present invention, and all of them should be considered as belonging to the protection scope of the present invention.

Claims

1. A method for manufacturing an antistatic device for system-in-package (SIP), the method comprising:

s101, selecting a Si substrate;

s102, etching the Si substrate to form a TSV hole and an isolation trench respectively, wherein the depth of the TSV hole is the same as that of the isolation trench, and the TSV hole is 80-120 mu m;

s103, filling the isolation groove and the TSV to form an isolation region and a TSV region respectively;

s106, forming an interconnection line between the first end face of the TSV region and the SCR tube, wherein the interconnection line is a spiral copper interconnection line;

s107, preparing a metal salient point on the second end face of the TSV region to complete the preparation of the TSV adapter plate;

before S107, the method further includes:

x1, using an auxiliary wafer as a support of the upper surface of the Si substrate;

x3, utilizing a CMP process to carry out planarization treatment on the lower surface of the Si substrate until the second end face of the TSV region is exposed;

s104 specifically comprises the following steps:

s1041, forming SiO on the surface of the Si substrate by a thermal oxidation process at 1050-1100 ℃ temperature₂A buffer layer;

s1042, depositing Si on the surface of the Si substrate by LPCVD process at the temperature of 700-800 DEG C₃N₄A layer;

s1043, photoetching N well region, adopting ion implantation process with glueInjecting phosphorus, removing photoresist to form N well region of SCR tube with doping concentration of 1 × 10¹⁷cm^-3；

S1044, annealing the substrate for 2.5 hours at 950 ℃ to carry out N well propulsion;

s1045, removing Si on the surface of the substrate by using a wet etching process₃N₄A layer;

s1046, photoetching the P well region, adopting an ion implantation process with glue to perform boron implantation, removing the photoresist to form the P well region of the SCR tube, wherein the doping concentration is 1 multiplied by 10¹⁸cm^-3；

S1047, annealing the substrate for 2.5h at 950 ℃ to carry out P well propulsion.

2. The method according to claim 1, wherein S102 comprises:

s1022, etching the Si substrate by using a DRIE process to form the TSV and the isolation trench;

wherein the depth of the TSV and the isolation trench is less than the thickness of the Si substrate.

3. The method according to claim 1, wherein S103 comprises:

s1031, thermally oxidizing the TSV and the isolation trench to form an oxidation layer on the inner walls of the TSV and the isolation trench;

s1032, etching the oxide layer by utilizing a wet etching process to finish the planarization of the TSV and the inner wall of the isolation groove;

s1034, filling SiO in the isolation trench by using a CVD process₂Forming the isolation region;

s1035, forming a filling pattern of the TSV by utilizing a photoetching process;

s1036, filling a polysilicon material in the TSV by utilizing a CVD (chemical vapor deposition) process, and introducing a doping gas to carry out in-situ doping to form the TSV region.

4. The method according to claim 1, wherein S105 comprises:

s1051, photoetching the N trap contact area and the cathode pattern, and carrying out N by adopting an ion implantation process⁺Injecting and removing photoresist to form an N trap contact region and a cathode of the SCR tube;

s1052, photoetching the P well contact area and the anode pattern, and performing P by adopting an ion implantation process⁺And injecting and removing the photoresist to form a P trap contact area and an anode of the SCR tube.

5. The method according to claim 1, wherein S107 comprises:

s1072, depositing an insulating layer, photoetching a pattern of the metal bump on the second end face of the TSV region, depositing metal by using an electrochemical copper plating process, removing redundant metal by using a chemical mechanical polishing process, and forming the metal bump on the second end face of the TSV region;

s1073, removing the auxiliary wafer.

6. The production method according to claim 1, wherein the doping concentration of the Si substrate is 1 x 10¹⁴cm^-3The thickness is 150 to 250 μm.

7. The method of claim 6, wherein the TSV region and the isolation region have a depth of 80-120 μm.

8. An antistatic device for system-in-package, wherein the TSV interposer is prepared by the method of any one of claims 1-7.