CN208385403U - Anti-static device for system in package - Google Patents
Anti-static device for system in package Download PDFInfo
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- CN208385403U CN208385403U CN201721778943.2U CN201721778943U CN208385403U CN 208385403 U CN208385403 U CN 208385403U CN 201721778943 U CN201721778943 U CN 201721778943U CN 208385403 U CN208385403 U CN 208385403U
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- triode
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- tsv
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- interconnection line
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- 239000000758 substrate Substances 0.000 claims abstract description 61
- 239000010949 copper Substances 0.000 claims abstract description 27
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052802 copper Inorganic materials 0.000 claims abstract description 26
- 239000000463 material Substances 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 10
- 229910052721 tungsten Inorganic materials 0.000 claims description 10
- 239000010937 tungsten Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 58
- 230000000694 effects Effects 0.000 abstract description 11
- 238000005538 encapsulation Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 40
- 238000001259 photo etching Methods 0.000 description 30
- 230000008569 process Effects 0.000 description 26
- 239000003292 glue Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000012535 impurity Substances 0.000 description 10
- 229910052681 coesite Inorganic materials 0.000 description 9
- 229910052906 cristobalite Inorganic materials 0.000 description 9
- 238000002360 preparation method Methods 0.000 description 9
- 229910052682 stishovite Inorganic materials 0.000 description 9
- 229910052905 tridymite Inorganic materials 0.000 description 9
- 238000011161 development Methods 0.000 description 8
- 230000018109 developmental process Effects 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000004026 adhesive bonding Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000004913 activation Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000708 deep reactive-ion etching Methods 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000011946 reduction process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- ALKZAGKDWUSJED-UHFFFAOYSA-N dinuclear copper ion Chemical compound [Cu].[Cu] ALKZAGKDWUSJED-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
The utility model relates to a kind of anti-static devices for system in package, comprising: Si substrate (101), the area TSV (102), isolated area (103), triode (104), interconnection line (105), the first insulating layer (106), second insulating layer (107) and copper bump (108).The utility model forms the anti-static device of system in package by the way that triode is arranged on anti-static device as ESD protection device, it solves the problems, such as that the IC system grade encapsulation antistatic effect based on TSV technique is weak, enhances the antistatic effect of IC system grade encapsulation.
Description
Technical field
The utility model category semiconductor integrated circuit technology field, in particular to a kind of antistatic for system in package
Device.
Background technique
With computer, communication, the development of automotive electronics, aerospace industry and other consumer system regions, half-and-half
The requirement of the size and power consumption of conductor chip is continuously improved, needs smaller, thinner and lighter, highly reliable, multi-functional, low-power consumption
With the chip of low cost, three-dimensional packaging technology is come into being in this background.It has been reached in the packaging density of two-dimensional package technology
In the case where the limit, the advantage of more highdensity three-dimensional packaging technology is self-evident.
Three-dimension packaging (3D-TSV) based on through silicon via (Through-Silicon Via, abbreviation TSV) has high speed mutually
The features such as company, High Density Integration, miniaturization, while showing homogeneity and the advantages that heterogeneous function is integrated, becoming and partly lead in recent years
One of the research direction that body technique is most popular.Although 3D-TSV encapsulation technology have many advantages, at present there are still it is some not
Sharp factor restricts the development of 3D-TSV integrated packaging technology.
Pinboard typically refers to the functional layer of interconnection and pin redistribution between chip and package substrate.Pinboard can be with
Intensive I/O lead is redistributed, realizes the high density interconnection of multi-chip, it is macro with grade to become nanometer-grade IC
It sees electric signal between the world and connects one of most effective means.When realizing that multifunction chip is integrated using pinboard, not same core
The antistatic effect of piece is different, and the weak chip of antistatic effect influences whether that resisting for whole system after encapsulation is quiet when three-dimensional stacked
Electric energy power；Therefore the system in package antistatic effect for how improving the 3D-IC based on TSV technique becomes semicon industry urgently
It solves the problems, such as.
Utility model content
In order to improve the system in package antistatic effect of 3D integrated circuit, the utility model provides a kind of for system
The anti-static device of grade encapsulation；The technical problems to be solved in the utility model is achieved through the following technical solutions:
The embodiments of the present invention provide a kind of anti-static device for system in package, comprising:
Si substrate 101, the area TSV 102, isolated area 103, triode 104, interconnection line 105, the first insulating layer 106, second are absolutely
Edge layer 107 and copper bump 108: where
The area TSV 102, isolated area 103 and triode 104 are all set in Si substrate 101；The area TSV 102 is set to three poles
104 two sides of pipe；Isolated area 103 is set between triode 104 and the area TSV 102, is used in Si substrate 101 to triode
104 are isolated；Material in the area TSV 102 is copper；
First insulating layer 106 and second insulating layer 107 are respectively arranged at 101 upper and lower surfaces of Si substrate；Interconnection line
105 are set in the first insulating layer 106, for connecting the first end face and triode 104 in the area TSV 102；
Copper bump 108 is set in the second end face in the area TSV 102.
In one embodiment of the utility model, triode 104 includes: the buried layer of device trenches 1041, triode
1042, the emitter region 1045 in the collector contact area 1043 of triode, the base contact area 1044 of triode and triode；Its
In, the buried layer 1042 of triode is located at 1041 lower end of device trenches；The collector contact area 1043 of triode, triode base area
The emitter region 1045 of contact zone 1044 and triode is located in device trenches 1041.
In one embodiment of the utility model, the area TSV 102 includes the first area TSV and the 2nd area TSV, interconnection line
105 include the first interconnection line and the second interconnection line；The first end face in the first area TSV and the base contact area 1044 and three of triode
The emitter region 1045 of pole pipe is connected by the first interconnection line；The first end face in the 2nd area TSV and the collector contact area of triode
1043 are connected by the second interconnection line.
In one embodiment of the utility model, the base contact area 1044 of triode and the emitter region 1045 of triode
Tungsten plug is provided between the first interconnection line；It is respectively provided between the collector contact area 1043 and the second interconnection line of triode
There is tungsten plug.
In one embodiment of the utility model, the material of the first interconnection line and the second interconnection line is copper.
In one embodiment of the utility model, the area TSV 102 and isolated area 103 Si substrate 101 up and down.
Compared with prior art, the utility model has the following beneficial effects:
1, the utility model on anti-static device by being arranged ESD protection device --- and triode is formed for system-level
The anti-static device of encapsulation enhances the antistatic effect of laminate packaging chip；
2, the utility model, using the higher heat-sinking capability of pinboard, is mentioned by the way that triode is arranged on anti-static device
High current handling capacity in high device work；
3, have smaller around the triode of anti-static device provided by the utility model using isolated area up and down
Leakage current and parasitic capacitance.
Detailed description of the invention
It, below will be to required in embodiment description in order to illustrate more clearly of the technical solution of the utility model embodiment
The attached drawing used is briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the utility model
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of anti-static device structural schematic diagram for system in package provided by the embodiment of the utility model；
Fig. 2 is a kind of preparation method stream of the anti-static device for system in package provided by the embodiment of the utility model
Journey schematic diagram；
Fig. 3 a- Fig. 3 j is the preparation method flow chart of another anti-static device provided by the embodiment of the utility model.
Specific embodiment
Further detailed description, but the embodiment party of the utility model are done to the utility model combined with specific embodiments below
Formula is without being limited thereto.
Embodiment one
Referring to Figure 1, Fig. 1 is a kind of anti-static device knot for system in package provided by the embodiment of the utility model
Structure schematic diagram, comprising:
Si substrate 101, the area TSV 102, isolated area 103, triode 104, interconnection line 105, the first insulating layer 106, second are absolutely
Edge layer 107 and copper bump 108: where
The area TSV 102, isolated area 103 and triode 104 are all set in Si substrate 101；The area TSV 102 is set to three poles
104 two sides of pipe；Isolated area 103 is set between triode 104 and the area TSV 102, is used in Si substrate 101 to triode
104 are isolated；Material in the area TSV 102 is copper；
First insulating layer 106 and second insulating layer 107 are respectively arranged at 101 upper and lower surfaces of Si substrate；Interconnection line
105 are set in the first insulating layer 106, for connecting the first end face and triode 104 in the area TSV 102；
Copper bump 108 is set in the second end face in the area TSV 102.
Specifically, triode 104 include: device trenches 1041, the buried layer 1042 of triode, triode collector contact
The emitter region 1045 in area 1043, the base contact area 1044 of triode and triode；Wherein, the buried layer 1042 of triode is located at
1041 lower end of device trenches；Collector contact area 1043, the base contact area 1044 of triode and the hair of triode of triode
Area 1045 is penetrated to be located in device trenches 1041.
Preferably, the area TSV 102 includes the first area TSV and the 2nd area TSV, and interconnection line 105 includes the first interconnection line and second
Interconnection line；The emitter region 1045 of the first end face in the first area TSV and the base contact area 1044 of triode and triode passes through the
The connection of one interconnection line；The first end face in the 2nd area TSV and the collector contact area 1043 of triode are connected by the second interconnection line.
Preferably, it is arranged between the base contact area 1044 of triode and the emitter region 1045 of triode and the first interconnection line
There is tungsten plug；Tungsten plug is provided between the collector contact area 1043 and the second interconnection line of triode.
Preferably, the material of the first interconnection line and the second interconnection line is copper.
Preferably, the depth of device trenches 1041 is 15~25 μm.
Preferably, the first insulating layer 106 and the material of second insulating layer 107 are SiO2。
Preferably, the doping type of Si substrate 101 is N-type, and doping concentration is 1 × 1015cm-3, with a thickness of 80~120 μm.
Specifically, the area TSV 102 and isolated area 103 Si substrate 101 up and down.
Anti-static device provided in this embodiment, by the way that ESD protection device --- three poles are arranged on through silicon via pinboard
Pipe, enhances the antistatic effect of laminate packaging chip；The weak chip of antistatic effect influences whether when solving three-dimensional stacked
After encapsulation the problem of the antistatic effect of whole system；Meanwhile the present embodiment provides utilize around the triode of anti-static device
Isolated area up and down has lesser leakage current and parasitic capacitance.
Embodiment two
Fig. 2 is referred to, Fig. 2 is a kind of anti-static device for system in package provided by the embodiment of the utility model
Preparation method flow diagram, comprising:
S101, Si substrate is chosen；
S102, triode is prepared in Si substrate；
S103, etching Si substrate form isolated groove and TSV in triode two sides respectively；
S104, SiO is filled in isolated groove2Form isolated area；
S105, the area TSV is formed in TSV filling copper product；
S106, on a si substrate surface prepare the first end face in the area TSV and the interconnection line of triode；
S107, the second end face in the area TSV prepare metal salient point to complete the preparation of TSV pinboard.
Specifically, the doping type of Si substrate (101) is N-type, and doping concentration is 1 × 1015cm-3, with a thickness of 150~250
μm。
Preferably, S102 may include:
S1021, device etching groove figure is formed using photoetching process；
S1022, dry etch process, etching Si substrate formation device trenches are utilized；
S1023, photoetching buried layer area carry out N using band glue ion implantation technology+Ion implanting removes photoresist, forms three
The buried layer of pole pipe；
S1024, the collector contact area for preparing triode respectively, base contact area and emitter region.
Further, S1024 may include:
S10241, device trench fill figure is formed using photoetching process；
S10242, using CVD technique, deposit silicon materials and device trenches filled, and be passed through impurity gas and carry out in situ mix
It is miscellaneous, the collecting zone in situ for activating doped chemical to form triode；
S10243, photoetching collector contact area carry out N using band glue ion implantation technology+Ion implanting removes photoetching
Glue forms collector contact area；
S10244, photoetching base area carry out P using band glue ion implantation technology+Ion implanting removes photoresist, forms three
Pole pipe base area；
S10245, photoetching base contact area carry out P using band glue ion implantation technology+Ion implanting removes photoresist,
Form base contact area；
S10246, photoetching emitter region carry out N using band glue ion implantation technology+Ion implanting removes photoresist, is formed
Emitter region.
Preferably, the depth of device trenches is 15~25 μm.
Preferably, S103 may include:
S1031, using photoetching process, form the etched features of TSV and isolated groove in the upper surface of Si substrate；
S1032, DRIE technique, etching Si substrate formation TSV and isolated groove are utilized.
Preferably, S105 may include:
S1051, the filling figure that TSV is formed using photoetching process；
S1052, adhesion layer and seed layer are made using physical vapor deposition methods；
S1053, copper product is filled to TSV to form the area TSV by the method for electrochemical deposition.
Preferably, before S107 further include:
X1, using auxiliary disk as the supporting element of Si upper surface of substrate；
X2, thinned, recycling CMP technique, to Si substrate is carried out to Si substrate lower surface using mechanical grinding reduction process
Lower surface carry out planarizing process, until expose the area TSV second end face.
Preferably, the depth of the area TSV and isolated area is 80~120 μm.
The preparation flow of anti-static device provided in this embodiment can be completed on prior art platform, and preparation is simple
It is applied widely；By processing triode on TSV pinboard, the antistatic effect of laminate packaging chip is enhanced；Meanwhile this
Isolated area up and down is provided around the triode of embodiment offer TSV pinboard, there is lesser leakage current and parasitism
Capacitor.
Embodiment three
The present embodiment on the basis of the above embodiments, to specific in the preparation method of the anti-static device of the utility model
Parameter citing is described as follows.Specifically, a- Fig. 3 j, Fig. 3 a- Fig. 3 j are provided by the embodiment of the utility model another referring to figure 3.
The preparation method flow chart of kind anti-static device,
S201, as shown in Figure 3a, selection Si substrate 201；
Preferably, the crystal orientation of Si substrate can be (100), (110) or (111), and doping type is N-type, and Si substrate is mixed
Miscellaneous concentration is 1 × 1015cm-3, with a thickness of 150~250 μm.
S202, as shown in Figure 3b；It forms device trenches 202 on a si substrate using etching technics, recycles ion implanting
The N of technique formation triode+Buried layer 203, can specifically include following steps:
S2021, using CVD technique, deposit silicon nitride layer on a si substrate；
S2022, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete device trenches etched features；
S2023, device trenches are formed using dry etch process etch nitride silicon layer and Si substrate；The depth of device trenches
It is 15~25 μm；
S2024, using CMP process, the silicon nitride removed on Si substrate planarizes substrate surface；
S2025, in device trenches bottom photoetching N+Buried layer carries out N by the way of with glue ion implanting+Ion implanting is gone
Except photoresist, the N of triode is formed+Buried layer；Doping concentration preferably 5 × 1018cm-3, the preferred phosphorus of impurity.
S203, as shown in Figure 3c；The collector contact area 204 for preparing triode, can specifically include following steps:
S2031, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete device trenches and fill figure；
S2032, using low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition,
LPCVD) technique, 600 DEG C~950 DEG C at a temperature of, utilize selective silicon epitaxial growth method selective epitaxial growth silicon material
Material, while being passed through impurity gas and carrying out doping in situ, and realizing the activation in situ of doped chemical, form the collecting zone of triode.
Doping concentration preferably 5 × 1017cm-3, the preferred phosphorus of impurity；
S2033, using CMP process, substrate surface is planarized；
S2034, photoetching collector contact area carry out N+ ion implanting by the way of with glue ion implanting, remove photoetching
Glue forms the collector contact area of triode；Doping concentration preferably 1 × 1019cm-3, the preferred phosphorus of impurity；
S2035, by substrate at a temperature of 950~1100 DEG C, anneal 15~120s, carry out impurity activation.
S204, as shown in Figure 3d；Base contact area 205 and the emitter region 206 for preparing triode, can specifically include as follows
Step:
S2041, photoetching base area, carry out N by the way of with glue ion implanting+Ion implanting removes photoresist, forms three
The base area of pole pipe.Doping concentration preferably 5 × 1018cm-3, the preferred boron of impurity；
S2042, photoetching base contact area, carry out P by the way of with glue ion implanting+Ion implanting removes photoresist,
Form the base contact area of triode.Doping concentration preferably 1 × 1021cm-3, the preferred boron of impurity；
S2043, photoetching N+Emitter region carries out N by the way of with glue ion implanting+Ion implanting removes photoresist, shape
At the N of triode+Emitter region.Doping concentration preferably 1 × 1021cm-3, the preferred phosphorus of impurity；
S2044, by substrate at a temperature of 950~1100 DEG C, anneal 15~120s, carry out impurity activation.
S205, as shown in Figure 3 e, prepare four TSV207 and four isolated grooves on a si substrate using etching technics
208, it may include steps of:
S2051,1050 DEG C~1100 DEG C at a temperature of, utilize thermal oxidation technology on a si substrate surface grow one layer
The SiO of 800nm~1000nm2Layer；
S2052, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete TSV and isolated groove etched features；
S2053, Si substrate is etched using DRIE technique, forms TSV and isolated groove that depth is 80~120 μm；
S2054, using CMP process, remove the SiO on Si substrate2, substrate surface is planarized.
S206, as illustrated in figure 3f；Using CVD technique, SiO is deposited on a si substrate2Isolated groove is filled to be formed
Isolated area can specifically include following steps:
S2061,1050 DEG C~1100 DEG C at a temperature of, the inner wall of thermal oxide TSV and isolated groove formed with a thickness of
The oxide layer of 200nm~300nm；
S2062, using wet-etching technology, etch the oxide layer of the inner wall of TSV and isolated groove to complete TSV and isolation
The planarizing of trench wall.To prevent the protrusion of TSV and isolated groove side wall from forming electric field concentrated area；
S2063, using photoetching process, pass through the techniques such as gluing, photoetching, development and complete isolated groove and fill figure；
S2064,690 DEG C~710 DEG C at a temperature of, utilize LPCVD technique, deposit SiO2Isolated groove is filled out
It fills, forms isolated area；It is understood that the SiO2Material is mainly used for isolating, can by undoped polycrystalline silicon etc. other
Material substitution；
S2065, using CMP process, substrate surface is planarized.
S207, as shown in figure 3g；TSV is filled using copper plating process, can specifically include following steps:
S2071, adhesion layer and seed layer are made using physical vapor deposition methods, the material of adhesion layer is titanium or tantalum, kind
The material of sublayer is copper；
S2072, copper product is filled in TSV by the method for electrochemical deposition；
S2073, CMP process, the extra metal layer of removal substrate surface are utilized.
S208, as illustrated in figure 3h；Using electroplating technology, surface forms copper interconnecting line 209 on a si substrate, specifically can wrap
Include following steps:
S2081, plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor is utilized
Deposition, PECVD) technique, SiO is deposited in substrate surface2Layer；
S2082, in the first end in the area TSV and collector contact area, base contact area and the emitter region of triode, utilize
Photoetching process completes contact hole graph by techniques such as gluing, photoetching, developments；
S2083, using CVD technique, the collector contact area, base contact area and emitter region of triode deposit Ti film,
TiN film and tungsten are to form tungsten plug；
S2084, substrate surface is planarized using CMP process；
S2085, deposit SiO2Insulating layer, photoetching copper-connection figure deposit copper, passing through using the method for Cu electroplating
The method for learning mechanical lapping removes extra copper, and the first end for forming the area TSV concatenates copper interconnecting line with triode；
S2086, substrate surface is planarized using CMP process.
Further, it when preparing copper interconnecting line, surrounds spiral using metal interconnecting wires and makes it have inductance
Characteristic to be more particularly for the electrostatic protection of RF IC.
S209, as shown in figure 3i；Thinned, the leakage area TSV is carried out to Si substrate using CMP process, specifically
It may include steps of:
S2091, Si upper surface of substrate and auxiliary wafer bonding are passed through into auxiliary using high molecular material as middle layer
Being thinned for Si substrate is completed in the support of disk；
S2092, Si substrate lower surface is carried out using mechanical grinding reduction process it is thinned, until reduce to be slightly larger than the area TSV
The thickness of depth, preferably greater than 10 μm of TSV depth；
S2093, using CMP process to Si substrate lower surface carry out it is smooth, until expose the area TSV；
S210, as shown in Fig. 3 j；Copper bump 210 is formed using electric plating method in Si substrate lower surface, specifically can wrap
Include following steps:
S2101, using pecvd process, deposit SiO in substrate lower surface2Layer；
S2102, the second end in the area TSV complete contact hole by techniques such as gluing, photoetching, developments using photoetching process
Figure；
S2103, using CVD technique, the area TSV second end deposit Ti film, TiN film and tungsten to form tungsten plug；
S2104, substrate surface is planarized using CMP process；
S2105, deposit SiO2Insulating layer, the second end photoetching copper bump figure in the area TSV, utilizes electrochemical plating process for copper
Copper is deposited, extra copper is removed by chemical mechanical milling tech, etches SiO2Layer, the second end in the area TSV form copper bump；
S2106, the auxiliary disk being temporarily bonded is removed using the method for heated mechanical.
The preparation method of anti-static device provided in this embodiment, using triode device periphery by SiO2Insulating layer surrounds
Technique, the parasitic capacitance between active area and substrate can be effectively reduced.The utility model is on the basis of considering technological feasibility
The hole TSV by optimal setting certain length and the doping concentration using given range, and consider that the electric current of device passes through energy
Power reduces parasitic capacitance and resistance, and the inductance introduced using the hole TSV carries out a degree of tune to the parasitic capacitance of device
It is humorous, the working range of esd protection circuit is expanded while raising system in package anti-ESD ability.
It, cannot the above content is specific preferred embodiment further detailed description of the utility model is combined
Assert that the specific implementation of the utility model is only limited to these instructions.For example, the multiple isolated areas referred in the utility model are only
It is only to be illustrated according to device architecture sectional view provided by the utility model, wherein multiple isolated areas are also possible to some
The first part and second part that the sectional view of such as ring bodies is shown in entirety, for the utility model technical field
It for those of ordinary skill, should not be limited to these explanations, without departing from the concept of the premise utility, can also make
Several simple deduction or replace, all shall be regarded as belonging to the protection scope of the utility model.
Claims (5)
1. a kind of anti-static device for system in package characterized by comprising Si substrate (101), the area TSV (102),
Isolated area (103), triode (104), interconnection line (105), the first insulating layer (106), second insulating layer (107) and copper bump
(108): where
The area TSV (102), the isolated area (103) and the triode (104) are all set in the Si substrate (101)；
The area TSV (102) is set to the triode (104) two sides；The isolated area (103) is set to the triode (104)
Between the area TSV (102), for the triode (104) to be isolated in the Si substrate (101)；The TSV
Material in area (102) is copper；
First insulating layer (106) and the second insulating layer (107) be respectively arranged at Si substrate (101) upper surface and
Lower surface；The interconnection line (105) is set in first insulating layer (106), for connecting the of the area TSV (102)
One end face and the triode (104)；
The copper bump (108) is set in the second end face of the area TSV (102).
2. anti-static device according to claim 1, which is characterized in that the triode (104) includes: device trenches
(1041), the base contact area (1044) of the buried layer (1042) of triode, the collector contact area (1043) of triode, triode
With the emitter region (1045) of triode；Wherein, the buried layer (1042) of the triode is located at the device trenches (1041) lower end；
The transmitting in the collector contact area (1043), base contact area (1044) and the triode of the triode of the triode
Area (1045) is located in the device trenches (1041).
3. anti-static device according to claim 2, which is characterized in that the area TSV (102) include the first area TSV and
2nd area TSV, the interconnection line (105) include the first interconnection line and the second interconnection line；The first end face in the first area TSV with
The base contact area (1044) of the triode is connected with the emitter region (1045) of the triode by first interconnection line；
The first end face in the 2nd area TSV and the collector contact area (1043) of the triode are connected by second interconnection line
It connects.
4. anti-static device according to claim 3, which is characterized in that the base contact area (1044) of the triode and
Tungsten plug is provided between the emitter region (1045) and first interconnection line of the triode；The collector of the triode connects
Tungsten plug is provided between touching area (1043) and second interconnection line.
5. anti-static device according to claim 1, which is characterized in that the area TSV (102) and the isolated area
(103) the Si substrate (101) up and down.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721778943.2U CN208385403U (en) | 2017-12-15 | 2017-12-15 | Anti-static device for system in package |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721778943.2U CN208385403U (en) | 2017-12-15 | 2017-12-15 | Anti-static device for system in package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108074923A (en) * | 2017-12-15 | 2018-05-25 | 西安科锐盛创新科技有限公司 | For the anti-static device of system in package |
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2017
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108074923A (en) * | 2017-12-15 | 2018-05-25 | 西安科锐盛创新科技有限公司 | For the anti-static device of system in package |
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