JP2010186870A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily find out an anomaly of an electrode pad. <P>SOLUTION: A semiconductor device includes: a semiconductor substrate 10; a first through electrode 25 formed in a first through hole 80 bored from a first surface in a first region of the semiconductor substrate to a second surface facing the first surface; a first electrode pad 28 formed in contact with the first through electrode on the first surface of the semiconductor substrate; a second electrode pad 29 formed away from the first electrode pad and facing the first electrode pad; an external terminal 27 formed on the second surface of the semiconductor substrate and electrically connected to the first through electrode; and a third electrode pad 28 formed on a second through hole 80 bored from the first surface in a second region different from the first region of the semiconductor substrate to the second surface on the first surface of the semiconductor substrate and electrically floating. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device including an electrically floating electrode pad.

  Along with miniaturization of electronic equipment, semiconductor devices to be mounted need to be miniaturized and highly integrated. In the second half of the 1990s, the practical application of Wafer Level Chip Scale Package (wafer level CSP) has begun. The wafer level CSP is a flip chip type in which lead wires are arranged, and the semiconductor chip surface is faced downward and bonded to the substrate by bumps.

  In addition, since the late 1990s, development of stacked packages (multi-chip packages) has been underway, in which a plurality of semiconductor chips can be stacked three-dimensionally to achieve significant downsizing, and a package using through electrodes has been proposed. (For example, refer to Patent Document 1). The study of wafer level CSP for optical elements begins around 2000. Non-Patent Document 1 describes a structure of glass + adhesive layer + image sensor + penetrating electrode and a cross-sectional photograph actually created by Koyanagi et al.

  By the way, when a wafer level CSP is created by an optical element, the optical element is first created in a wafer state, and the quality of each chip is determined by a die sort test. At this time, the needle of the die sort tester hits the electrode pad existing in the uppermost layer of the optical element, and a mark always remains on the electrode pad. When the cross section of the trace of the electrode pad is observed, the electrode pad is greatly recessed. When there is only one electrode pad, if this electrode pad is used for both the die sort test and the stopper for anisotropic etching, the part that is scratched and thinned by the die sort test does not function as a stopper, and is anisotropic. There arises a disadvantage that the etching breaks through the electrode pad. In order to avoid this, it is necessary to separate the electrode pad used in the die sort test and the electrode pad used as a stopper for anisotropic etching.

  For example, aluminum (Al) is used for this electrode pad. If Al is left in the air, it may react with moisture to cause oxidation called corrosion. The electrode pad used in the uppermost die sort test has no shielding, so it can be easily detected even if an abnormality occurs by leaving it in the air. However, the electrode pad serving as a stopper for the through electrode cannot be seen directly behind the electrode pad used in the die sort test. For this reason, for example, even if the electrode pad reacts with moisture in the air after the through hole is formed and an abnormality occurs, the abnormality cannot be easily found after the through electrode is formed.

JP-A-10-223833

International Electron Devices Meeting 1999 Technical Digest pp.879-882

  The present invention provides a semiconductor device capable of easily detecting an abnormality of an electrode pad.

  A semiconductor device according to an aspect of the present invention includes a semiconductor substrate and a first through hole formed in the first through hole formed from the first surface in the first region of the semiconductor substrate to the second surface opposite to the first surface. 1 through electrode, a first electrode pad formed on and in contact with the first through electrode on the first surface of the semiconductor substrate, and spaced apart from the first electrode pad, and the first electrode pad An opposing second electrode pad; an external terminal formed on the second surface of the semiconductor substrate and electrically connected to the first through electrode; and the semiconductor substrate on the first surface of the semiconductor substrate. A third electrode pad that is formed on a second through hole that is formed from the first surface to the second surface in a second region different from the first region, and is electrically floating.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which can discover abnormality of an electrode pad easily can be provided.

Sectional drawing which shows the camera module which concerns on each embodiment of this invention. The process flow which shows the manufacturing process of the camera module which concerns on embodiment of this invention. 1 is a plan view showing a wafer level silicon substrate in a camera module according to a first embodiment of the present invention. Sectional drawing which shows the silicon substrate along the IV-IV line in FIG. Sectional drawing which shows the silicon substrate along the VV line in FIG. Sectional drawing which shows the silicon substrate along the VI-VI line in FIG. Sectional drawing which shows the modification of the silicon substrate in FIG. Sectional drawing which shows the manufacturing process of the wafer level silicon substrate in the camera module which concerns on the 1st Embodiment of this invention. FIG. 9 is a cross-sectional view illustrating the manufacturing process of the wafer level silicon substrate in the camera module according to the first embodiment of the present invention, following FIG. 8. Sectional drawing which shows the manufacturing process of the wafer level silicon substrate in the camera module which concerns on the 1st Embodiment of this invention following FIG. Sectional drawing which shows the manufacturing process of the wafer level silicon substrate in the camera module which concerns on the 1st Embodiment of this invention following FIG. FIG. 12 is a cross-sectional view showing the manufacturing process of the wafer level silicon substrate in the camera module according to the first embodiment of the present invention, following FIG. 11. Sectional drawing which shows the manufacturing process of the wafer level silicon substrate in the camera module which concerns on the 1st Embodiment of this invention following FIG. FIG. 14 is a cross-sectional view showing the manufacturing process of the wafer level silicon substrate in the camera module according to the first embodiment of the present invention, following FIG. 13. The top view which shows the silicon substrate of the wafer level in the camera module which concerns on the 2nd Embodiment of this invention. Sectional drawing which shows the silicon substrate along the XVI-XVI line in FIG. The top view which shows the silicon substrate of the wafer level in the camera module which concerns on the 3rd Embodiment of this invention. Sectional drawing which shows the silicon substrate along the XVIII-XVIII line in FIG.

  Embodiments of the present invention will be described below with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

[1] Camera Module Here, as a semiconductor device according to each embodiment of the present invention, a camera module including a glass substrate and a silicon substrate having an imaging element and a through electrode is taken as an example.

[1-1] Structure of Camera Module First, the structure of the camera module according to each embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a configuration of a camera module according to each embodiment of the present invention.

  As shown in FIG. 1, the camera module includes a silicon substrate (imaging device chip) 10, a glass substrate (cover glass) 23, a solder ball 27, an infrared cut glass (IR cut glass) 40, an infrared cut film (IRCF) 41, A light shielding / electromagnetic shield 70, an imaging lens 50, and a lens holder 60 are provided.

  An imaging element and a through electrode (not shown) are formed in the silicon substrate 10. A glass substrate 23 is formed on the first surface of the silicon substrate 10 with an adhesive 33 interposed therebetween. An IR cut glass 40 is formed on the glass substrate 23 via an adhesive 34, and an IRCF 41 is formed on the IR cut glass 40. A lens holder 60 including the imaging lens 50 is placed on the IRCF 41 via an adhesive 35. A camera module is configured by bonding them together.

  An external terminal, for example, a solder ball 27 is formed on the second surface opposite to the first surface of the silicon substrate 10. A light shielding / electromagnetic shield 70 is disposed around the silicon substrate 10 and the glass substrate 23, and the light shielding / electromagnetic shield 70 is bonded to the lens holder 60 with an adhesive 36.

[1-2] Camera Module Manufacturing Method Next, a camera module manufacturing method according to each embodiment of the present invention will be briefly described. FIG. 2 is a process flow showing a manufacturing method of the camera module of FIG.

  First, a solid-state imaging device (not shown) is formed on a wafer level silicon substrate (silicon wafer) 10 (step S1). That is, an image pickup device including a photodiode and a transistor is formed on the first surface of the silicon substrate 10. Furthermore, an internal electrode (not shown), an interlayer insulating film (not shown), an element surface electrode (not shown), a color filter (not shown), and a micro lens (see FIG. Not shown).

  Next, a die sort test is performed on each chip including the image sensor to check whether each chip operates normally (step S2). In this die sort test, a tester needle is applied to the element surface electrode.

  Next, the adhesive 33 is formed on the first surface of the silicon substrate 10 by spin coating or laminating (step S3). The adhesive 33 has not only an adhesive function but also a function capable of patterning by lithography and a function of maintaining a patterning shape. The adhesive 33 is patterned so as to be removed from the image pickup device by lithography, that is, not formed.

  Next, the first surface of the silicon substrate 10 with the adhesive 33 is bonded to the glass substrate 23 (step S4).

  Next, the silicon substrate 10 is shaved and thinned from the second surface side by back grinding or the like (step S5). At this time, unevenness is left on the second surface of the silicon substrate 10 after backgrinding. For this reason, in the next lithography and RIE process, there is a possibility that a lithography defect and an RIE defect may occur. Therefore, it is desirable to planarize the second surface of the silicon substrate 10 by CMP (Chemical Mechanical Polish), wet etching, or the like.

Next, through holes (not shown) are formed from the second surface to the first surface of the silicon substrate 10 by RIE. (Step S6)
Next, an insulating film is formed on the second surface and the through hole of the silicon substrate 10 by a CVD (Chemical Vapor Deposition) method or the like (step S7). Thereafter, a part of the insulating film at the bottom of the through hole is etched to expose the internal electrode (step S8).

  Next, a metal seed layer is formed on the insulating film and the exposed internal electrode by sputtering. Thereafter, the metal seed layer is plated by electroplating or the like to form a through electrode (step S9).

  Next, a solder resist is formed on the entire second surface of the silicon substrate 10 by spin coating or the like. Next, the solder resist in the region where the solder balls 27 are placed is opened by lithography (step S10). Thereafter, a continuity check is performed (step S11), and a solder ball is placed on the through electrode in the opening portion of the solder resist (step S12).

  Finally, the silicon substrate 10 and the glass substrate 23 are separated into pieces by dicing (step S13), pickup (step S14), mounting of the lens 50 (step S15), and image check (lens adjustment) (step S16) are performed. Is called. Thus, the camera module is packed (step S17), and the manufacturing of the camera module is completed.

[2] First Embodiment The first embodiment is an example in which a region in which only one electrode pad that is electrically floating is provided in an imaging element chip is formed in a silicon wafer in the manufacturing process of a camera module. . The semiconductor device according to the first embodiment will be described below.

[2-1] Structure of Silicon Substrate The structure of the silicon substrate in the camera module will be described below. FIG. 3 is a plan view of a part of the silicon substrate of the wafer level CMOS sensor in this embodiment as viewed from the glass substrate side. Here, a glass substrate, an adhesive, and a color filter / microlens layer to be described later are not shown. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a cross-sectional view taken along line VV in FIG. 6 and 7 are cross-sectional views taken along line VI-VI in FIG.

  First, the planar structure of the silicon substrate will be described with reference to FIG. As shown in FIG. 3, the image pickup device chip 1 is formed by being divided by a dicing line 2. The imaging device chip 1 includes a pixel unit 3 and electrode pads 4 and 5.

  The pixel unit 3 is formed at the center of the image sensor chip 1. A plurality of electrode pads 4 and 5 are formed in the X direction at the end of the image sensor chip 1. Here, the electrode pad 4 shown by a solid line in FIG. 3 is a pad for taking out the signal of the pixel unit 3 to the outside, and has two layers of electrode pads of an element surface electrode 29 and an internal electrode 28 described later. Yes. The region where the electrode pad 4 is provided is hereinafter referred to as a two-layer electrode pad region (1) and (3). On the other hand, an electrode pad 5 indicated by a broken line in FIG. 3 is a dummy pad for finding an abnormality of the electrode pad, and has a single electrode pad of only an internal electrode 28 described later. The region where the electrode pad 5 is provided is hereinafter referred to as a dummy electrode pad region (2). The electrode pads 5 are formed in gaps between a plurality of electrode pads 4 formed in the imaging element chip 1.

  Next, a cross-sectional structure along the X direction will be described with reference to FIG. As shown in FIG. 4, the silicon substrate 10 is provided with through holes 80 from the first surface to the second surface. An insulating film 24 is formed on the inner surface of the through hole 80 and on the second surface of the silicon substrate 10. A through electrode 25 is formed on the insulating film 24. The through electrode 25 is discontinuous by being divided on the second surface of the silicon substrate 10 for each through hole 80. A protective film such as a solder resist 26 is formed on the through electrode 25 and the insulating film 24. The solder resist 26 is made of, for example, a phenol resin, a polyimide resin, or an amine resin.

  A first interlayer insulating film 13 is formed on the first surface of the silicon substrate 10. The first interlayer insulating film 13 is composed of, for example, a silicon oxide film or a silicon nitride film. Further, the through electrode 25 formed in the through hole 80 penetrates the first surface of the silicon substrate 10 and protrudes from the first surface of the silicon substrate 10. An internal electrode 28 electrically connected to the through electrode 25 is formed on the through electrode 25. A first interlayer insulating film 13 is formed on the internal electrode 28. A second interlayer insulating film 17 is partially formed on the first interlayer insulating film 13. A color filter / microlens layer 21 is formed on the second interlayer insulating film 17. The second interlayer insulating film 17 and the color filter / microlens layer 21 are opened on the central portion of the internal electrode 28 to form a pad opening 32. A glass substrate 23 is formed on the color filter / microlens layer 21 and the pad opening 32 via an adhesive 33.

  Here, in the present embodiment, in the two-layer electrode pad regions (1) and (3), the element surface electrode 29 is formed above the internal electrode 28, and in the dummy electrode pad region (2), the internal electrode 28 is formed. The element surface electrode 29 does not exist above. Thereby, the internal electrode 28 in the dummy electrode pad region (2) can be observed through the glass substrate 23, the adhesive 33, and the first interlayer insulating film 13. The element surface electrodes 29 in the two-layer electrode pad regions (1) and (3) are arranged to be separated from the internal electrode 28 and to face the internal electrode 28. The element surface electrode 29 is exposed from the pad opening 32 of the color filter / microlens layer 21 and used for the die sort test.

  In the dummy electrode pad region (2), the pad opening 32 is not formed, and the second interlayer insulating film 17 and the color filter / microlens layer 21 are continuously formed on the first interlayer insulating film 13. Also good. Even in this case, the internal electrode 28 can be observed from the glass substrate 23 side. In the dummy electrode pad region (2), at least the internal electrode 28 may be formed, and the through electrode 25 connected to the internal electrode 28 may not be formed.

  Next, a cross-sectional structure along the Y direction orthogonal to the X direction of the two-layer electrode pad region (1) will be described with reference to FIG. As shown in FIG. 5, the camera module includes an imaging pixel unit in which the imaging element 12 is formed, and a peripheral circuit unit that processes a signal output from the imaging pixel unit.

  In the imaging pixel portion of the camera module, an STI (Shallow Trench Isolation) 11 as an element isolation insulating layer and an element region partitioned by the STI 11 are arranged on the first surface of the silicon substrate 10. In this element region, an imaging element 12 including a photodiode and a transistor is formed. A first interlayer insulating film 13 is formed on the first surface on which the image sensor 12 is formed. A wiring 14 is formed in the first interlayer insulating film 13. A passivation film 15 is formed on the first interlayer insulating film 13, and a base layer 16 is formed on the passivation film 15. The passivation film 15 and / or the base layer 16 corresponds to the second interlayer insulating film 17 in FIG. On the base layer 16, color filters 18 are arranged so as to correspond to the image sensor 12. An overcoat 19 is formed on the color filter 18. Microlenses 20 are formed on the overcoat 19 so as to correspond to the image pickup device 12 and the color filter 18, and a styrene resin layer 31 is formed on the overcoat 19 in a region where the image pickup device 12 does not exist. Has been. The color filter 18, overcoat 19, microlens 20 and / or styrene resin layer 31 correspond to the color filter / microlens layer 21 of FIG. 4. A cavity 22 is formed on the microlens 20, and a glass substrate 23 is disposed on the cavity 22.

  Here, the STI 11 is made of, for example, a silicon oxide film. The wiring 14 is made of, for example, aluminum (Al), the color filter 18 is made of, for example, acrylic resin, and the microlens 20 is made of, for example, styrene resin.

  In the peripheral circuit portion of the camera module, a through hole 80 is provided in the silicon substrate 10 from the first surface to the second surface, and an insulating film 24 is formed on the inner surface of the through hole 80 and on the second surface of the silicon substrate 10. Is formed. A through electrode 25 is formed on the insulating film 24, and a protective film such as a solder resist 26 is formed on the through electrode 25. Further, a part of the solder resist 26 on the through electrode 25 is opened, and the through electrode 25 is exposed. An external terminal such as a solder ball 27 is connected to the exposed through electrode 25.

  A first interlayer insulating film 13 is formed on the first surface of the silicon substrate 10. The through electrode 25 formed in the through hole 80 protrudes from the first surface of the silicon substrate 10, and the internal electrode 28 is formed on the through electrode 25. The internal electrode 28 is electrically connected to a peripheral circuit (not shown) formed in the image sensor 12 or the peripheral circuit section. Thus, the through electrode 25 electrically connects the solder ball 27, the imaging element 12, and the peripheral circuit.

  Further, an element surface electrode 29 is formed on the internal electrode 28 via the first interlayer insulating film 13. In the first interlayer insulating film 13 between the internal electrode 28 and the element surface electrode 29, a contact plug 30 for electrically connecting these electrodes is formed. The element surface electrode 29 is used for voltage application and signal readout via the contact plug 30 and the internal electrode 28. In particular, a needle is applied to the element surface electrode 29 during the die sort test.

  A passivation film 15 is formed on the end portion on the element surface electrode 29. A base layer 16 is formed on the passivation film 15, and an overcoat 19 is formed on the base layer 16. A styrene resin layer 31 is formed on the overcoat 19. The passivation film 15, the base layer 16, the overcoat 19, and the styrene resin layer 31 are opened on the center portion of the element surface electrode 29, and a pad opening portion 32 is formed.

  A glass substrate 23 is formed on the styrene resin layer 31 and the element surface electrode 29 via an adhesive 33. The adhesive 33 is patterned and is not disposed on the image sensor 12 and the microlens 20.

  The contact plug 30 is disposed at a position that does not overlap the pad opening 32 or the through hole 80 in a direction perpendicular to the surface of the silicon substrate 10. As a result, the contact plug 30 is not formed over the entire area between the internal electrode 28 and the element surface electrode 29, so that the space between these electrodes is not strengthened. Therefore, a part of the element surface electrode 29 or the internal electrode 28 enters the silicon substrate 10 to destroy the camera module, and the element surface electrode 29 and the internal electrode 28 are separated from the silicon substrate 10 when the needle is released. Problems such as peeling can be reduced.

  Here, an example is shown in which two electrode pads (internal electrode 28, element surface electrode 29) are arranged, but it is sufficient that at least two electrode pads are arranged. For example, one or a plurality of electrode pads may be disposed in the first interlayer insulating film 13 between the internal electrode 28 and the element surface electrode 29. Thereby, even when the element surface electrode 29 is damaged by the die sort test, the internal electrode 28 can be used as an etching stopper in the anisotropic etching when the through hole 80 is formed in the silicon substrate 10.

  Further, although an example in which three layers of wirings 14 are formed in the first interlayer insulating film 13 is shown, the present invention is not limited to this.

  Further, in the pad opening 32 on the element surface electrode 29, the positions of the opening end of the passivation film 15 and the opening ends of the base layer 16, the overcoat 19, and the styrene resin layer 31 are different and stepped. These opening ends may be formed so that the positions thereof coincide with each other. Further, there may be a step between the opening end of the overcoat 19 and the opening end of the styrene-based resin layer 31, or there may be no step.

  Next, a cross-sectional structure along the Y direction of the dummy electrode pad region (2) will be described with reference to FIGS. As shown in FIG. 6, the element surface electrode 29 and the contact plug 30 do not exist on the internal electrode 28 in the dummy electrode pad region (2) with respect to the two-layer electrode pad region (1). Further, the solder resist 26 on the through electrode 25 is not opened, and the solder ball 27 is not formed. For this reason, the through electrode 25 and the internal electrode 28 are in an electrically floating state. That is, the internal electrode 28 and the through electrode 25 in the dummy electrode pad region (2) do not have a function as a device.

  In addition, as shown in FIG. 7, even if the pad opening 32 is not formed and the passivation film 15, the base layer 16, the overcoat 19, and the styrene resin layer 31 are continuously formed on the first interlayer insulating film 13. Good.

  Each member on the first surface of the silicon substrate 10 shown in FIGS. 3 to 7 is formed in the solid-state imaging device manufacturing process in step S1 of FIG. 2 described above. At this time, each part of the two-layer electrode pad regions (1) and (3) and the dummy electrode pad region (2) is formed at the same time, but the element surface electrode 29 is formed in the two-layer electrode pad regions (1) and (3). ) Only done. Further, the above-described die sort test in step S2 of FIG. 2 is performed only on the element surface electrodes 29 in the two-layer electrode pad regions (1) and (3). This is because, as described above, the internal electrode 28 in the dummy electrode pad region (2) does not have a function as a device, so that it is not necessary to perform a die sort test.

[2-2] Manufacturing Method of Through Electrode Next, a manufacturing process of the through electrode in the two-layer electrode pad region and the dummy electrode pad region in the camera module will be described in detail (Step S6 to Step S9 in FIG. 2). 8 to 14 are cross-sectional views showing a manufacturing process of the through electrode in the two-layer electrode pad region (1) and the dummy electrode pad region (2). Here, in each step, the through electrodes in the two-layer electrode pad region (1) and the dummy electrode pad region (2) are formed simultaneously. In each figure, the first surface of the silicon substrate 10 described above is located on the lower side, and the second surface is located on the upper side.

  First, as shown in FIG. 8, a through hole 80 is formed from the second surface to the first surface of the silicon substrate 10. The through hole 80 is formed as follows.

  First, a resist (not shown) is applied on the second surface of the silicon substrate 10. Next, the resist at a position corresponding to the pad opening (pad opening 32 in FIGS. 4 to 7) is opened by lithography, and a part of the second surface of the silicon substrate 10 is exposed. At this time, since the opening of the second surface of the silicon substrate 10 is aligned with an alignment mark (not shown) on the first surface of the silicon substrate 10, means such as a double-sided aligner and a double-sided stepper Should be used.

  Next, the silicon substrate 10 is etched by RIE using the patterned resist as a mask. At this time, a stopper in the RIE of the silicon substrate 10 is a layer directly in contact with the silicon substrate 10 in the first interlayer insulating film 13 or a gate insulating film formed on the silicon substrate 10. Next, the resist is removed by ashing and wet cleaning. In this way, the through hole 80 is formed in the silicon substrate 10 (step S6 in FIG. 2).

  Preferably, after the RIE of the silicon substrate 10 or the resist is removed, the RIE residue is removed by HF wet cleaning. Further, the shape of the through hole 80 of the silicon substrate 10 formed by RIE is desirably a tapered shape that becomes gradually narrower from the second surface to the first surface. If a notching or bowing shape occurs and a taper in the opposite direction is formed, it may cause a defective formation of an insulating film by CVD or a formation of a metal seed layer by sputtering.

  Next, as shown in FIG. 9, the insulating film 24 is formed in the through hole 80 and on the second surface of the silicon substrate 10 by the CVD method. The insulating film 24 is made of, for example, a silicon oxide film, a silicon oxynitride film, or a silicon nitride film (step S7 in FIG. 2).

  Next, as shown in FIG. 10, a resist 100 is applied on the insulating film 24. This resist is formed in the entire surface of the through hole 80 and on the insulating film 24 on the second surface in the silicon substrate 10.

  Next, as shown in FIG. 11, the resist 100 is patterned by lithography. As a result, the resist 100 is opened to the bottom of the through hole 80 (on the first surface side of the silicon substrate 10), and the insulating film 24 at the bottom of the through hole 80 is exposed.

  Next, as shown in FIG. 12, RIE of the insulating film 24 and the first interlayer insulating film 13 is performed using the resist 100 as a mask (step S8 in FIG. 2). At this time, the internal electrode 28 serves as a stopper during RIE of the insulating film 24 and the first interlayer insulating film 13. Through this step, a part of the internal electrode 28 is exposed.

  Next, as shown in FIG. 13, the resist 100 is removed by ashing and wet cleaning. At this time, since the surface of the internal electrode 28 may be oxidized by several nm to several tens of nm, it is desirable that the surface be slightly etched by alkaline wet etching.

  Next, as shown in FIG. 14, the through electrode 25 is formed on the insulating film 24 and the internal electrode 28. The through electrode 25 is formed as follows.

  First, it is desirable to remove the oxide layer on the internal electrode 28 by reverse sputtering. Next, a metal seed layer such as Ti or Cu is formed by sputtering. Next, a resist (not shown) is applied on the second surface of the silicon substrate 10. Next, patterning is performed by lithography so that the resist remains only in the portion where the through electrode 25 is not formed. Next, the metal seed layer is plated by electric field plating or the like, and the through electrode 25 is formed. Thereafter, the resist is removed by wet etching or the like. Subsequently, an unplated metal seed layer is etched by wet cleaning or the like. In this way, the through electrode 25 is formed on the insulating film 24 (step S9 in FIG. 2). Note that the through electrode 25 may not be formed in the dummy electrode pad region (2).

  By the way, the internal electrode 28 (for example, Al) reacts with moisture and corrodes when left in the air. In order to prevent this corrosion, it is desirable to manage the standing time after the internal electrode 28 is exposed within a certain time. For example, after the internal electrode 28 is exposed by the step of removing the insulating film 24 and the first interlayer insulating film 13 by RIE, the step of forming the metal seed layer by sputtering is preferably performed within 3 hours, preferably within 24 hours at the longest. It is desirable to be done.

[2-3] Effect According to the first embodiment, in the silicon wafer in the manufacturing process of the camera module, the dummy electrode having only the internal electrode 28 that is electrically floating on the through electrode 25 in the imaging element chip 1. A pad area (2) is provided. On the internal electrode 28 in the dummy electrode pad region (2), there is no shielding like the element surface electrode 29 in the two-layer electrode pad regions (1) and (3). Thereby, the internal electrode 28 in the dummy electrode pad region (2) can be easily observed through the glass substrate 23 and the like. That is, when the internal electrode 28 is exposed during the manufacturing process (step S8 in FIGS. 12 and 2), and abnormalities such as corrosion occur due to being left in the air, the through electrode 25 is formed. However, the abnormality can be easily found from the glass substrate 23 side (step S9 in FIGS. 14 and 2). Accordingly, when an abnormality is found in the internal electrode 28 in the dummy electrode pad region (2), an abnormality has also occurred in the internal electrode 28 in the two-layer electrode pad regions (1) and (3) in the vicinity thereof. Judgment can be made.

[3] Second Embodiment In the first embodiment, the dummy electrode pad region is formed in the imaging device chip in the silicon wafer. On the other hand, the second embodiment is an example in which a dummy electrode pad region is formed on a dicing line in a silicon wafer. Here, the description of the same points as in the first embodiment will be omitted, and different points will be described in detail.

[3-1] Structure of Through Electrode FIG. 15 is a plan view of a part of the silicon substrate of the wafer level CMOS sensor in this embodiment as viewed from the glass substrate side. 16 is a cross-sectional view taken along line XVI-XVI of FIG.

  As shown in FIG. 15, the imaging element chip 1 is formed by being partitioned by a dicing line 2. The imaging element chip 1 is provided with a two-layer electrode pad region (1) having a pixel portion 3 and an electrode pad 4. The dicing line 2 is provided with a dummy electrode pad region (4) having electrode pads 5.

  A plurality of two-layer electrode pad regions (1) are formed at the end in the image sensor chip 1 without gaps along the X direction. The dummy electrode pad region (4) is formed on the dicing line 2 in isolation. The dummy electrode pad region (4) may be formed anywhere on the dicing line 2.

  As shown in FIG. 16, in the cross section of the dummy electrode pad region (4), the second embodiment has the same structure as the dummy electrode pad region (2) in the first embodiment. That is, the element surface electrode 29 and the contact plug 30 do not exist on the internal electrode 28 and are not connected to the solder ball 27. For this reason, the through electrode 25 and the internal electrode 28 are in an electrically floating state, and the internal electrode 28 and the through electrode 25 in the dummy electrode pad region (4) do not have a function as a device.

[3-2] Effects According to the second embodiment, the same effects as those of the first embodiment can be obtained.

  Furthermore, in the second embodiment, the dummy electrode pad region 5 is formed on the dicing line 2 in the silicon wafer. Thereby, even if the inside of the image pickup device chip 1 is filled with the two-layer electrode pad region (1), it is possible to easily find the abnormality of the internal electrode 28 by the dummy electrode pad region (4) on the dicing line 2. It is.

[4] Third Embodiment In the second embodiment, one dummy electrode pad region is formed on a dicing line in a silicon wafer. In contrast, the third embodiment is an example in which a plurality of adjacent dummy electrode pad regions are formed on a dicing line. Here, the description of the same points as in the first and second embodiments will be omitted, and different points will be described in detail.

[4-1] Structure of Through Electrode FIG. 17 is a plan view of a part of the silicon substrate of the wafer level CMOS sensor in this embodiment as viewed from the glass substrate side. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG.

  As shown in FIG. 17, a plurality of dummy electrode pad regions (5) to (7) are formed adjacent to each other on the dicing line 2. The dummy electrode pad regions (5) to (7) may be formed anywhere as long as there are a plurality of dummy electrode pad regions (5) to (7) on the dicing line 2, or may be formed with a gap.

  As shown in FIG. 18, in the cross section of the dummy electrode pad regions (5) to (7), the third embodiment has the same structure as the dummy electrode pad region (4) in the second embodiment. The dummy electrode pad regions (5) to (7) are formed adjacent to each other.

[4-2] Effects According to the third embodiment, the same effects as in the second embodiment can be obtained.

  Furthermore, in the third embodiment, a plurality of dummy electrode pad regions (5) to (7) are formed adjacent to each other on the dicing line 2. This facilitates discovery when an abnormality occurs in the internal electrode 28, compared to the second embodiment in which one dummy electrode pad region (5) to (7) is formed.

  In addition, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention when it is practiced. Furthermore, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.

  DESCRIPTION OF SYMBOLS 1 ... Imaging device chip, 2 ... Dicing line, 3 ... Pixel part, 4, 5 ... Electrode pad, 10 ... Silicon substrate, 11 ... STI, 12 ... Imaging device, 13 ... 1st interlayer insulation film, 14 ... Wiring, 15 ... Passivation film, 16 ... Base layer, 17 ... Second interlayer insulating film, 18 ... Color filter, 19 ... Overcoat, 20 ... Micro lens, 21 ... Color filter / micro lens layer, 22 ... Cavity, 23 ... Glass substrate, 24 ... insulating film, 25 ... through electrode, 26 ... solder resist, 27 ... solder ball, 28 ... internal electrode, 29 ... element surface electrode, 30 ... contact plug, 31 ... styrenic resin layer, 32 ... pad opening, 33 , 34, 35, 36 ... adhesive, 40 ... IR cut glass, 41 ... IRCF, 50 ... imaging lens, 60 ... lens holder, 70 ... light shielding and electromagnetic shield De, 80 ... through hole, 100 ... resist.

Claims (5)

A semiconductor substrate;
A first through electrode formed in a first through hole opened from a first surface in the first region of the semiconductor substrate to a second surface facing the first surface;
A first electrode pad formed in contact with the first through electrode on the first surface of the semiconductor substrate;
A second electrode pad formed spaced apart from the first electrode pad and facing the first electrode pad;
An external terminal formed on the second surface of the semiconductor substrate and electrically connected to the first through electrode;
The first surface of the semiconductor substrate is formed on a second through-hole formed from the first surface to the second surface in a second region different from the first region of the semiconductor substrate, and is electrically floating A third electrode pad,
A semiconductor device comprising:   2. The semiconductor device according to claim 1, further comprising a second through electrode formed in the second through hole, in contact with the third electrode pad, and electrically floating. An image sensor formed on the first surface of the semiconductor substrate and connected to the external terminal via the first electrode pad and the first through electrode;
A color filter disposed corresponding to the image sensor and exposing the second electrode pad;
A microlens disposed on the color filter corresponding to the image sensor;
A supporting glass provided above the microlens, the second electrode pad, and the third electrode pad;
The semiconductor device according to claim 1, further comprising:   The semiconductor device according to claim 3, wherein the color filter and the microlens are continuously disposed above the third electrode pad.   The semiconductor device according to claim 1, wherein the second region exists in a semiconductor chip.

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