JP5925006B2 - 半導体集積回路装置の製造方法 - Google Patents
半導体集積回路装置の製造方法 Download PDFInfo
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- JP5925006B2 JP5925006B2 JP2012069669A JP2012069669A JP5925006B2 JP 5925006 B2 JP5925006 B2 JP 5925006B2 JP 2012069669 A JP2012069669 A JP 2012069669A JP 2012069669 A JP2012069669 A JP 2012069669A JP 5925006 B2 JP5925006 B2 JP 5925006B2
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- 239000004065 semiconductor Substances 0.000 title claims description 246
- 238000004519 manufacturing process Methods 0.000 title claims description 171
- 238000000034 method Methods 0.000 claims description 397
- 230000008569 process Effects 0.000 claims description 240
- 230000015572 biosynthetic process Effects 0.000 claims description 102
- 229910052751 metal Inorganic materials 0.000 claims description 80
- 239000002184 metal Substances 0.000 claims description 80
- 239000000758 substrate Substances 0.000 claims description 57
- 238000011049 filling Methods 0.000 claims description 41
- 230000004888 barrier function Effects 0.000 claims description 35
- 238000012360 testing method Methods 0.000 claims description 21
- 229910021332 silicide Inorganic materials 0.000 claims description 16
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 15
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 15
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 238000010894 electron beam technology Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 111
- 230000002093 peripheral effect Effects 0.000 description 68
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 37
- 229910052814 silicon oxide Inorganic materials 0.000 description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 30
- 229910052802 copper Inorganic materials 0.000 description 30
- 239000010949 copper Substances 0.000 description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 28
- 229920005591 polysilicon Polymers 0.000 description 28
- 150000001408 amides Chemical class 0.000 description 23
- 239000011229 interlayer Substances 0.000 description 23
- 238000007689 inspection Methods 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 239000000523 sample Substances 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 238000004544 sputter deposition Methods 0.000 description 16
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 15
- 229910000679 solder Inorganic materials 0.000 description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 15
- 229910052721 tungsten Inorganic materials 0.000 description 15
- 239000010937 tungsten Substances 0.000 description 15
- 238000000059 patterning Methods 0.000 description 14
- 230000008901 benefit Effects 0.000 description 13
- 230000004048 modification Effects 0.000 description 13
- 238000012986 modification Methods 0.000 description 13
- 238000001312 dry etching Methods 0.000 description 12
- 238000004380 ashing Methods 0.000 description 11
- 239000011521 glass Substances 0.000 description 11
- 238000012545 processing Methods 0.000 description 11
- 238000002161 passivation Methods 0.000 description 10
- 238000001459 lithography Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 230000006872 improvement Effects 0.000 description 8
- 229910052759 nickel Inorganic materials 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000005520 cutting process Methods 0.000 description 6
- 238000009713 electroplating Methods 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- UPSOBXZLFLJAKK-UHFFFAOYSA-N ozone;tetraethyl silicate Chemical compound [O-][O+]=O.CCO[Si](OCC)(OCC)OCC UPSOBXZLFLJAKK-UHFFFAOYSA-N 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 4
- 238000000227 grinding Methods 0.000 description 4
- 238000009413 insulation Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 238000009966 trimming Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910001371 Er alloy Inorganic materials 0.000 description 2
- 229910001252 Pd alloy Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910001260 Pt alloy Inorganic materials 0.000 description 2
- 241000724291 Tobacco streak virus Species 0.000 description 2
- 229910000756 V alloy Inorganic materials 0.000 description 2
- 229910000821 Yb alloy Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- VJDVOZLYDLHLSM-UHFFFAOYSA-N diethylazanide;titanium(4+) Chemical compound [Ti+4].CC[N-]CC.CC[N-]CC.CC[N-]CC.CC[N-]CC VJDVOZLYDLHLSM-UHFFFAOYSA-N 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 229910052736 halogen Inorganic materials 0.000 description 2
- 150000002367 halogens Chemical class 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000001603 reducing effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 241000027294 Fusi Species 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical compound [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
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- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
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- H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
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- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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Description
先ず、本願において開示される代表的な実施の形態について概要を説明する。
(a)デバイス主面および裏面を有する半導体ウエハを準備する工程;
(b)前記半導体ウエハの前記デバイス主面から、前記半導体ウエハの表面の半導体領域に、その内部に至る複数のホールを形成する工程;
(c)前記複数のホールの内面に絶縁膜を成膜する工程;
(d)前記工程(c)の後、前記複数のホールの底部を除く前記内面が前記絶縁膜で被覆された状態で、前記複数のホール内を導電性部材で埋め込むことにより、複数の貫通ビア電極を形成する工程。
(e)ウエハ工程中において、前記複数の貫通ビア電極の少なくとも一つをゲート電極に電気的に接続する工程。
(f)前記工程(d)の後であってウエハ工程中に、電子ビームを前記ウエハの前記デバイス主面に照射することによって、前記複数の貫通ビア電極の導通状態をテストする工程。
(g)前記工程(d)の後、前記半導体ウエハの前記裏面側から、前記半導体ウエハに対して、薄膜化処理を実施することにより、前記複数の貫通ビア電極を前記半導体ウエハの前記裏面側に於いて露出させる工程。
(h)前記工程(g)の後、前記複数の貫通ビア電極を他の半導体基板に設けられたバンプ電極と接続する工程。
1.本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクションに分けて記載する場合もあるが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しを省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
実施の形態について更に詳述する。各図中において、同一または同様の部分は同一または類似の記号または参照番号で示し、説明は原則として繰り返さない。
以下では、シリコン系CMIS型半導体集積回路(すなわち、MOS型半導体集積回路)を例にとり、具体的に説明するが、バイポーラ型半導体集積回路やその他のデバイスでもよいことは言うまでもない。
(1)ウエハ1の表面1a側から、半導体表面領域に、その内部に至る複数のホールを形成する。
(2)その後、前記複数のホールの内面に絶縁膜を形成する。
(3)前記(2)の後、前記複数のホールの底部を除く前記内面が、前記絶縁膜で被覆された状態で(すなわち、底部の少なくとも一部は被覆されていない)、前記複数のホール内を導電部材で埋め込むことにより、複数の貫通ビア電極を形成する。
ここに示すプロセスは、一例であり、各要素プロセスは種々変形できることは言うまでもない。また、各要素プロセスは、特に必須である旨、明記した場合、または、明らかに必須である場合以外は、必須のものではない。更に、このことは、セクション3に示す各要素プロセスについても同じである。なお、言うまでもないことであるが、セクション3から6に示す各付加的要素は、任意付加的なものであって、必須のものではない。
ここでは、半導体基板の接合方式および積層形式として、B2F(Back−to−Face)接合によるD2D(Die−to−Die)方式を例に取り具体的に説明するが、F2F(Face−to−Face)方式でも良いことは言うまでもない。また、積層形式としては、W2W(Wafer−to−wafer)方式でも、D2W(Die−to−Wafer)方式でも良いことは言うまでもない。なお、このW2W方式には、良品確認チップ(Known Good Die)をウエハ又はウエハ状基板上に再配列した再配列ウエハ(Reconfigured Wafer)等も含まれる。また、W2W方式およびD2W方式にも、同様にB2F接合およびF2F接合の両方が適用できる。
このセクションでは、セクション3で説明した製造の各時点でのウエハプローブ検査に於いて、起こる可能性のある問題点を解決するために有用な付加的な技術である。従って、この方法はもちろん必須ではない。
このセクションでは、たとえば、セクション2の図11の工程(貫通ビアの埋め込み完了時点)等で実施する電子線等を用いた貫通ビア電極の導通テストについて説明する。
ボルテージコントラストテストには、大きく分けて2種類あり、一方が、ウエハ1の表面1a側を正に帯電させるPVC(Positive Voltage Contrast)テストであり、他方がウエハ1の表面1a側を負に帯電させるNVC(Negative Voltage Contrast)テストである。まず、PVCテストについて説明する。
NVCテストにおいては、図30に示すように、正常な貫通ビア電極9nは、半導体基板部1sからの電子供給があるので、帯電が進まず、暗く見える。一方、非導通貫通ビア電極9dの方は、半導体基板部1sからの電子供給がないので帯電が進み、明るく見える。
これらのテストの好適なタイミングとしては、たとえば、セクション2の図11の工程(貫通ビアの埋め込み完了時点、以下同じ)、図38、図42、図51等を例示することができる。このように、電子ビームをウエハのデバイス面に照射することによって、多数(複数の)貫通ビア電極の導通状態をその完成直後に(後の工程まで待つことなく)比較的簡単に検査することができる。
このセクションでは、これまでに説明した貫通ビア電極9と半導体基板部1s間の電気的接続状態を更に向上させる付加的な手法について説明する。なお、以下の(1)から(3)の手法は、任意に組み合わせて適用することができる。
図31に示すように、たとえば、図9の貫通ビア底部16bの絶縁膜除去完了段階において、ウエハ1のデバイス面1aから、たとえば、イオン注入により、半導体基板部1s(たとえば、P型シリコン基板)に、これよりも高濃度のP型不純物(たとえば、ボロン)を導入する。注入条件としては、たとえば、打ち込み角:ほぼ垂直、ドーズ量:例えば1x1015/cm2程度、打ち込みエネルギ:例えば50KeV程度を公的なものとして例示することができる。このように、貫通ビア底部16bの半導体基板部1sに高濃度領域39を設けることにより、貫通ビア電極9と半導体基板部1sの間のコンタクトをオーミックコンタクトとすることができる。
図31の工程の後、図32に示すように、高濃度領域39の表面に、メタルシリサイド膜46(材料としては、たとえばニッケル系シリサイド、タングステンシリサイド、コバルトシリサイド、チタンシリサイド、白金系シリサイド等)を形成すると、よりコンタクト抵抗を下げることができる。すなわち、このようにすることにより、複数の貫通ビア電極の各々と、その近傍の半導体領域との間には、メタルシリサイド層が形成されていることになり、相互のコンタクトを良好にするメリットがある。
図33に示すように、たとえば、図9の貫通ビア底部16bの絶縁膜除去完了後であって、図10の貫通ビア内バリアメタル膜9bすなわち、窒化チタン膜の成膜の前において、たとえば、スパッタリング成膜等により、ウエハ1のデバイス面1a側のほぼ全面に、比較的薄いチタン膜9c(例えば、厚さ10nm程度)を成膜する。すなわち、バリアメタル構造を、外側のチタン膜と内側の窒化チタン膜とすることにより、チタン膜の良好な酸化膜等への密着性および、シリコンに対する還元作用等に起因して、良好なコンタクト特性を確保することができる。
このセクションでは、セクション2等で説明したプロセスに対する貫通ビア形成のタイミングに関する変形例として、ビアラスト方式の例を説明する。貫通ビア形成のタイミングが、プリメタル領域完成時点から最上層埋め込み配線22の完成時点に移るのみであるので、プロセスの流れは、貫通ビア部分の除き、図4から図27と基本的に同じである。従って、以下では原則として、貫通ビア形成のタイミングの移動に伴って異なってくる部分のみを説明する。
このセクションでは、セクション2等で説明したプロセスに対する貫通ビア形成のタイミングに関する変形例として、ビアファースト−ポリシリコン方式の例を説明する。貫通ビア形成のタイミングが、プリメタル領域完成時点からSTI領域および一部不純物ドープ領域(例えば、図2のNウエル領域WN、Pウエル領域WP等)の完成時点に移るのみであるので、プロセスの流れは、貫通ビア部分の除き、図4から図27と基本的に同じである。従って、以下では原則として、貫通ビア形成のタイミングの移動に伴って異なってくる部分のみを説明する。
このセクションでは、セクション2等で説明したプロセスに対する貫通ビア形成のタイミングに関する変形例として、ビアファースト−コンタクト方式の例を説明する。貫通ビア形成開始のタイミングが、プリメタル領域完成時点からゲート電極の完成時点(例えば、ゲート電極のパターニング、ソースドレインの導入、サイドウォール形成等の後であって、プリメタル絶縁膜6の成膜前)に移るのみであるので、プロセスの流れは、貫通ビア部分の除き、図4から図27と基本的に同じである。従って、以下では原則として、貫通ビア形成のタイミングの移動に伴って異なってくる部分のみを説明する。
(1)TSVの問題点および、各実施例の特徴:
TSVすなわち、シリコン基板等の半導体基板に明けられた貫通孔に形成された貫通ビア電極は、たとえば、本願で主に説明した貫通ビア先行表面ビア型プロセスでは、ウエハの薄膜化の前には、一般に、下端が閉じられているため、貫通ビア電極の導通テストが困難である。また、ウエハの半導体基板部と各貫通ビア電極が一般に絶縁されている場合が多いため、貫通ビア電極の埋め込み後のプロセスにより、不所望なチャージアップが発生した場合は、ゲート破壊等の不良が発生する恐れがある。
(2)貫通ビア電極形成のタイミングに関する考察等:
セクション1から6で主に説明したようなビアミドル方式は、下層配線(たとえば、第1層埋め込み配線)の微細加工が適用でき、かつ、銅等を貫通ビア電極の主要材料とすることができ、低抵抗の貫通ビア電極とすることができるメリットがある。
以上本発明者によってなされた発明を実施形態に基づいて具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。
1a ウエハまたはチップの表面(デバイス面または第1の主面)
1b ウエハまたはチップの裏面(第2の主面)
1s 半導体基板部(P型単結晶シリコン基板)
2,2x、2y 半導体チップまたはチップ領域
3 STI領域
4 ゲート絶縁膜
5 ゲート電極(ゲートポリシリコン膜)
6 プリメタル絶縁膜
6a 主プリメタル絶縁膜
6b キャップ層プリメタル絶縁膜
7 導電性プラグ
7a 主メタルプラグ
7b メタルプラグバリアメタル膜
8 第1層埋め込み配線
8a 第1層銅配線膜
8b 第1層配線バリアメタル膜
9,9x、9y 貫通ビア電極
9a 貫通ビア主メタル電極
9b 貫通ビア内バリアメタル膜
9c 貫通ビア内チタン膜
9d 非導通貫通ビア電極
9n 正常な貫通ビア電極
9p ポリシリコン貫通ビア電極
10 多層埋め込み配線
11 貫通ビア内ライナ絶縁膜
12 第1層配線層間絶縁膜
14 ゲート電極−貫通ビア電極間配線
15 貫通ビア形成用レジスト膜
16 貫通ビア
16b 貫通ビア底部
16i 貫通ビア内面
17 貫通ビア底絶縁膜除去用レジスト膜
18 第1層配線溝形成用レジスト膜
19 中間層埋め込み配線
20 配線層間絶縁膜
20p パッド下層間絶縁膜
21 中間層&上層層間絶縁膜
22 パッド層等を除く最上層配線(最上層埋め込み配線)
22a 最上層埋め込み配線主メタル膜
22b 最上層埋め込み配線バリアメタル膜
23 上層のタングステンプラグ
24p 電極パッド(アルミニウム系パッド)
24pg 出力用電極パッド
24pi データ入力用電極パッド
24ps スイッチ制御用電極パッド
24w パッド層配線
25 ファイナルパッシベーション膜
26 銅バンプ電極(メタルバンプ電極)
27 半田バリアメタル膜
28 半田層
29 接着剤層
30 バンプ電極
31 サポート基板(ガラスサポートウエハ)
32 裏面絶縁膜
33 裏面パッド
34 ダイシングテープ
35 多層配線基板
36 上部ランド
37 下部ランド
38 外部半田バンプ電極(半田ボール)
39 高濃度領域
40 コンタクトホール
41 非導通部
42 下層中層埋め込み配線
43 ゲート絶縁膜エッチング用レジスト膜
44 ゲート電極加工用レジスト膜
45 コンタクトホール形成用レジスト膜
46 メタルシリサイド膜
47 第1層配線溝
51 プローブ針
101 ビア形成工程
102 絶縁膜成膜工程
103 ビア電極形成工程
DN N型ソースドレイン領域
DP P型ソースドレイン領域
IC LSI内部回路
IF 入出力回路
Qn Nチャネル型MISFET
Qp Pチャネル型MISFET
R1 MISFETおよび貫通ビア周辺部切り出し領域
SW スイッチ又はスイッチ回路
WN Nウエル領域
WP Pウエル領域
Claims (19)
- 以下の工程を含む半導体集積回路装置の製造方法:
(a)デバイス主面および裏面を有する半導体ウエハを準備する工程;
(b)前記半導体ウエハの前記デバイス主面から、前記半導体ウエハの半導体表面領域に、その内部に至る複数のホールを形成する工程;
(c)前記複数のホールの内面に絶縁膜を成膜する工程;
(d)前記工程(c)の後、前記複数のホールの底部を除く前記内面が前記絶縁膜で被覆された状態で、前記複数のホール内を導電性部材で埋め込むことにより、複数の貫通ビア電極を形成する工程;
(e)前記工程(d)の後であってウエハ工程中に、電子ビームを前記ウエハの前記デバイス主面に照射することによって、前記複数の貫通ビア電極の導通状態をテストする工程。 - 請求項1に記載の半導体集積回路装置の製造方法において、更に以下の工程を有する:
(f)ウエハ工程中において、前記複数の貫通ビア電極の少なくとも一つをゲート電極に電気的に接続する工程。 - 請求項2に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極はビアミドル方式によって形成される。
- 請求項3に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極の埋め込みは、第1層配線形成工程中に於いて、第1層配線の埋め込みと異なるタイミングで実行される。
- 請求項3に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極の埋め込みは第1層配線の埋め込みと同時に実行される。
- 請求項2に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極はビアラスト方式によって形成される。
- 請求項6に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極の形成は、パッド層を除く最上層配線形成工程中に実行される。
- 請求項7に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極の少なくとも一つを、前記パッド層に属する配線によって、パッドに電気的に接続する。
- 請求項1に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極のうち少なくとも1つは、前記ホールの底部において、前記半導体基板と接触している。
- 請求項2に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極はビアファースト方式によって形成される。
- 請求項10に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極の埋め込みは、ゲート電極形成工程中に於いて、ゲート電極膜の形成と異なるタイミングで実行される。
- 請求項10に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極の埋め込みはゲート電極膜の形成と同時に実行される。
- 請求項10に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極の埋め込みは、コンタクト形成工程中に於いて、コンタクトプラグの形成と異なるタイミングで実行される。
- 請求項10に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極の埋め込みはコンタクトプラグの形成と同時に実行される。
- 請求項2に記載の半導体集積回路装置の製造方法において、少なくとも、前記工程(d)の後には、前記複数の貫通ビア電極の各々の下端近傍の半導体領域には、当該部分の周辺の半導体領域と同一導電型を有し、不純物濃度が高い高濃度領域が形成されている。
- 請求項2に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極のバリアメタル構造は、主に外層のチタン膜および内層の窒化チタン膜から構成されている。
- 請求項2に記載の半導体集積回路装置の製造方法において、前記複数の貫通ビア電極の各々の下端と、その近傍の半導体領域との間には、メタルシリサイド層が形成されている。
- 請求項2に記載の半導体集積回路装置の製造方法において、更に以下の工程を有する:
(g)前記工程(e)の後、前記半導体ウエハの前記裏面側から、前記半導体ウエハに対して、薄膜化処理を実施することにより、前記複数の貫通ビア電極を前記半導体ウエハの前記裏面側に於いて露出させる工程。 - 請求項18に記載の半導体集積回路装置の製造方法において、更に以下の工程を有する:
(h)前記工程(g)の後、前記複数の貫通ビア電極を他の半導体基板に設けられたバンプ電極と接続する工程。
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US13/795,731 US9240330B2 (en) | 2012-03-26 | 2013-03-12 | Method of manufacturing a semiconductor integrated circuit device |
TW102108854A TWI594388B (zh) | 2012-03-26 | 2013-03-13 | 半導體積體電路裝置之製造方法 |
CN201310099950.XA CN103441095B (zh) | 2012-03-26 | 2013-03-26 | 半导体集成电路器件的制造方法 |
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