CN103081077A - 半导体装置的制造方法及半导体装置 - Google Patents

半导体装置的制造方法及半导体装置 Download PDF

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CN103081077A
CN103081077A CN2011800389423A CN201180038942A CN103081077A CN 103081077 A CN103081077 A CN 103081077A CN 2011800389423 A CN2011800389423 A CN 2011800389423A CN 201180038942 A CN201180038942 A CN 201180038942A CN 103081077 A CN103081077 A CN 103081077A
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大见忠弘
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Abstract

本发明的课题在于提供一种即使将基板减薄也能够防止其翘曲的TSV构造的制造方法。本发明的半导体装置的制造方法在半导体基板的表面集成半导体元件，形成至少一部分电路，自半导体基板的表面开孔，在孔的内表面形成绝缘膜和阻挡膜，在阻挡膜的表面以填埋孔的方式形成导电性金属，加工半导体基板的背面使其厚度减小，使导电性金属突出，在半导体基板的背面设置SiCN膜。

Description

半导体装置的制造方法及半导体装置
技术领域
本发明涉及一种具有TSV构造的半导体装置的制造方法及半导体装置。
背景技术
近年来，根据半导体LSI（Large-scale integration，大规模集成电路）的超高密度化，为了将装置构成为三维结构，采用了一种TSV（Through Silicon Via、硅贯通电极）构造，即以贯通半导体装置（半导体芯片或半导体晶圆）内的方式设置贯通电极并将该贯通电极的端部连接于另一个半导体装置的电极从而形成三维构造的技术。
在TSV构造中，在层叠多枚半导体装置的情况下，由于通过贯通电极对半导体装置之间进行连接，因此，不再需要用于连接的焊盘、中介层等，能够将半导体装置更加小型化。
在此，在具有TSV构造的半导体装置中，为了谋求装置的进一步薄型化，存在一种如下一种情况：在形成电路的硅基板（晶圆）上开设多个必要的孔，并在孔中形成Cu、W的电极金属柱而作为TSV，然后通过从晶圆背面进行蚀刻等加工将晶圆减薄，并且使电极金属柱从背面突出（专利文献1）。
专利文献1：日本特开2010－114155号公报
然而，在上述加工中虽然能够将基板减薄，但是存在有在将基板减薄时容易发生基板翘曲的问题。
发明内容
发明要解决的问题
本发明即是鉴于上述问题而做成的，其技术课题在于提供一种即使将基板减薄也能够防止其翘曲的、具有TSV构造的半导体装置的制造方法。
用于解决问题的方案
为了解决上述课题，本发明的第1技术方案为一种半导体装置的制造方法，其特征在于，该半导体的制造方法包括在半导体基板的表面集成半导体元件，形成全部电路或一部分电路的工序（a）；自上述半导体基板的表面开孔的工序（b）；在上述孔的内表面形成绝缘膜和阻挡膜（具有对之后形成的导电性金属起阻挡作用的膜）的工序（c）；在上述阻挡膜的内表面以填埋上述孔的方式形成导电性金属的工序（d）；然后加工上述半导体基板的背面使上述半导体基板的厚度减小从而使上述导电性金属、上述阻挡膜、及上述绝缘膜自上述背面突出的工序（e）；然后在上述半导体基板的背面设置SiCN膜的工序（f）。
本发明的第2技术方案为一种半导体装置，其特征在于，该半导体装置包括在表面形成有半导体元件的半导体基板、贯通上述半导体基板且一部分自背面突出地设置的贯通电极、覆盖上述背面地设置的SiCN膜。
发明的效果
采用本发明，能够提供一种即使将基板减薄也能够防止其翘曲的、具有TSV构造的半导体装置的制造方法。
附图说明
图1是表示半导体装置100的剖视图。
图2是表示半导体装置100的制造工序的剖视图。
图3是表示半导体装置100的制造工序的剖视图。
图4是表示半导体装置100的制造工序的剖视图。
图5是表示半导体装置100的制造工序的剖视图。
图6是表示半导体装置100的制造工序的剖视图。
图7是表示半导体装置100的制造工序的剖视图。
图8是表示半导体装置100的制造工序的剖视图。
图9是表示半导体装置100的制造工序的剖视图。
图10是表示SiCN膜20的成分与物理特性（内部应力）的关系的图。
具体实施方式
以下参照附图详细地说明本发明中较佳的实施方式。
首先，参照图1说明本实施方式的半导体装置100的结构。
如图1所示，半导体装置100包括硅基板等基板1，通过在基板1的表面集成未图示的半导体元件，来形成作为DRAM（Dynamic Random Access Memory，动态随机存取存储器）、闪存器等LSI构造的电路2。
另外，在半导体装置100中，贯通基板1地形成有贯通电极31（TSV），贯通电极31的一部分自基板1的背面（形成有电路2的面的相反侧的面）突出。
贯通电极31包括由Cu等导电性金属形成的柱状的插头13、覆盖插头13地形成的TaN等阻挡膜12。
而且，在贯通电极31和基板1之间，覆盖贯通电极31、且与基板1接触地设有Si3N4等绝缘膜11。
另一方面，在基板1的背面，覆盖该背面地形成有SiCN膜20。
SiCN膜20为设置于基板的背面的、使基板1不产生翘曲的钝化膜。通常作为钝化膜使用有氧化硅膜、氮化硅膜，但这些钝化膜存在会使较薄的基板产生翘曲的问题。详细见后述，而SiCN膜20则能够利用膜中的C量使其内部应力变化，因此，能够通过控制成膜时的C量使晶圆的翘曲实质上为0。
接着，参照图2～图10说明半导体装置100的制造方法。
首先，准备如图2所示的基板1。
如上所述，基板1使用硅基板等，使未图示的半导体元件集成，在基板1表面形成全部或一部分的电路2。
在此，准备厚度775μm的硅基板作为基板1，在其表面集成半导体元件，形成DRAM、闪存器等LSI构造的电路2。
接着，如图3所示，在基板1的用于形成TSV构造（贯通电极31）的部分自表面形成预定数量的孔10。
在此，孔10的径为10μm×10μm左右，深度为40μm～50μm左右。
开孔例如利用蚀刻进行。具体地说，蚀刻开孔使用2.45GHz微波激励RLSA（radial line slot antenna，径向线缝隙天线）型等离子电蚀刻器、915MHz微波激励MSEP（Metal SurfacewaveExcitation Plasma）等离子电蚀刻器进行。
由于这些电蚀刻器的腔室的内壁表面利用非水溶液的阳极氧化产生的Al2O3膜覆盖，因此完全不会产生水分。如果将抗蚀剂中的有机溶剂、水分全部预先去除，那么抗蚀剂和Si的蚀刻选择比成为50～100。因而，抗蚀剂的膜厚为2μm左右的薄度即可，由此能够相应提高其分辨率。
接着，如图4所示，在孔10的内表面形成绝缘膜11。绝缘膜11的形成方法列举有将Si直接氮化，并在其上CVD形成氮化硅膜的方法。
在该情况下，直接氮化采用915MHz微波激励的一层簇射板的MSEP等离子处理装置，自簇射板流出Ar气和NH3气的混合气体地进行。接着，在该氮化硅上利用CVD（Chemical VaporDeposition，化学气相沉积）形成Si3N4膜。
该CVD采用915MHz微波激励的双层簇射板的MSEP等离子处理装置，自上层簇射板流出Ar气和NH3气的混合气体，自下层簇射板流出Ar气和SiH4气的混合气体地进行。
接着，如图5所示，在绝缘膜11的内表面形成阻挡膜12。在此，与形成绝缘膜11时采用的方式相同，采用915MHz微波激励的双层簇射板的MSEP等离子处理装置，自上层簇射板流出Ar气和NH3气的混合气体，自下层簇射板流出TaCl3等气体，在Si3N4膜上通过CVD形成TaN膜作为阻挡膜12。该阻挡膜12是用于防止在后面成膜的Cu向半导体基板扩散的导电性阻挡膜。
接着，如图6所示，在孔10内以填埋孔10的方式形成插头13。在此使电流在TaN膜（阻挡膜12）上流过，将TaN膜作为晶种膜在TaN膜的内表面进行Cu的电镀，形成Cu的金属柱（TSV电极）作为插头13。
这样，在每个孔10内形成有TSV电极（贯通电极31）。
接着，如图7所示，从基板1的背面侧进行蚀刻，将基板1的厚度减薄至预定的厚度，进一步使被TaN膜12和绝缘膜11覆盖的TSV电极（插头13）底面侧的一部分自基板1的背面突出（露出）。
蚀刻是将基板1的正面侧粘贴在多孔性玻璃基板33（东京应化制（東京応化工業））上，利用使用HF/HNO3/CH3COOH/H2O溶液的超高速湿法蚀刻将775μm的硅基板1的背面侧以750μm/min的速度蚀刻约1分钟。其结果，基板1的厚度成为20μm～30μm左右。此时，由于Si3N4膜（绝缘膜11）不会被蚀刻，因此，能够仅利用湿法蚀刻而将基板1减薄。
如图7中明确地那样，在薄度成为20μm～30μm的基板1的背面侧突出有被TaN膜（阻挡膜12）和Si3N4膜（绝缘膜11）覆盖的Cu的插头13的底面侧。
接着，如图8所示，在基板1的背面利用CVD成膜SiCN膜20。
具体的说，SiCN膜20采用915MHz微波激励的双层簇射板的MSEP等离子处理装置，自上层簇射板流出Ar气和NH3气的混合气体，自下层簇射板流出Ar气、SiH4气、及SiH（CH3）3气的混合气体，以100℃左右的温度成膜而成。
其结果，能够完全地控制晶圆（基板1）的翘曲。
即，SiCN通过使C量为10原子%左右，而使其内部应力从正变成负，因此，能够通过抑制C量找出将晶圆的翘曲做成零的条件。
具体的说，如图10的空心箭头所示，能够例如通过调节SiH（CH3）3气体的浓度（即，通过调节膜中的C含量）来做到SiCN膜20的内部应力实质上成为0。
SiCN的成分优选为在氮化硅Si3N4中含有（添加）略少于10%的C而成，但也可以是添加了2原子%～40原子%的C而成的成分。
另外，SiCN不仅作为钝化膜特性卓越，还具有热传导性优良的特征。相对于SiO2的导热系数1.4W/m/开尔文，SiCN的热传导系数为70W/m/开尔文从而压倒性地大于SiO2的导热系数。
因此，通过在基板1的背面形成SiCN膜20，如上所述，能够兼顾完全的保护膜功能和抑制晶圆的翘曲。
另外，在形成SiCN时，如图8所示，在被TaN膜（阻挡膜12）和Si3N4膜（绝缘膜11）覆盖的Cu的插头13的突出部表面也形成有SiCN膜20。
然后，自玻璃基板33剥离晶圆（基板1）。另外，由于玻璃基板33在该状态下直接利用湿法蚀刻用的HF/HNO3/CH3COOH/H2O溶液被逐渐蚀刻，因此，利用涂覆添加了CeO2的Y2O3并以700℃左右烧结而成的未图示的保护膜将其露出面覆盖，从而停止蚀刻。
另外，在剥离玻璃基板33之前，如图9所示，在基板1的背面侧，在SiCN膜20（形成为硅基板背面的部分）的表面涂覆抗蚀剂，从而将覆盖了贯通电极31表面（阻挡膜12的自基板1的背面突出的表面）的SiCN膜20和Si3N4膜（绝缘膜11）蚀刻去除。
利用以上工序完成图1所示的半导体装置100。
这样，采用本实施方式，半导体装置100通过在基板1上开孔10，在孔10内形成绝缘膜11、阻挡膜12、插头13，蚀刻基板1的背面减薄基板1并使绝缘膜11、阻挡膜12、插头13突出，然后在基板1的背面形成SiCN膜20制造而成。
因此，在本发明的具有TSV构造的半导体装置的制造方法中，即使存在利用蚀刻将基板1减薄的情况，也能够防止基板1的翘曲。
产业上的可利用性
在上述实施方式中，针对将本发明应用于使用表面形成有DRAM、闪存器的硅基板的半导体装置100的情况进行了说明，但本发明并不限定于此，其能够应用于所有的TSV构造。
附图标记说明
1、基板；2、电路（LSI构造）；10、孔；11、绝缘膜；12、阻挡膜（TaN膜）；13、插头（导电性金属）；20、SiCN膜；31、贯通电极；33、玻璃基板；100、半导体装置。

Claims (17)

1.一种半导体装置的制造方法，其特征在于，
该半导体装置的制造方法包括：
工序（a），在半导体基板的表面集成半导体元件，形成至少一部分的电路；
工序（b），自上述半导体基板的表面开孔；
工序（c），在上述孔的内表面形成绝缘膜和阻挡膜；
工序（d），在上述阻挡膜的内表面以填埋上述孔的方式形成导电性金属；
工序（e），在工序（d）后，加工上述半导体基板的背面，减小上述半导体基板的厚度，使上述导电性金属、上述阻挡膜、及上述绝缘膜自上述背面突出；
工序（f），在工序（e）后，在上述半导体基板的背面设置SiCN膜。
2.根据权利要求1所述的半导体装置的制造方法，其特征在于，
上述工序（f）是控制上述SiCN膜的成分、使得上述半导体基板的翘曲实质上为零的工序。
3.根据权利要求1或2中任一项所述的半导体装置的制造方法，其特征在于，
上述工序（f）是形成SiCN膜的工序，该SiCN膜的成分为向Si3N4中添加了2原子%～40原子%的C而成。
4.根据权利要求1～3中任一项所述的半导体装置的制造方法，其特征在于，
上述工序（e）是通过蚀刻上述半导体基板的背面使上述半导体基板的厚度减小的工序。
5.根据权利要求1～4中任一项所述的半导体装置的制造方法，其特征在于，
上述工序（e）是将上述半导体基板的正面侧粘贴在多孔性玻璃基板上，通过湿法蚀刻上述半导体基板的背面使上述半导体基板的厚度减小的工序。
6.根据权利要求1～5中任一项所述的半导体装置的制造方法，其特征在于，
上述工序（f）包括利用CVD在上述半导体基板的背面成膜SiCN膜后，将形成于自上述背面突出的上述阻挡膜的表面上的上述绝缘膜和上述SiCN膜去除的工序。
7.根据权利要求1～6中任一项所述的半导体装置的制造方法，其特征在于，
上述半导体基板为Si基板；
上述工序（c）包括通过氮化上述孔的内表面形成上述绝缘膜的至少一部分的工序。
8.根据权利要求1～7中任一项所述的半导体装置的制造方法，其特征在于，
上述工序（c）包括形成导电性阻挡膜作为上述阻挡膜的工序；
上述工序（d）包括将上述导电性阻挡膜用作通电部件地利用电镀形成上述导电性金属的工序。
9.根据权利要求1～7中任一项所述的半导体装置的制造方法，其特征在于，
上述工序（c）包括在形成上述绝缘膜后，在上述绝缘膜上形成TaN膜作为上述阻挡膜的工序。
10.根据权利要求9所述的半导体装置的制造方法，其特征在于，
上述工序（d）是在上述TaN膜上将上述TaN膜作为晶种层，通过电镀形成Cu作为上述导电性金属的工序。
11.一种半导体装置，其特征在于，
该半导体装置包括：
在表面形成有电路的半导体基板；
贯通上述半导体基板且一部分自背面突出地设置的贯通电极；
覆盖上述背面地设置的SiCN膜。
12.根据权利要求11所述的半导体装置，其特征在于，
上述SiCN膜具有使上述半导体基板的翘曲实质上为零的成分。
13.根据权利要求11或12中任一项所述的半导体装置，其特征在于，
上述SiCN膜具有向Si3N4中添加了2原子%～40原子%的C而成的成分。
14.根据权利要求11～13中任一项所述的半导体装置，其特征在于，
上述贯通电极被对该电极的材料构成阻挡的阻挡膜覆盖，且上述阻挡膜被与上述半导体基板接触地设置的绝缘膜覆盖。
15.根据权利要求14所述的半导体装置，其特征在于，
上述半导体基板为Si基板；
上述绝缘膜包括Si3N4膜。
16.根据权利要求14所述的半导体装置，其特征在于，
上述阻挡膜的材料为TaN。
17.根据权利要求11～16中任一项所述的半导体装置，其特征在于，
上述贯通电极的材料为Cu。
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Application publication date: 20130501