TW201216411A - Method of manufacturing a semiconductor device and semiconductor device - Google Patents

Method of manufacturing a semiconductor device and semiconductor device Download PDF

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TW201216411A
TW201216411A TW100128435A TW100128435A TW201216411A TW 201216411 A TW201216411 A TW 201216411A TW 100128435 A TW100128435 A TW 100128435A TW 100128435 A TW100128435 A TW 100128435A TW 201216411 A TW201216411 A TW 201216411A
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film
substrate
semiconductor
semiconductor device
semiconductor substrate
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Tadahiro Ohmi
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Univ Tohoku
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
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    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

201216411 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種具有TSV構造的半導體裝置的製造方 及半導體裝置。 【先前技術】 近年來，為了因應半導體LSI的超高密度化，並以三維方式 ^裝置’遂開始採用TSV (Through Silicon Via，石夕貫通電極） 才ί造，、Ϊ即以貫通半導體裝置（半導體晶片或半導體晶圓）内部 帝方式**又置貫通電極，使該貫通電極的端部與其他半導體裝置的 電極連接以軸三轉造的技術。 读、i、TSV構造中’在堆疊複數片半導體裝置的情況下，由於係 =通電極連接各半導體裝置，故不需要連接用的接合墊或内 插層專構件’可使半導體裝置更進—步小型化。 牛在此，在具有TSV構造的半導體裝置中，為了使裝置更進一 型化’會在形成了電路的矽基板（晶圓）上形成複數個必要 ^孔、’ f其中形成Cu或W的電極金屬柱作為TSV，之後從晶圓 北颠刻等的加工，藉此使晶圓變薄，同時讓電極金屬柱從 月面大·出（專利文獻1)。 習知技術文獻 專利文獻 專利文獻1:日本特開2010 —114155號公報 【發明内容】 [發明所欲解決的問題] 發生=的S3加工雖可使基板變薄，但此時會有基板容易 的半題，本發狀目的在紐供1具有贾構造 問法，其即使絲板變薄也能夠防趟曲 s 201216411
[解決問題之技術手段；I 製造解ii述導=!1態樣係-種半導體裝置的 電路的全部或-部份的步驟^;在形成 ίί :e);在該半導二 右本ii明?第2態樣係一種半導體裝置，包含：在表面上形成 的半導體基板；貫通該半導體基板且-部分從該半 的si^^f面突出的貫通電極；以及覆蓋該半導體基板的背面 [對照先前技術之功效] 【實施方式】 以下，參照圖式詳細説明本發明的較佳實施態樣。 首先，參照圖1説明本實施態樣之半導體裝置1〇〇的構造。 如圖1所示的，半導體裝置100具有矽基板等的基板丨，在基 板1的表面上設有由圖中未顯示之半導體元件整合所形 DRAM或快閃記憶體等的LSI構造，亦即電路2。 、另外，在半導體裝置100上，以貫通基板i的方式設置了貫 通電極3丨（TSV) ’貫通電極31的一部分從基板1的背面（電路 2形成面的相反侧的面）突出。 貫通電極31包含由Cu等導電性金屬所形成的柱狀栓塞13以 及包覆栓塞13的TaN等的阻隔膜π。
5 201216411 再者’在貫通電極31與基板1之間，以覆蓋貫通電極31且 與基板1接觸的方式設置了 Si3N4等的絶緣膜η。 另一方面，在基板1的背面上，以覆蓋該背面的方式形成了 SiCN 膜 20。 ^ SlCN膜20係設置在基板的背面，防止基板1產生翹曲的保 濩膜。一般而言會使用氧化矽膜或氮化矽膜作為保護膜，惟該等 膜層用在較薄的基板上會有產生龜曲的問題。詳細情況容後敘 述’惟SiCN膜20由於其内部應力會因為膜中的c量而改變，故 可藉由控制成膜時的C量使晶圓的翹曲實質上為〇。 以下’參照圖2〜圖1〇説明半導體裝置1〇〇的製造方法。 首先’準備如圖2所示的基板1。 -使靜基板等作為級丨，在絲社整合未經圖 不之半導體70件，以形成電路2的全部或一部份。 I八準:厚度775叫的矽基板作為基板1，並在其表面上 整合+導體請以形成DRAM或快閃記憶體等LSI構造的電路2。 ㈣1圖u 3所示的’在基板1用來形成TSV構造（貫通電 極31)的雜上，從表面打出既定數量的開孔。 〜孔1G敝長料咖咖㈣左右，深度約為卿m
可用例如侧來形賴孔。具體*言，開孔可 3m皮激發虹/八電衆钱刻器或915耻微波激發MSEP n lwa ltati<)nPlasma)電漿侧器來進行。 該專蝕刻益，利用非水溶液的陽極氧 水分。 ΐ全部抽乾的話，則抗蝕劑與幻的蝕刻選擇比合變成50〜 1〇〇。因此’抗鋪的臈厚*2卿左右比較好 =緣，成方法，例如:將:直内=，在成其絶二 ^_1VapOTD_tiGn ’化學氣她積）方式職化= S： 201216411 -板的二微波激彻段喷淋 的混合氣齡蹄齡驟m板 =倾狀卿氣體 Si3N4膜。 $接者，在該虱化矽上以CVD方式形成 驟l/t使用915ΜΗΖ微波激發的2段喷淋板的 水處理裝置，從上段喷淋板喷出&氣體以及 體的混合氣體^ 在此接在絶緣臈11的内表面上形成阻隔膜12。 ί 9成 的裝置相同，使用915應2微波激發 s 處雜置’從上段喷淋板喷出-= 體合氡體，從τ段喷淋板喷出TaC1;等的氣體， i 上^(通方式形成施膜作為阻隔膜12。該阻隔膜 接ί防膜之Cu向半導體基板擴散的導電性阻隔膜。 开in Hi示的，以填埋開孔10的方式在開孔10内部 2栓塞13。在此讓電流_ TaN膜（阻隔膜12)，以蘭膜 (TSV電極）作為栓塞13。 取的金屬柱 如疋，分別在各開孔10内形成TSV電極（貫诵雷搞 接著，如圖7所示的，從基板i的背面侧進行^ 薄至既定厚度’並使TaN膜12以及絶緣膜^ 的1 電極（栓塞13)的底面側的一部分從基板i的背面突出 出）。 關於姓刻’係將基板1的表面侧貼合在多孔質的玻璃基板％ C東^應化製品）上，以使用hf/hn〇3/CH3C〇〇h/H2〇溶液 的超尚速濕式蝕刻，對775μηι的矽基板1的背面侧，以 mm的速度’進行約i分鐘的餘刻。最後基板i的厚度變成瓜 〜3〇μιη左右。此時，s^N4膜（絶緣膜u)不會受到蝕刻史 濕式蝕刻便可只讓基板1變薄。 由圖7可知，Τ3Ν膜（阻隔膜12)以及ShN4膜（絶緣膜n ) 201216411 所f覆的Cu的栓塞13的底面側從變薄至2〇μιη〜 的背面侧突出。 如圖8所不的’在基板1的背面上以CVD方式形成 u 而言，sicNM 20，係使用915廳微波激發的2段喷淋 理裝置，從上段喷淋板喷仏氣體以及‘ Γ ^下t喷淋板喷出&氣體、卿氣體以及SiH 3) 3氣體的混合氣體，在l〇〇°C左右的溫度下成膜。 結果，便可完全控制晶圓（基板丨.）的鍾曲。 Μ ’就SiCN而言，由於讓c量在1G原子％前後便可使内 縣力由正變負，故控制c量便可找到使晶圓的趣曲為零的條件。 具體而言，SiCN膜20的内部應力，如圖1〇的白 的，藉由調節例如SiH. (CH3) 3氣體的濃度（亦即，藉色=膜、 中的C含有量），便可實質上為〇。 猎由調郎膜 關於SiCN的組成，在氮化石夕_4中添加i 〇%以下 好的，惟添加2原子％〜4〇原子％的c也是可以。 另外’ SiCN ’除了作為保護膜的特性優異之外，更呈 導性優異_性。姆於SiQ2的祕導率為， SiCN為70W/m/Kelvin明顯大很多。 因此，在基板1的背面上形成SiCN膜2〇，如上 同時達到完整的保護膜功能與晶圓的趣曲控制這兩個目的。' 另外’在形成SiCN時，如圖8所示的，在TaN膜（ 以及_膜（絶緣膜⑴所包覆的Cu的 ^ = 表面上也會形成SiCN膜20。 W大4 之後，從玻璃基板33將晶圓（基板丨）剝除。另 璃基板33就這樣放著的話會被濕式蝕刻用的； CHfOOH/H：2。溶液-點一點地侧掉，故會在其露3 ，加了⑽的YA並在70(rc左右锻燒成圖中未顯示 ^ 覆盘該露出©，讓侧停止。 以 另外，在剝除玻璃基板33之前，如圖9所示的，在基板1的 201216411 月面側，於SiCN膜20 (形成於石夕基板背面的部分）的表面上塗 佈抗韻劑，將貫通電極31的表面（從基板1的背面突出的阻隔膜 12f表面）所包覆的SiCN膜20以及Si：^4膜（絶緣膜U)蝕刻 除去。 利用以上的步驟便可完成如圖1所示的半導體裝置1〇〇。
如是，根據本實施態樣，半導體裝置1〇〇係以下述方式製造： 在基板1上形成開孔，在開孔10内形成絶緣膜11、阻隔膜12、 ΐϋ對基板1的背面進行餘刻使基板1變薄並使絶緣膜1卜 膜二:2、检塞13突出來，之後，在基板1的背面上形成sicN 、因此，根據本發明的具有TSV構造的半導體裝置的製造方 Γ使在__使基板1㈣的航下，也㈣防止基板1 屋生趣曲。 産業利用性 亡，實施_，係針對將本發明應用於半導體震置觸的情 快門’该半導體裝置漏使用了在表面上形成有DRAM或 所基板’惟本發明並非以此為限，本發明可應用於 【圖式簡單說明】. 圖1係表示半導體裝置100的剖面圖。 圖2係表示半導體裝置100的製造步驟的剖面圖。 圖3係表示半導體裝置100的製造步驟的剖面 圖4係表示半導體裝置1〇〇的製造步驟的剖面圖。 圖5係表示半導體裝置1〇〇的製造步驟的剖面 圖6係表示半導體裝置1〇〇的製造步驟的剖面 圖7係表示半導體裝置1〇〇的製造步驟的剖面 圖8係表示半導體裝置1〇〇的製造步驟的剖面圖。 圖9係表示半導體裝置100的製造步驟的剖面 圖10係表示SiCN膜20的組成與物性（内部應力）的關係圖。 9
Ci 201216411 【主要元件符號說明】 1 .基板 2 電路（LSI構造） 10開孔 11 絶緣膜 12 阻隔膜（TaN膜） 13栓塞（導電性金屬） 20 SiCN 膜 31貫通電極 33玻璃基板 100半導體裝置

Claims (1)

  1. 201216411 七、申請專利範圍： 1、一種半導體農置的製造方法，包: 在半導體基板的表面上整合半導體元件以形成電路的至+一 部份的步驟（a ); 在該半導體基板的表面上形成開孔的步驟（b); 在該開孔的内表面上形成絶緣膜以及阻隔膜的步驟（c) ; 在該阻隔膜的内表面上，以填埋該開孔的方式形成 屬的步驟（d);. * 之後對該半導體基板的背面加工，使該半導體基板的 少，讓該導電性金屬、該阻隔膜以及該絶緣膜從該背面突出二乎 驟（e);以及之後在該半導體基板的背面上設置SiCN膜的步^ 2、 如申請專利範圍第丨項之半導體裝置的製造方法，复 該步驟⑴係控繼SiCN賴組成以使該半導縣板的^ 質上為零的步驟。 3、 如申請專利細第1或2項之半導雜置的製造方法，立 =成隠膜的步驟，該卿，膜具有在^ 中添加2原子％〜40原子％的c的組成。 4、 如憎專利範圍第丨至3項中任—項之半導體裝置的製造 方法’其中’該步驟⑷係對該半導體基板 該半導體基板的厚度減少的步驟。 5、 如申請專利範圍第i至4項中任—項之半導體裝 3 步驟⑷係將該半導體基板的表面側貼合在ί孔 i的玻璃基板上’對辭導縣板的背面進行赋烟，使 導體基板的厚度減少的步驟。 ° 6、 如申請專利範圍第i至5項中任—項 方法，其中，該步驟⑴係以CVD方式在該半^置的# 上形成懸膜之後，將從該背面突出的該阻隔 的該絶緣膜以及該SiCN麟摘倾。 祕 201216411 、7、如申請專利範圍第1至6項中任一項之半導 方法，其中，該半導體基板為Si基板，該步驟（c)係^該門= 内表面氮化以形成該絶緣膜的至少一部份的步驟。’、^的 8、 如申請專利範圍第丨至7項中任—項之 生 2: &含形成導電性阻峨作為該=茲 金包屬 =導電性阻隔膜作為通電機構並利用 9、 如申請專利範圍第i至7項中任一項之 ~@_彡_絶緣膜之後，麟絶^ 上形成TaN膜作為該阻隔膜的步驟。 1〇、如”專利制第9項之半導體裝㈣製造方法， =驟⑷係以該蘭臈為晶種層，在該侧 ^ 該導電性金屬的步驟。 默电锻Ui作為 11、 一種半導體裝置，包含·· 半V體基板，其在表面上形成有電路； 香而二!?電極’其胃通斜導體基板且—部分從該半導體基板的 者面犬出；以及SCN膜，其覆蓋該半導體基板的背面。 12、 如申請專利範圍第11項之半導體裳置，1中， 該SiCNj有使該轉體基板_曲實質上為零的: 13、 如申請專利範圍第u ，，具有在，添加2原子％〜4〇m^中成該 14、 如申請專利範圍第u至13項中任—項之半導體裝^， 霜該^極被對該貫通電極的材料具有阻隔作用的阻隔膜 與該半導體基板接觸的絶緣膜所覆蓋。 a板為s. 减第14項之半導體裝置，其中，該半體 土板為Si基板’該絶緣膜包含幻凡膜。 的：為ΪΓ’專利範圍第14項之半導體裝置，其中，該阻隔膜 12
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