CN112204737B - 闪存堆叠系统和方法 - Google Patents

闪存堆叠系统和方法 Download PDF

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CN112204737B
CN112204737B CN201980036081.1A CN201980036081A CN112204737B CN 112204737 B CN112204737 B CN 112204737B CN 201980036081 A CN201980036081 A CN 201980036081A CN 112204737 B CN112204737 B CN 112204737B
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stack
wafers
wafer
traces
dielectric material
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CN112204737A (zh
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B·哈巴
L·默罕默德
J·A·德拉克鲁斯
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Adeia Semiconductor Technologies LLC
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Invensas LLC
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Abstract

以晶圆对晶圆方式执行的三维堆叠技术减少了生产时的机器运动。晶圆使用金属迹线进行处理，并且在切成单独管芯堆叠之前进行堆叠。堆叠的每个层的迹线经由无电解镀而互连。

Description

闪存堆叠系统和方法
技术领域
以下描述涉及用于制造集成电路的硅晶圆的堆叠。更具体地，以下描述涉及堆叠的多层晶圆以及连接用于集成电路、印刷电路板或存储器部件的各个层的过程。
背景技术
通常，微电子学涉及使用可以形成为单个单元的诸如硅晶圆之类的薄半导体材料。这样的元件常常用于随后可以安装到印刷电路板(PCB)上的集成电路(IC)。在过去的几十年中，微电子领域迅速发展，需要增加存储装置或存储器的容量并且减小尺寸。附加地，成本降低由于极大地影响了新微电子技术和过程的开发而受到持续关注。
对性能更高、容量更大和成本更低的消费者产品和应用的需求推动了对更小巧且功能更强大的微电子部件的需求。对更小尺寸的这种不断增长的需求导致了3D堆叠的开发。通常，3D堆叠涉及以垂直方式堆叠微电子部件并且在各层之间施加垂直互连。传统上讲，垂直互连方法已经包括了硅通孔(TSV)、引线键合和倒装芯片方法，这些方法使得制造商能够生产出容量更大且占位面积更小的IC。
随着对尺寸更小且容量更大的需求的增加，性能、容量和成本之间的平衡是开发微电子部件时的挑战。由于制造时间和所用材料成本的增加，所以已经造成了当前用于堆叠和键合的方法的成本的增加。
发明内容
根据各个实施例的系统和方法提供了一种晶圆级的闪存堆叠，并且随后采用三维格式互连晶圆。在若干个实施例中，三维堆叠包括具有凹槽的多个晶圆，该凹槽被配置为位于切片道内并且填充有电介质材料，还被配置为借助于无电解镀在多个接触焊盘之间互连。
许多实施例涉及一种芯片级堆叠，具有多个减薄的芯片，该多个减薄的芯片中的每个减薄的芯片具有第一表面以及与第一表面相对的第二表面以及多个侧表面，其中至少一个侧表面由从第一表面延伸到第二表面的电介质材料覆盖；多个键合层，该多个键合层设置在多个减薄的芯片的每个减薄的芯片之间；多个导电焊盘，该多个导电焊盘设置在多个减薄的芯片的每个减薄的芯片的第一表面上；多个导电迹线，该多个导电迹线位于第一表面上，该多个导电迹线通过印刷、直接成像和/或模版印刷而被设置，其中多个导电迹线中的每个导电迹线与设置在第一表面上的多个导电焊盘中的至少一个导电焊盘电接触并且被配置为在由电介质材料覆盖的至少一个侧表面的电介质材料上延伸，并且其中多个导电迹线中的每个导电迹线在多个减薄的芯片中的每个减薄的芯片上具有至少一个对应迹线；以及无电解镀连接，该无电解镀连接至少部分地设置在电介质材料上，并且被配置为将多个减薄的芯片中的每个减薄的芯片之间的多个印刷导电迹线与对应迹线连接。
在其他实施例中，电介质材料被配置为在大小和形状上相等。
在又其他实施例中，电介质材料被配置为在多个芯片之间具有多种形状和大小。
在其他实施例中，电介质材料的CTE与多个减薄的芯片的CTE类似。
在其他实施例中，多个减薄的晶圆或芯片中的每个减薄的晶圆或芯片上的印刷导电迹线之间的距离大于减薄的晶圆或芯片与键合层或粘合剂层的组合厚度。
在再其他实施例中，附加的元件被键合到堆叠的顶部表面，并且被配置为通过附加的无电解镀连接而连接到多个减薄的芯片的迹线。
在再又其他实施例中，堆叠的顶部表面被配置为适应芯片级封装格式。
在其他实施例中，芯片级格式是倒装芯片格式。
在再其他实施例中，用于无电解镀连接的金属选自由以下各项组成的组：镍、铜、银、以及金。
许多实施例包括一种用于生产微电子堆叠的方法，其中多个晶圆具有第一面和第二面。多个晶圆各自具有预先确定的路径图案以及设置在其上的预先确定的数目的切片道。沿着切片道去除多个晶圆的一部分，使得在晶圆的主体的切片道内形成凹槽，该凹槽从第一面但是仅部分延伸通过主体，使得凹槽不会延伸到第二面。电介质材料设置在凹槽内。通过印刷、直接成像和/或模版印刷在电介质材料上设置多个金属迹线。迹线与路径中的至少一个路径互连。从多个晶圆的第二面去除材料，使得材料的去除减小了多个晶圆的厚度以暴露形成在其中的凹槽。向晶圆的面施加粘合剂层。堆叠多个晶圆，使得形成在其中切片道以及凹槽根据预先确定的图案对齐，从而生产晶圆堆叠。然后，沿着预先确定的切片道对晶圆堆叠进行切片，使得切片对堆叠的垂直边缘进行暴露。暴露的垂直边缘包括电介质材料和金属迹线。然后，金属迹线沿着垂直边缘通过无电解镀而被互连。
在其他实施例中，切割的晶圆堆叠通过带拉伸分开。
在其他实施例中，电介质材料包括环氧树脂和二氧化硅的混合物。
在其他实施例中，晶圆堆叠还经由选自焊料键合和无电解镀组成的组的方法键合到集成电路。
在还其他实施例中，可以去除电介质材料的一部分，从而增加或扩大无电解镀层与导电迹线之间的接触面积。
在又其他实施例中，多个电介质层可以设置在凹槽中，并且其中多个电介质层可以是有机的、无机的或两者的组合。在一些实施例中，电介质材料可以选自由以下各项组成的组：氧化硅、氮化硅、氧化铝、聚酰亚胺、环氧树脂、弹性体、以及电泳沉积的聚合物。
在一些实施例中，至少一个对应迹线可以不连接到导电焊盘。
在随后描述中对附加实施例和特征进行部分阐述，而且在查阅说明书时，对于本领域技术人员而言，这些实施例和特征部分变得显而易见，或可以通过实践所公开的主题而获悉。通过参考形成本公开的一部分的说明书和附图的其余部分，可以实现对本公开的本质和优点的进一步理解。
附图说明
参考以下附图，更全面地理解本说明书，这些附图作为本公开的各种实施例而呈现，并且不应被解释为对本公开的范围的完整叙述，其中：
图1图示了本领域中已知的晶圆级(WL)NAND堆叠方法的示例。
图2图示了根据本发明的实施例的堆叠方法的示例性实施例。
图3图示了根据本发明的实施例的堆叠方法的剖视图。
图4A图示了根据各种实施例的其中附件元件设置在堆叠的顶部表面上的晶圆堆叠。
图4B图示了根据本发明的各个实施例的闪存晶圆堆叠。
图4C图示了根据本发明的各个实施例的各种走线应用
图5A图示了根据本发明的一些实施例的晶圆堆叠与IC的键合。
图5B图示了根据许多实施例的晶圆堆叠与IC的键合。
图6A图示了根据本发明的各个实施例的导体焊盘暴露的晶圆堆叠。
图6B图示了根据本发明的各个实施例的闪存晶圆堆叠。
图6C图示了根据本发明的各个实施例的闪存晶圆堆叠。
图7A图示了根据各个实施例的具有各种走线图案的闪存晶圆堆叠。
图7B图示了根据许多实施例的闪存晶圆堆叠。
具体实施方式
结合如下文所描述的附图，可以通过参考以下具体实施方式来理解本公开。应当指出，为了说明清楚，各种附图中的某些元件可能未按比例绘制。
公开了多层微电子结构以及堆叠并生产多层微电子结构以减少制造时间和成本的系统和方法。本文中所公开的实施例涉及获得晶圆(例如，包含闪存管芯的晶圆)，该晶圆由被设计为在微电子结构内使用的合适材料制成。晶圆具有与切片道相对应的凹槽，该凹槽切入表面并且随后填充有非导电材料。许多实施例包括在减薄多个晶圆并将其键合以形成堆叠之前添加导电路径。一旦堆叠，就可以沿着切片道对晶圆进行切割或切片，并且这些晶圆分成单个管芯，以用于多种微电子结构中。
生产微电子和/或IC的传统方法通常从在硅晶圆的表面上创建或放置金属迹线或电子导电路径。这些路径通常与最终从硅晶圆上切下的单个管芯相关联。放置迹线的传统方法涉及多种技术。设置迹线的最流行方法通常通过电镀。其他方法包括：生长迹线路径，并且在晶圆上放置导电层，然后再使用化学或光产生部件的期望路径。
在这样的传统方法中，通常，硅晶圆被切成单个管芯，一旦放置了迹线，这些管芯就可以堆叠以在IC内创建三维(3D)堆叠。在大多数情况下，粘合剂层或键合层被施加到管芯，以开始堆叠。堆叠方法通常遵循拾取和放置方法，其中机器将选择单个切片管芯并且将其堆叠。机器来回移动，选择下一管芯并且将其堆叠在前一管芯上。这种堆叠通常按组进行，其中机器将创建堆叠的管芯组，然后根据期望层数和容量堆叠这些组。附加地，因为单个不良管芯会导致整个堆叠失效，所以通常在堆叠每个管芯之前先对其进行测试，以确保可行性。一旦已经堆叠了管芯，单个层需要互连以创建最终部件。
传统互连方法通常使用称为引线键合的方法。引线键合是一种方法，通过该方法，金线物理键合在每层之间，从而将用于堆叠的管芯的每个层的各个迹线路径互连。这与图1所示的WL NAND堆栈类似。其中引线键合或引导结构110连接堆叠的管芯120中的每个堆叠的管芯。业界已经引入的其他方法包括使用TSV。
TSV通常涉及使用导电材料对通孔进行电镀。通孔贯穿管芯的各个层之间的晶圆衬底，并且当被电镀时，创建电连接。
已经证明，这种传统堆叠和互连方法比期望的堆叠和互连方法昂贵。如所提及的，例如，使用拾取和放置方法的管芯至管芯的堆叠需要更多的机器运动，这可能导致处理低效并且总体制造成本增加。更进一步地，这些方法通常包括横截面类似于如图1所示的阶梯轮廓的堆叠方法。阶梯轮廓130最终会增加堆叠的x-y维度特点，这在许多方面中与通过3D堆叠减小微电子器件的尺寸的期望结果相反。这种堆叠方法增加了总成本，并且没有最终产品的期望结果。
附加地，借助于引线键合甚至TSV的互连方法增加了总体制造成本。由于其在传输低压信号方面的可靠性和耐腐蚀性能，金通常已成为包括引线键合在内的大多数互连的选择材料。金价格的波动导致了互连管芯的这些方法的成本增加。
已经使用了用于切片和互连的其他技术，这些技术被证明没有成本效益，因此还没有成为工业标准的生产方法。例如，典型的Shell-case制造方法可能包括：使用切割晶圆的“V”形切片道。“V”形切片道暴露晶圆的边缘以供键合。随后，通过在边缘处电镀导电层或光刻印刷导电层来执行该互连。因而，用于分散迹线以及堆叠并互连层的新方法对于具有成本效益的部件的未来开发和生产至关重要。
根据许多实施例，图2至图5图示了多层微电子结构和堆叠晶圆级管芯的方法。图2图示了本文中所公开的过程的示例性实施例的流程图，而图3至图5以图解方式图示了根据本发明的许多实施例的堆叠和互连方法。
图2的示意图对其中生成晶圆级微电子部件和堆叠的示例性过程进行了总结。图2的每个框表示根据许多实施例的3-D闪存晶圆堆叠的生产过程中的步骤。图3中还通过各个部件在图2的方法步骤期间的剖视图图示了对应步骤。
关于图2所示的流程，现在转到图3，对许多实施例进行了说明。在这样的实施例的步骤210中，整个半导体晶圆310根据最终产品的期望特性来选择。根据一些实施例，在步骤215中建立用于放置导电路径和切片道的预先确定的图案。
一旦已经建立了预先确定的路径，就可以在步骤220中沿着切片道在晶圆的表面中切割出凹槽320。凹槽的维度根据晶圆和管芯的期望结果来仔细确定。根据许多实施例，凹槽不是延伸穿过晶圆的整个厚度，而是在预先确定的距离处停止，使得可以填充凹槽。在步骤230中，沿着切片道放置的凹槽可以填充有非导电电介质材料330。
根据许多实施例，下一步骤240包括：将导电路径340设置在晶圆的表面上。导电路径或迹线340以它们在电介质材料330上延伸的方式设置，使得在制造过程的后一部分中，暴露迹线340的边缘以供键合。
步骤250继续根据许多实施例的过程，通过该过程，可以减薄晶圆，使得从晶圆的底部部分去除材料。去除材料的程度应使填充有电介质材料的先前放置的凹槽暴露出来。一旦减薄了晶圆，则在许多实施例中，紧接着步骤260A，其中可以对一个或多个晶圆施加粘合剂层350，使得可以堆叠并键合减薄的晶圆。只要在堆叠晶圆之前，放置粘合剂层，粘合剂层是放置在晶圆的顶部上还是底部上无关紧要。
在许多实施例中，上述过程可以重复多次，如步骤260B所示，以堆叠每个晶圆做准备。步骤270包括：堆叠准备好的晶圆360并且对它们进行切片做准备。许多实施例可以包括施加带层370以辅助后续处理。
如本文中的实施例中所公开的，因为堆叠了其上暴露有若干个管芯的整个晶圆，所以晶圆级堆叠有助于降低生产成本。处理晶圆的一个或多个机器不会具有如先前所述的拾取和放置方法中那样多的运动。例如，可以堆叠一组16个晶圆，最终生产若干个堆叠的管芯，并且只需要机器移动这些堆叠的管芯16次以供放置晶圆，而不是进行次数为16乘以管芯的总数的移动。晶圆级堆叠显着提高了微电子制造效率。
在根据许多实施例的步骤290中，沿着切片道对晶圆进行切片，使得在晶圆的切片的部分之间形成空间380。根据一些实施例，分离可以包括带拉伸，以增加切片后的分离。一旦进行了切片，垂直堆叠的层留下暴露的边缘，从而暴露电介质材料以及每个晶圆层的迹线，使得每个层可以互连。
根据许多实施例，互连步骤295涉及通过无电解镀(electroless plating)而键合晶圆层中的每个晶圆层的过程。无电解镀不涉及使用层间的引线键合或TSV的电镀。这是一种自动催化反应，其中化学浴用于将金属放置到某个衬底或基底上。化学浴通常包括还原剂，该还原剂用于将金属离子键合到衬底。无电解镀的使用减少了产生互连所需的金属量。附加地，无电解镀防止腐蚀和磨损。因此，使用无电解镀形成互连键合是对之前的方法的改进，因为它使用的材料更少并且降低了总体生产成本。
凹槽和电介质的实施例
根据许多实施例，如图3所示，在步骤270至295中，凹槽320在堆叠的微电子器件的多个层之间是一致的；其中示出了：在每个层中，在每个对应凹槽320中设置相似量的电介质材料330。在其他实施例中，如图4B所示，凹槽330A的尺寸可以有所不同。根据一些实施例，可能希望根据将在每个晶圆上生产的单个管芯的期望特点来使凹槽宽度发生变化。在其他情况下，可以基于凹槽相对于切割路径的宽度来适应未对准。然而，如图3和图4B所示，在整个堆叠和随后的通过无电解镀进行的互连中，暴露的电介质和走线材料的垂直边缘在Y方向上没有发生改变。在先前所提及的方法中，Y维度可能逐渐增加，如图1中的阶梯横截面所示。本文中所公开的实施例示出了堆叠的Y维度没有变化，从而即使在堆叠内具有大小不同的管芯的情况下，也减小了优选的堆叠方法的总体堆叠尺寸。
根据许多实施例，凹槽中设置的电介质材料应足以覆盖晶圆材料中凹槽的所有表面。图4C图示了其中以确保凹槽的所有表面都被电介质材料330覆盖的方式设置电介质材料330的各种实施例。
根据许多示例性实施例的电介质材料应当被配置为具有低热膨胀系数(CTE)。材料的CTE是加热时材料膨胀的速率。传统上讲，与例如铜的CTE相比较，PCB中使用的材料的CTE较低。当晶圆经历业界中典型的各种处理步骤时，该晶圆可能暴露于多种加热和冷却循环。因此，电介质的CTE越低或越接近晶圆310的CTE，它就越难以在处理过程期间破坏或失去其键合，并因此保留稍后设置在其上的迹线。
例如，硅晶圆的CTE通常为3-4ppm/℃，而依据其成分，电介质的CTE可能更高。根据许多实施例，电介质330可以由粘合剂和二氧化硅颗粒组成，以帮助将电介质330的CTE降低为更接近晶圆材料的CTE。
迹线的实施例
如图3至图4C所示，根据许多实施例，迹线可以分散在电介质材料上。根据许多实施例，迹线分散在电介质上，使得在后续处理或管芯切割时，迹线的边缘会被暴露向被放置在堆叠晶圆之间的互连。
迹线340的传统分散方法的成本已引起业界关注，从而导致需要改进的创建迹线方法。许多实施例结合了把迹线放置在晶圆上的现有技术的丝网印刷方法。如图4C所示，可以使用在晶圆上把迹线设置到电介质材料上方的丝网印刷方法或模版印刷方法。如图4C所示，在许多实施例中，与丝网印刷和模板印刷方法在Z方向上产生的迹线相比，丝网印刷和模板印刷方法分别在X维度和Y维度上产生的迹线可以更长且更宽。
根据许多实施例，丝网印刷方法能够产生维度受控的迹线，该迹线将提供优异的导电性能并且与本文中所描述的附加堆叠步骤一起良好工作。根据许多实施例，印刷迹线是一种优选方法。与传统光刻和电镀方法相比，印刷迹线的关键优势在于节省了材料成本。
堆叠和无电解镀的实施例
如图4A和图5A和图5B所示，可以通过各种实施例对晶圆的堆叠进行说明。图4A图示了在许多实施例中，附加元件410可以添加到堆叠，使得仅增加整个堆叠的Z尺寸。处理这样的附加元件410与处理堆叠中的闪存晶圆的类似之处在于：在该附加元件410中，可以切割填充有电介质的凹槽并且在其上设置迹线。随后，许多实施例可以使用其他无电解镀以将附加元件410电键合到该堆叠的剩余部分上。
图5A和图5B图示了各种实施例，其中堆叠可以键合到IC或其他部件。图5A图示了借助于焊接技术将堆叠键合到IC或其他部件的方法，该焊接技术在业界中司空见惯。相比之下，图5B图示了将堆叠无电解镀到IC的节省成本的键合方法。
根据许多实施例，无电解镀依据生产水平和期望键合工艺由用于堆叠或整个部件的化学浴组成。在许多实施例中，化学浴可以包括来自镍、银、铜或金的金属离子。
如图6A至图6C所示，根据一些实施例，晶圆堆叠可以以芯片级封装(CSP)格式配置。CSP格式是如下的格式：发生堆叠使得端级管芯被配置为在可直接表面安装的封装中直接被安装到PCB。在这样的封装中，堆叠的最终表面可能已经暴露了导体焊盘610，该导体焊盘可以配置有导电凸块620或焊料凸块630。最终管芯封装640可以通过使凸块与PCB或IC上的对应焊盘对齐来直接安装到PCB或IC。这样的过程也称为其中完成的堆叠被翻转并且连接到PCB或IC的倒装芯片。
根据许多实施例，迹线可以以各种图案分散在单个管芯中的每个单个管芯上。例如，图7A图示了根据本发明的许多实施例的不同的迹线图案。根据许多实施例，从晶圆上切下的单个管芯在切割之前其上已经设置有导电焊盘710。在许多实施例中，导电焊盘710需要迹线340，该迹线340连接到并且指向电介质材料330或切片道。
图7A还图示了在许多实施例中导电焊盘710可能需要与常规迹线路径340结合的局部迹线路径340A。当根据本文中所描述的实施例堆叠晶圆时，每个导电焊盘710需要连接到闪存晶圆堆叠的每个层。因而，导电焊盘710在堆叠晶圆中的每个堆叠晶圆上的导体焊盘的对应位置处可能需要局部迹线340A。例如，图7A中的顶部晶圆图示了与下部晶圆不同的迹线图案。具有不同迹线图案的导电焊盘710需要局部迹线340A与上层迹线相对应，使得其连接到所有的下层晶片(waver)。同样，下部晶圆(这些下部晶圆在对应位置中具有焊盘，这些焊盘具有不同的迹线图案)需要在顶部晶圆上的局部迹线，以将这些下部晶圆连接到顶部晶圆。这样的连接确保了在堆叠中的迹线之间维持适当间距。
晶圆的间距是指迹线之间的间隔。在图7B中，Z维度间距用“t”描绘，而X维度和Y维度分别用“r”和“s”描绘。迹线之间的Z维度与单个晶圆和粘合剂层的组合厚度相对应。为了本文中所描述的系统和方法，可以配置许多实施例，使得X维度和Y维度的间距大于Z维度的间距，这样的关系可以由等式t<r或t<s来说明。根据许多实施例，维持“t”与“s”或“r”之间的关系对于确保堆叠的适当功能必不可少。
等同原则
为了说明和描述的目的，已经给出了本发明的描述。并不旨在穷举本发明或将本发明限制为所描述的精确形式，并且根据上述教导，许多修改和变型是可能的。选择和描述实施例是为了最好地解释本发明的原理及其实际应用。该描述使得本领域的其他技术人员能够以各种实施例和适于特定用途的各种修改来最佳地利用和实践本发明。本发明的范围由所附权利要求书限定。

Claims (34)

1.一种芯片堆叠，包括：
多个减薄的芯片，其中所述多个减薄的芯片中的每个减薄的芯片具有第一表面以及与所述第一表面相对的第二表面以及多个侧表面，其中所述多个减薄的芯片中的每个减薄的芯片的至少一个侧表面由从所述第一表面延伸到所述第二表面而未延伸到所述第一表面之外且未延伸到所述第二表面之外的电介质材料覆盖；
多个键合层，设置在所述多个减薄的芯片中的每个减薄的芯片之间；
多个导电焊盘，设置在所述多个减薄的芯片的每个减薄的芯片的第一表面上；
多个导电迹线，设置在所述第一表面上，其中所述多个导电迹线中的每个导电迹线与设置在所述第一表面上的所述多个导电焊盘中的至少一个导电焊盘电接触，并且在由所述电介质材料覆盖的所述至少一个侧表面的所述电介质材料上延伸，并且其中所述多个导电迹线中的每个导电迹线在所述多个减薄的芯片中的每个减薄的芯片上具有至少一个对应迹线；以及
无电解镀连接，至少部分地设置在所述电介质材料上，并且将所述多个减薄的芯片中的每个减薄的芯片之间的所述多个导电迹线与所述对应迹线连接。
2.根据权利要求1所述的芯片堆叠，其中所述多个减薄的芯片中的每个减薄的芯片中的所述电介质材料在大小和形状上相等。
3.根据权利要求1所述的芯片堆叠，其中所述多个减薄的芯片中的每个减薄的芯片中的所述电介质材料在所述多个减薄的芯片中的每个减薄的芯片之间具有变化的大小和形状。
4.根据权利要求1所述的芯片堆叠，其中所述电介质材料的热膨胀系数与所述多个减薄的芯片的热膨胀系数类似。
5.根据权利要求4所述的芯片堆叠，其中所述电介质材料能够选自由以下各项组成的组：氧化硅、氮化硅、氧化铝、聚酰亚胺、环氧树脂、弹性体、以及电泳沉积的聚合物。
6.根据权利要求5所述的芯片堆叠，其中所述电介质材料还包括多个层，其中至少一个层是有机材料。
7.根据权利要求5所述的芯片堆叠，其中所述电介质材料还包括多个层，其中至少一个层是无机材料。
8.根据权利要求1所述的芯片堆叠，其中所述多个减薄的芯片中的至少一个减薄的芯片上的所述对应迹线中的至少一个迹线未连接到导电焊盘。
9.根据权利要求1所述的芯片堆叠，其中所述多个减薄的芯片的每个减薄的芯片上的所述导电迹线之间的距离大于所述减薄的芯片和键合层的组合厚度。
10.根据权利要求1所述的芯片堆叠，其中附加的元件被键合到所述堆叠的顶部表面，并且通过附加的无电解镀连接而连接到所述多个减薄的芯片的所述导电迹线。
11.根据权利要求10所述的芯片堆叠，其中所述附加的元件选自由衬底和另一芯片组成的组，所述另一芯片还包括与对应迹线直接相邻并且电连接到所述对应迹线的导电焊盘。
12.根据权利要求1所述的芯片堆叠，其中所述堆叠的顶部表面被配置为适应芯片级封装格式。
13.根据权利要求12所述的芯片堆叠，其中所述芯片级格式是倒装芯片格式。
14.根据权利要求1所述的芯片堆叠，其中用于所述无电解镀连接的金属选自由以下各项组成的组：镍、铜、银、以及金。
15.根据权利要求1所述的芯片堆叠，其中一些电介质材料被从至少一个导电迹线附近的区域部分地去除，使得所述无电解镀层与所述导电迹线之间的接触面积扩大。
16.一种用于生产微电子堆叠的方法，包括：
提供多个晶圆以用于生产微电子部件，所述多个晶圆具有形成其主体的第一面和第二面，所述多个晶圆各自具有预先确定的路径图案和设置在其上的预先确定的数目的切片道；
沿着所述切片道去除所述多个晶圆的一部分，使得在所述晶圆的所述主体的所述切片道内形成凹槽，所述凹槽从所述第一面仅部分地延伸通过所述主体，使得所述凹槽不会延伸到所述第二面；
在所述凹槽内设置至少第一电介质材料层，而未将所述第一电介质材料层延伸到所述第一面之外；
以一种方式在所述电介质材料上设置多个金属迹线，所述方式选自由以下各项组成的组：印刷以及直接成像；所述多个金属迹线与所述预先确定的路径图案中的至少一个预先确定的路径图案互连；
从所述多个晶圆的所述第二面去除材料，使得材料的所述去除减小所述多个晶圆的厚度以暴露形成在其中的所述凹槽；
向所述晶圆的面施加粘合剂层；
堆叠所述多个晶圆，使得形成在其中的所述切片道和凹槽根据预先确定的图案对齐，从而生产晶圆堆叠；
沿着预先确定的所述切片道对所述晶圆堆叠进行切片，使得所述切片对堆叠的垂直边缘进行暴露，其中暴露的所述垂直边缘由所述电介质材料和金属迹线形成；以及
沿着所述垂直边缘通过无电解镀而互连所述金属迹线，使得所述金属迹线被电互连通过所述堆叠的每层。
17.根据权利要求16所述的方法，其中所述粘合剂层施加到所述晶圆的所述第二面。
18.根据权利要求16所述的方法，其中所述多个晶圆中的每个晶圆的所述凹槽在大小和形状上一致。
19.根据权利要求16所述的方法，其中所述多个晶圆中的每个晶圆的所述凹槽被形成为具有不同的大小和尺寸。
20.根据权利要求16所述的方法，其中所述无电解镀中使用的所述金属选自由以下各项组成的组：镍、铜、银、以及金。
21.根据权利要求16所述的方法，其中附加的元件被键合到所述晶圆堆叠的所述面。
22.根据权利要求16所述的方法，其中所述多个晶圆中的每个晶圆上的所述金属迹线之间的距离大于所述晶圆和粘合剂层的组合厚度。
23.根据权利要求16所述的方法，还包括：在所述至少一个金属迹线附近的区域，部分地去除所述电介质材料中的一些电介质材料。
24.根据权利要求16所述的方法，其中在所述电介质材料上设置所述多个金属迹线包括模版印刷所述多个金属迹线。
25.一种用于生产微电子堆叠的方法，包括：
提供多个晶圆以用于生产微电子部件，所述多个晶圆具有形成其主体的第一面和第二面，所述多个晶圆各自在其上具有至少一个电介质区域，其中所述至少一个电介质区域从所述第一面延伸至所述第二面而未延伸到所述第一面之外且未延伸到所述第二面之外；
以一种方式在所述电介质区域上设置多个导电金属迹线，所述方式选自由以下各项组成的组：印刷以及直接成像，其中所述导电金属迹线中的每个导电金属迹线在所述多个晶圆中的每个晶圆上具有至少一个对应的迹线；
将键合层施加到所述晶圆的面；
堆叠所述多个晶圆；
沿着预先确定的切片道对晶圆堆叠进行切片，使得所述切片对堆叠的垂直边缘进行暴露，其中暴露的所述垂直边缘由所述电介质区域和所述多个导电金属迹线形成；以及
沿着所述垂直边缘通过无电解镀而互连所述导电金属迹线，使得所述导电金属迹线被电互连通过所述堆叠的每层。
26.根据权利要求25所述的方法，其中所述键合层被施加到所述晶圆的所述第二面。
27.根据权利要求25所述的方法，其中所述多个晶圆中的每个晶圆的所述电介质区域在大小和形状上一致。
28.根据权利要求25所述的方法，其中所述多个晶圆中的每个晶圆的所述电介质区域具有不同的大小和尺寸。
29.根据权利要求25所述的方法，其中所述无电解镀中使用的金属选自由以下各项组成的组：镍、铜、银、以及金。
30.根据权利要求25所述的方法，其中附加的元件被键合到堆叠的多个晶圆的表面。
31.根据权利要求25所述的方法，其中所述晶圆堆叠中的每个晶圆上的所述导电金属迹线之间的距离大于所述晶圆和键合层的组合厚度。
32.根据权利要求25所述的方法，还包括：从所述多个导电金属迹线中的至少一个导电金属迹线附近的区域中的所述电介质区域中，部分地去除一些电介质材料。
33.根据权利要求25所述的方法，其中所述键合层是键合管芯。
34.根据权利要求25所述的方法，其中在所述电介质区域上设置所述多个导电金属迹线包括模版印刷所述多个导电金属迹线。
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